Unified Coverage Report :: Group :: tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_prim_reg_we_check.u_prim_onehot_check.u_prim_onehot_check_if::prim_onehot_check_without_addr_fault_if_proxy::onehot_without_addr_fault_cg

Group : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_prim_reg_we_check.u_prim_onehot_check.u_prim_onehot_check_if::prim_onehot_check_without_addr_fault_if_proxy::onehot_without_addr_fault_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_sec_cm_0/prim_onehot_check_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_prim_reg_we_check.u_prim_onehot_check.u_prim_onehot_check_if	100.00	1	100	1	64	64

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Group Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_prim_reg_we_check.u_prim_onehot_check.u_prim_onehot_check_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

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Summary for Group Instance tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_prim_reg_we_check.u_prim_onehot_check.u_prim_onehot_check_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_prim_reg_we_check.u_prim_onehot_check.u_prim_onehot_check_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_onehot_enable_fault	1	0	1	100.00	100	1	1	0
cp_onehot_fault	1	0	1	100.00	100	1	1	0

Summary for Variable cp_onehot_enable_fault

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_onehot_enable_fault

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
hit	21	1		T12	5		T16	5		T17	5

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Summary for Variable cp_onehot_fault

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_onehot_fault

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
hit	29	1		T12	5		T16	5		T17	5