Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	20763627	1		T15	8535		T26	113		T1	277769
full_word	7134349	1		T15	1845		T26	2358		T1	2663

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	27897656	1		T15	10360		T26	2471		T1	280432
auto[TlIntgErrCmd]	114	1		T15	11		T192	8		T213	4
auto[TlIntgErrData]	110	1		T15	1		T192	4		T213	10
auto[TlIntgErrBoth]	96	1		T15	8		T192	8		T213	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	23781104	1		T15	8308		T26	1273		T1	278633
auto[1]	4116872	1		T15	2072		T26	1198		T1	1799

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	20150228	1		T15	7787		T26	113		T1	277476
auto[TlIntgErrNone]	partial	auto[1]	613110	1		T15	733		T1	293		T2	741
auto[TlIntgErrNone]	full_word	auto[0]	3630745	1		T15	513		T26	1160		T1	1157
auto[TlIntgErrNone]	full_word	auto[1]	3503573	1		T15	1327		T26	1198		T1	1506
auto[TlIntgErrCmd]	partial	auto[0]	43	1		T15	2		T192	5		T213	2
auto[TlIntgErrCmd]	partial	auto[1]	61	1		T15	6		T192	3		T213	2
auto[TlIntgErrCmd]	full_word	auto[0]	2	1		T15	1		T330	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	8	1		T15	2		T278	1		T248	1
auto[TlIntgErrData]	partial	auto[0]	47	1		T15	1		T192	1		T213	6
auto[TlIntgErrData]	partial	auto[1]	48	1		T192	3		T213	3		T237	2
auto[TlIntgErrData]	full_word	auto[0]	5	1		T280	1		T248	1		T331	2
auto[TlIntgErrData]	full_word	auto[1]	10	1		T213	1		T278	2		T281	1
auto[TlIntgErrBoth]	partial	auto[0]	31	1		T15	3		T192	1		T213	2
auto[TlIntgErrBoth]	partial	auto[1]	59	1		T15	3		T192	6		T213	4
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T15	1		T192	1		T278	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1		T15	1		T248	1		T332	1

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	24757	1		T15	16		T27	80		T165	1274
full_word	4205555	1		T15	1		T2	16097		T3	5

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4230010	1		T2	16097		T3	5		T6	415
auto[TlIntgErrCmd]	94	1		T15	3		T192	4		T213	5
auto[TlIntgErrData]	116	1		T15	7		T192	6		T213	5
auto[TlIntgErrBoth]	92	1		T15	7		T192	9		T213	10

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	4200382	1		T15	5		T2	16097		T3	5
auto[1]	29930	1		T15	12		T27	112		T165	1430

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1562	1		T27	2		T165	73		T166	8
auto[TlIntgErrNone]	partial	auto[1]	22916	1		T27	78		T165	1201		T166	95
auto[TlIntgErrNone]	full_word	auto[0]	4198704	1		T2	16097		T3	5		T6	415
auto[TlIntgErrNone]	full_word	auto[1]	6828	1		T27	34		T165	229		T166	24
auto[TlIntgErrCmd]	partial	auto[0]	36	1		T15	1		T192	3		T213	2
auto[TlIntgErrCmd]	partial	auto[1]	51	1		T15	2		T192	1		T213	2
auto[TlIntgErrCmd]	full_word	auto[0]	2	1		T213	1		T237	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	5	1		T278	1		T326	1		T332	1
auto[TlIntgErrData]	partial	auto[0]	42	1		T15	3		T213	3		T233	1
auto[TlIntgErrData]	partial	auto[1]	65	1		T15	4		T192	5		T213	2
auto[TlIntgErrData]	full_word	auto[0]	2	1		T192	1		T331	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	7	1		T237	1		T280	1		T281	1
auto[TlIntgErrBoth]	partial	auto[0]	33	1		T15	1		T192	3		T213	2
auto[TlIntgErrBoth]	partial	auto[1]	52	1		T15	5		T192	6		T213	8
auto[TlIntgErrBoth]	full_word	auto[0]	1	1		T333	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	6	1		T15	1		T280	3		T248	1