Unified Coverage Report :: Module :: flash_phy_core

Module : flash_phy_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.87	100.00	91.51		100.00	97.83	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[1].u_core	96.36	100.00	83.96		100.00	97.83	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core	97.87	100.00	91.51		100.00	97.83	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.36	100.00	83.96		100.00	97.83	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.83	98.00	92.74	98.97	100.00	99.31	97.98

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.26	97.67	85.11			100.00		u_eflash

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prog_data.u_prog	98.64	100.00	96.83	95.00	100.00	100.00	100.00
u_disable_buf	100.00	100.00					100.00
u_erase	97.22	100.00	88.89		100.00	100.00
u_host_arb	91.95	75.93	91.89			100.00	100.00
u_host_outstanding_cnt	100.00			100.00
u_rd	97.62	99.15	93.49	100.00		99.25	96.23
u_scramble	98.18	100.00	90.91	100.00		100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.87	100.00	91.51		100.00	97.83	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	98.00	93.30	100.00	100.00	99.31	97.98

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.26	97.67	85.11			100.00		u_eflash

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prog_data.u_prog	99.47	100.00	96.83	100.00	100.00	100.00	100.00
u_disable_buf	100.00	100.00					100.00
u_erase	97.22	100.00	88.89		100.00	100.00
u_host_arb	93.98	75.93	100.00			100.00	100.00
u_host_outstanding_cnt	100.00			100.00
u_rd	97.57	99.15	93.22	100.00		99.25	96.23
u_scramble	98.18	100.00	90.91	100.00		100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : flash_phy_core

	Line No.	Total	Covered	Percent
TOTAL		79	79	100.00
ALWAYS	154	6	6	100.00
ALWAYS	167	3	3	100.00
CONT_ASSIGN	199	1	1	100.00
CONT_ASSIGN	203	1	1	100.00
ALWAYS	206	4	4	100.00
ALWAYS	218	6	6	100.00
ALWAYS	232	6	6	100.00
CONT_ASSIGN	280	1	1	100.00
CONT_ASSIGN	283	1	1	100.00
CONT_ASSIGN	284	1	1	100.00
CONT_ASSIGN	285	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	320	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
ALWAYS	328	29	29	100.00
CONT_ASSIGN	391	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	396	1	1	100.00
CONT_ASSIGN	397	1	1	100.00
CONT_ASSIGN	398	1	1	100.00
CONT_ASSIGN	399	1	1	100.00
CONT_ASSIGN	400	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	431	1	1	100.00
CONT_ASSIGN	551	1	1	100.00
CONT_ASSIGN	579	1	1	100.00
CONT_ASSIGN	586	1	1	100.00
CONT_ASSIGN	603	1	1	100.00
CONT_ASSIGN	604	1	1	100.00
CONT_ASSIGN	605	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
154	1	1
155	1	1
156	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
167	3	3
199	1	1
203	1	1
206	1	1
207	1	1
208	1	1
209	1	1
			MISSING_ELSE
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
			MISSING_ELSE
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
280	1	1
283	1	1
284	1	1
285	1	1
290	1	1
320	1	1
324	1	1
328	1	1
329	1	1
330	1	1
331	1	1
332	1	1
334	1	1
336	1	1
337	1	1
338	1	1
339	1	1
340	1	1
341	1	1
342	1	1
343	1	1
344	1	1
			MISSING_ELSE
350	1	1
351	1	1
352	1	1
			MISSING_ELSE
359	1	1
360	1	1
361	1	1
362	1	1
			MISSING_ELSE
368	1	1
369	1	1
370	1	1
371	1	1
372	1	1
			MISSING_ELSE
377	1	1
378	1	1
391	1	1
395	1	1
396	1	1
397	1	1
398	1	1
399	1	1
400	1	1
401	1	1
418	1	1
431	1	1
551	1	1
579	1	1
586	1	1
603	1	1
604	1	1
605	1	1

---

Cond Coverage for Module : flash_phy_core

	Total	Covered	Percent
Conditions	106	97	91.51
Logical	106	97	91.51
Non-Logical	0	0
Event	0	0

 LINE       199
 EXPRESSION (host_gnt && (muxed_part != FlashPartData))
             ----1---    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6
1	1	Covered	T189,T178,T9

 LINE       199
 SUB-EXPRESSION (muxed_part != FlashPartData)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       203
 EXPRESSION (((|host_outstanding)) & ((!ctrl_fsm_idle)))
             ----------1----------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6
1	1	Not Covered

 LINE       208
 EXPRESSION (host_gnt_err_event | host_outstanding_err_event)
             ---------1--------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T189,T178,T9

 LINE       220
 EXPRESSION (host_outstanding == '0)
            ------------1-----------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T1,T2,T3

 LINE       234
 EXPRESSION ((host_outstanding == '0) && ctrl_fsm_idle)
             ------------1-----------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       234
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T1,T2,T3

 LINE       245
 EXPRESSION (host_gnt && ((!host_req_done_o)) && (host_outstanding <= flash_phy_pkg::RspOrderDepth))
             ----1---    ----------2---------    -------------------------3------------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T6,T20
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T6

 LINE       245
 EXPRESSION (((!host_gnt)) && host_req_done_o && ((|host_outstanding)))
             ------1------    -------2-------    ----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T6,T20
1	0	1	Covered	T2,T3,T6
1	1	0	Covered	T138,T139,T140
1	1	1	Covered	T2,T3,T6

 LINE       284
 EXPRESSION (host_req & host_req_rdy_o)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T6,T4
1	1	Covered	T2,T3,T6

 LINE       285
 EXPRESSION (((|host_outstanding)) & rd_stage_data_valid)
             ----------1----------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6
1	1	Covered	T2,T3,T6

 LINE       320
 EXPRESSION ((phy_req & host_req) ? rd_stage_rdy : rd_stage_idle)
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       320
 SUB-EXPRESSION (phy_req & host_req)
                 ---1---   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T149,T150,T151
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T6

 LINE       324
 EXPRESSION (req_i & host_gnt)
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T42

 LINE       339
 EXPRESSION (ctrl_gnt && rd_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T19
1	1	Covered	T1,T2,T3

 LINE       341
 EXPRESSION (ctrl_gnt && prog_i)
             ----1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T23
1	0	Covered	T1,T19,T20
1	1	Covered	T1,T3,T23

 LINE       391
 EXPRESSION ((ctrl_fsm_idle & ctrl_rsp_vld) | ((host_outstanding == '0) & host_req_done_o))
             ---------------1--------------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T138,T139,T140
1	0	Covered	T181,T190

 LINE       391
 SUB-EXPRESSION (ctrl_fsm_idle & ctrl_rsp_vld)
                 ------1------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T181,T190

 LINE       391
 SUB-EXPRESSION ((host_outstanding == '0) & host_req_done_o)
                 ------------1-----------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T138,T139,T140

 LINE       391
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (host_sel ? host_addr_i : addr_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       396
 EXPRESSION (host_sel ? FlashPartData : part_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       397
 EXPRESSION (host_sel ? host_scramble_en_i : scramble_en_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       398
 EXPRESSION (host_sel ? host_ecc_en_i : ecc_en_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       399
 EXPRESSION (ctrl_rsp_vld & rd_i)
             ------1-----   --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T19
1	1	Covered	T1,T2,T3

 LINE       400
 EXPRESSION (ctrl_rsp_vld & prog_i)
             ------1-----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T23
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T23

 LINE       401
 EXPRESSION (ctrl_rsp_vld & (pg_erase_i | bk_erase_i))
             ------1-----   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T19,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T19,T20

 LINE       401
 SUB-EXPRESSION (pg_erase_i | bk_erase_i)
                 -----1----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T74,T52
1	0	Covered	T1,T19,T20

 LINE       431
 EXPRESSION ((host_gnt_rd_err & (host_outstanding == 1'b1)) | host_outstanding_rd_err)
             -----------------------1----------------------   -----------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       431
 SUB-EXPRESSION (host_gnt_rd_err & (host_outstanding == 1'b1))
                 -------1-------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Not Covered
1	1	Not Covered

 LINE       431
 SUB-EXPRESSION (host_outstanding == 1'b1)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       434
 EXPRESSION (phy_req & (rd_i | host_req))
             ---1---   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T19
1	1	Covered	T1,T2,T3

 LINE       434
 SUB-EXPRESSION (rd_i | host_req)
                 --1-   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3

 LINE       434
 EXPRESSION (arb_host_gnt_err ? ({flash_phy_pkg::FullDataWidth {1'b1}}) : flash_rdata)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       551
 EXPRESSION (prog_calc_req ? muxed_addr[(flash_phy_pkg::BusBankAddrW - 1):flash_phy_pkg::LsbAddrBit] : rd_calc_addr)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T41

 LINE       557
 EXPRESSION (prog_calc_req | rd_calc_req)
             ------1------   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T41

 LINE       557
 EXPRESSION (prog_op_req | rd_op_req)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T41

 LINE       557
 EXPRESSION (prog_op_req ? ScrambleOp : DeScrambleOp)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T41

 LINE       579
 EXPRESSION (fsm_err | prog_fsm_err)
             ---1---   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T16,T17
1	0	Covered	T12,T16,T17

---

FSM Coverage for Module : flash_phy_core

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	7	7	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCtrl	344	Covered	T15
StCtrlProg	342	Covered	T15
StCtrlRead	340	Covered	T15
StDisable	338	Covered	T15
StIdle	352	Covered	T15

transitions	Line No.	Covered	Tests
StCtrl->StIdle	372	Covered	T15
StCtrlProg->StIdle	362	Covered	T15
StCtrlRead->StIdle	352	Covered	T15
StIdle->StCtrl	344	Covered	T15
StIdle->StCtrlProg	342	Covered	T15
StIdle->StCtrlRead	340	Covered	T15
StIdle->StDisable	338	Covered	T15

---

Branch Coverage for Module : flash_phy_core

	Line No.	Total	Covered	Percent
Branches		46	45	97.83
TERNARY	320	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	396	2	2	100.00
TERNARY	397	2	2	100.00
TERNARY	398	2	2	100.00
TERNARY	551	2	2	100.00
TERNARY	434	2	1	50.00
TERNARY	557	2	2	100.00
IF	154	4	4	100.00
IF	167	2	2	100.00
IF	206	3	3	100.00
IF	218	4	4	100.00
IF	232	4	4	100.00
CASE	334	13	13	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	320	((phy_req & host_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	395	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	396	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	397	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	398	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	551	(prog_calc_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T41
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	434	(arb_host_gnt_err) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	557	(prog_op_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T41
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	154	if ((!rst_ni))
-2-:	156	if (ctrl_rsp_vld)
-3-:	158	if (inc_arb_cnt)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T4,T42
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	167	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	206	if ((!rst_ni))
-2-:	208	if ((host_gnt_err_event | host_outstanding_err_event))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T189,T178,T9
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	218	if ((!rst_ni))
-2-:	220	if ((host_outstanding == '0))
-3-:	222	if (host_gnt_err_event)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T9,T13,T14
0	0	0	Covered	T2,T3,T6

	LineNo.	Expression
-1-:	232	if ((!rst_ni))
-2-:	234	if (((host_outstanding == '0) && ctrl_fsm_idle))
-3-:	236	if (host_outstanding_err_event)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T9,T13,T14
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	334	case (state_q)
-2-:	337	if (prim_mubi_pkg::mubi4_test_true_loose(flash_disable[FsmDisableIdx]))
-3-:	339	if ((ctrl_gnt && rd_i))
-4-:	341	if ((ctrl_gnt && prog_i))
-5-:	343	if (ctrl_gnt)
-6-:	350	if (rd_stage_data_valid)
-7-:	360	if (prog_ack)
-8-:	370	if (erase_ack)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
StIdle	1	-	-	-	-	-	-	Covered	T10,T11,T12
StIdle	0	1	-	-	-	-	-	Covered	T1,T2,T3
StIdle	0	0	1	-	-	-	-	Covered	T1,T3,T23
StIdle	0	0	0	1	-	-	-	Covered	T1,T19,T20
StIdle	0	0	0	0	-	-	-	Covered	T1,T2,T3
StCtrlRead	-	-	-	-	1	-	-	Covered	T1,T2,T3
StCtrlRead	-	-	-	-	0	-	-	Covered	T1,T2,T3
StCtrlProg	-	-	-	-	-	1	-	Covered	T1,T3,T23
StCtrlProg	-	-	-	-	-	0	-	Covered	T1,T3,T23
StCtrl	-	-	-	-	-	-	1	Covered	T1,T19,T20
StCtrl	-	-	-	-	-	-	0	Covered	T1,T19,T20
StDisable	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	Covered	T12,T16,T17

---

Assert Coverage for Module : flash_phy_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ArbCntMax_A	699314190	4321476	0	0
CtrlPrio_A	699314190	4321472	0	0
HostTransIdleChk_A	699314190	45521949	0	0
NoRemainder_A	1974	1974	0	0
OneHotReqs_A	699314190	697706012	0	0
Pow2Multiple_A	1974	1974	0	0
RdTxnCheck_A	698981774	697373596	0	0
u_state_regs_A	699314190	697706012	0	0

ArbCntMax_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699314190	4321476	0	0
T2	92728	2985	0	0
T3	5422	0	0	0
T4	0	18638	0	0
T6	31238	0	0	0
T10	2350	0	0	0
T18	3996	0	0	0
T19	221416	0	0	0
T20	11844	0	0	0
T21	4686	0	0	0
T22	7458	0	0	0
T29	4198	0	0	0
T33	0	79928	0	0
T34	0	4647	0	0
T39	0	17388	0	0
T42	0	3718	0	0
T43	0	86623	0	0
T45	0	113	0	0
T144	0	77250	0	0
T191	0	76735	0	0

CtrlPrio_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699314190	4321472	0	0
T2	92728	2985	0	0
T3	5422	0	0	0
T4	0	18638	0	0
T6	31238	0	0	0
T10	2350	0	0	0
T18	3996	0	0	0
T19	221416	0	0	0
T20	11844	0	0	0
T21	4686	0	0	0
T22	7458	0	0	0
T29	4198	0	0	0
T33	0	79928	0	0
T34	0	4647	0	0
T39	0	17388	0	0
T42	0	3718	0	0
T43	0	86623	0	0
T45	0	113	0	0
T144	0	77250	0	0
T191	0	76735	0	0

HostTransIdleChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699314190	45521949	0	0
T2	92728	32194	0	0
T3	5422	20	0	0
T4	0	214123	0	0
T5	0	15	0	0
T6	31238	525	0	0
T10	2350	0	0	0
T18	3996	0	0	0
T19	221416	0	0	0
T20	11844	50	0	0
T21	4686	0	0	0
T22	7458	0	0	0
T25	0	75	0	0
T29	4198	0	0	0
T38	0	884	0	0
T39	0	217706	0	0
T42	0	32539	0	0
T43	0	838236	0	0
T44	0	17	0	0
T45	0	544	0	0

NoRemainder_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1974	1974	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T6	2	2	0	0
T10	2	2	0	0
T18	2	2	0	0
T19	2	2	0	0
T20	2	2	0	0
T21	2	2	0	0
T22	2	2	0	0

OneHotReqs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699314190	697706012	0	0
T1	1123456	1123324	0	0
T2	92728	92610	0	0
T3	5422	5072	0	0
T6	31238	31074	0	0
T10	2350	1834	0	0
T18	3996	3854	0	0
T19	221416	221072	0	0
T20	11844	11554	0	0
T21	4686	4544	0	0
T22	7458	6016	0	0

Pow2Multiple_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1974	1974	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T6	2	2	0	0
T10	2	2	0	0
T18	2	2	0	0
T19	2	2	0	0
T20	2	2	0	0
T21	2	2	0	0
T22	2	2	0	0

RdTxnCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	698981774	697373596	0	0
T1	1123456	1123324	0	0
T2	92728	92610	0	0
T3	5422	5072	0	0
T6	31238	31074	0	0
T10	2350	1834	0	0
T18	3996	3854	0	0
T19	221416	221072	0	0
T20	11844	11554	0	0
T21	4686	4544	0	0
T22	7458	6016	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699314190	697706012	0	0
T1	1123456	1123324	0	0
T2	92728	92610	0	0
T3	5422	5072	0	0
T6	31238	31074	0	0
T10	2350	1834	0	0
T18	3996	3854	0	0
T19	221416	221072	0	0
T20	11844	11554	0	0
T21	4686	4544	0	0
T22	7458	6016	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

	Line No.	Total	Covered	Percent
TOTAL		79	79	100.00
ALWAYS	154	6	6	100.00
ALWAYS	167	3	3	100.00
CONT_ASSIGN	199	1	1	100.00
CONT_ASSIGN	203	1	1	100.00
ALWAYS	206	4	4	100.00
ALWAYS	218	6	6	100.00
ALWAYS	232	6	6	100.00
CONT_ASSIGN	280	1	1	100.00
CONT_ASSIGN	283	1	1	100.00
CONT_ASSIGN	284	1	1	100.00
CONT_ASSIGN	285	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	320	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
ALWAYS	328	29	29	100.00
CONT_ASSIGN	391	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	396	1	1	100.00
CONT_ASSIGN	397	1	1	100.00
CONT_ASSIGN	398	1	1	100.00
CONT_ASSIGN	399	1	1	100.00
CONT_ASSIGN	400	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	431	1	1	100.00
CONT_ASSIGN	551	1	1	100.00
CONT_ASSIGN	579	1	1	100.00
CONT_ASSIGN	586	1	1	100.00
CONT_ASSIGN	603	1	1	100.00
CONT_ASSIGN	604	1	1	100.00
CONT_ASSIGN	605	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
154	1	1
155	1	1
156	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
167	3	3
199	1	1
203	1	1
206	1	1
207	1	1
208	1	1
209	1	1
			MISSING_ELSE
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
			MISSING_ELSE
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
280	1	1
283	1	1
284	1	1
285	1	1
290	1	1
320	1	1
324	1	1
328	1	1
329	1	1
330	1	1
331	1	1
332	1	1
334	1	1
336	1	1
337	1	1
338	1	1
339	1	1
340	1	1
341	1	1
342	1	1
343	1	1
344	1	1
			MISSING_ELSE
350	1	1
351	1	1
352	1	1
			MISSING_ELSE
359	1	1
360	1	1
361	1	1
362	1	1
			MISSING_ELSE
368	1	1
369	1	1
370	1	1
371	1	1
372	1	1
			MISSING_ELSE
377	1	1
378	1	1
391	1	1
395	1	1
396	1	1
397	1	1
398	1	1
399	1	1
400	1	1
401	1	1
418	1	1
431	1	1
551	1	1
579	1	1
586	1	1
603	1	1
604	1	1
605	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

	Total	Covered	Percent
Conditions	106	89	83.96
Logical	106	89	83.96
Non-Logical	0	0
Event	0	0

 LINE       199
 EXPRESSION (host_gnt && (muxed_part != FlashPartData))
             ----1---    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6
1	1	Not Covered

 LINE       199
 SUB-EXPRESSION (muxed_part != FlashPartData)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       203
 EXPRESSION (((|host_outstanding)) & ((!ctrl_fsm_idle)))
             ----------1----------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6
1	1	Not Covered

 LINE       208
 EXPRESSION (host_gnt_err_event | host_outstanding_err_event)
             ---------1--------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       220
 EXPRESSION (host_outstanding == '0)
            ------------1-----------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T1,T2,T3

 LINE       234
 EXPRESSION ((host_outstanding == '0) && ctrl_fsm_idle)
             ------------1-----------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       234
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T1,T2,T3

 LINE       245
 EXPRESSION (host_gnt && ((!host_req_done_o)) && (host_outstanding <= flash_phy_pkg::RspOrderDepth))
             ----1---    ----------2---------    -------------------------3------------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T6,T20
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T6

 LINE       245
 EXPRESSION (((!host_gnt)) && host_req_done_o && ((|host_outstanding)))
             ------1------    -------2-------    ----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T6,T20
1	0	1	Covered	T2,T3,T6
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T6

 LINE       284
 EXPRESSION (host_req & host_req_rdy_o)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T4,T42
1	1	Covered	T2,T3,T6

 LINE       285
 EXPRESSION (((|host_outstanding)) & rd_stage_data_valid)
             ----------1----------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6
1	1	Covered	T2,T3,T6

 LINE       320
 EXPRESSION ((phy_req & host_req) ? rd_stage_rdy : rd_stage_idle)
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       320
 SUB-EXPRESSION (phy_req & host_req)
                 ---1---   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T6

 LINE       324
 EXPRESSION (req_i & host_gnt)
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T42

 LINE       339
 EXPRESSION (ctrl_gnt && rd_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T23
1	1	Covered	T1,T2,T3

 LINE       341
 EXPRESSION (ctrl_gnt && prog_i)
             ----1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T24
1	0	Covered	T1,T74,T76
1	1	Covered	T1,T3,T23

 LINE       391
 EXPRESSION ((ctrl_fsm_idle & ctrl_rsp_vld) | ((host_outstanding == '0) & host_req_done_o))
             ---------------1--------------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       391
 SUB-EXPRESSION (ctrl_fsm_idle & ctrl_rsp_vld)
                 ------1------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       391
 SUB-EXPRESSION ((host_outstanding == '0) & host_req_done_o)
                 ------------1-----------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       391
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (host_sel ? host_addr_i : addr_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       396
 EXPRESSION (host_sel ? FlashPartData : part_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       397
 EXPRESSION (host_sel ? host_scramble_en_i : scramble_en_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       398
 EXPRESSION (host_sel ? host_ecc_en_i : ecc_en_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       399
 EXPRESSION (ctrl_rsp_vld & rd_i)
             ------1-----   --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T23
1	1	Covered	T1,T2,T3

 LINE       400
 EXPRESSION (ctrl_rsp_vld & prog_i)
             ------1-----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T23
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T23

 LINE       401
 EXPRESSION (ctrl_rsp_vld & (pg_erase_i | bk_erase_i))
             ------1-----   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T19,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T74,T76

 LINE       401
 SUB-EXPRESSION (pg_erase_i | bk_erase_i)
                 -----1----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T74,T52
1	0	Covered	T1,T19,T20

 LINE       431
 EXPRESSION ((host_gnt_rd_err & (host_outstanding == 1'b1)) | host_outstanding_rd_err)
             -----------------------1----------------------   -----------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       431
 SUB-EXPRESSION (host_gnt_rd_err & (host_outstanding == 1'b1))
                 -------1-------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Not Covered
1	1	Not Covered

 LINE       431
 SUB-EXPRESSION (host_outstanding == 1'b1)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       434
 EXPRESSION (phy_req & (rd_i | host_req))
             ---1---   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T23
1	1	Covered	T1,T2,T3

 LINE       434
 SUB-EXPRESSION (rd_i | host_req)
                 --1-   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3

 LINE       434
 EXPRESSION (arb_host_gnt_err ? ({flash_phy_pkg::FullDataWidth {1'b1}}) : flash_rdata)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       551
 EXPRESSION (prog_calc_req ? muxed_addr[(flash_phy_pkg::BusBankAddrW - 1):flash_phy_pkg::LsbAddrBit] : rd_calc_addr)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T41

 LINE       557
 EXPRESSION (prog_calc_req | rd_calc_req)
             ------1------   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T20,T38
1	0	Covered	T3,T4,T41

 LINE       557
 EXPRESSION (prog_op_req | rd_op_req)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T20,T38
1	0	Covered	T3,T4,T41

 LINE       557
 EXPRESSION (prog_op_req ? ScrambleOp : DeScrambleOp)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T41

 LINE       579
 EXPRESSION (fsm_err | prog_fsm_err)
             ---1---   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T16,T17
1	0	Covered	T12,T16,T17

---

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	7	7	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCtrl	344	Covered	T15
StCtrlProg	342	Covered	T15
StCtrlRead	340	Covered	T15
StDisable	338	Covered	T15
StIdle	352	Covered	T15

transitions	Line No.	Covered	Tests
StCtrl->StIdle	372	Covered	T15
StCtrlProg->StIdle	362	Covered	T15
StCtrlRead->StIdle	352	Covered	T15
StIdle->StCtrl	344	Covered	T15
StIdle->StCtrlProg	342	Covered	T15
StIdle->StCtrlRead	340	Covered	T15
StIdle->StDisable	338	Covered	T15

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

	Line No.	Total	Covered	Percent
Branches		46	45	97.83
TERNARY	320	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	396	2	2	100.00
TERNARY	397	2	2	100.00
TERNARY	398	2	2	100.00
TERNARY	551	2	2	100.00
TERNARY	434	2	1	50.00
TERNARY	557	2	2	100.00
IF	154	4	4	100.00
IF	167	2	2	100.00
IF	206	3	3	100.00
IF	218	4	4	100.00
IF	232	4	4	100.00
CASE	334	13	13	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	320	((phy_req & host_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	395	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	396	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	397	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	398	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	551	(prog_calc_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T41
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	434	(arb_host_gnt_err) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	557	(prog_op_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T41
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	154	if ((!rst_ni))
-2-:	156	if (ctrl_rsp_vld)
-3-:	158	if (inc_arb_cnt)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T4,T42
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	167	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	206	if ((!rst_ni))
-2-:	208	if ((host_gnt_err_event | host_outstanding_err_event))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T9,T13,T14
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	218	if ((!rst_ni))
-2-:	220	if ((host_outstanding == '0))
-3-:	222	if (host_gnt_err_event)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T9,T13,T14
0	0	0	Covered	T2,T3,T6

	LineNo.	Expression
-1-:	232	if ((!rst_ni))
-2-:	234	if (((host_outstanding == '0) && ctrl_fsm_idle))
-3-:	236	if (host_outstanding_err_event)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T9,T13,T14
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	334	case (state_q)
-2-:	337	if (prim_mubi_pkg::mubi4_test_true_loose(flash_disable[FsmDisableIdx]))
-3-:	339	if ((ctrl_gnt && rd_i))
-4-:	341	if ((ctrl_gnt && prog_i))
-5-:	343	if (ctrl_gnt)
-6-:	350	if (rd_stage_data_valid)
-7-:	360	if (prog_ack)
-8-:	370	if (erase_ack)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
StIdle	1	-	-	-	-	-	-	Covered	T10,T11,T12
StIdle	0	1	-	-	-	-	-	Covered	T1,T2,T3
StIdle	0	0	1	-	-	-	-	Covered	T1,T3,T23
StIdle	0	0	0	1	-	-	-	Covered	T1,T74,T76
StIdle	0	0	0	0	-	-	-	Covered	T1,T2,T3
StCtrlRead	-	-	-	-	1	-	-	Covered	T1,T2,T3
StCtrlRead	-	-	-	-	0	-	-	Covered	T1,T2,T3
StCtrlProg	-	-	-	-	-	1	-	Covered	T1,T3,T23
StCtrlProg	-	-	-	-	-	0	-	Covered	T1,T3,T23
StCtrl	-	-	-	-	-	-	1	Covered	T1,T74,T76
StCtrl	-	-	-	-	-	-	0	Covered	T1,T74,T76
StDisable	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	Covered	T12,T16,T17

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ArbCntMax_A	349657095	2006971	0	0
CtrlPrio_A	349657095	2006971	0	0
HostTransIdleChk_A	349657095	22495967	0	0
NoRemainder_A	987	987	0	0
OneHotReqs_A	349657095	348853006	0	0
Pow2Multiple_A	987	987	0	0
RdTxnCheck_A	349490887	348686798	0	0
u_state_regs_A	349657095	348853006	0	0

ArbCntMax_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349657095	2006971	0	0
T2	46364	1270	0	0
T3	2711	0	0	0
T4	0	6034	0	0
T6	15619	0	0	0
T10	1175	0	0	0
T18	1998	0	0	0
T19	110708	0	0	0
T20	5922	0	0	0
T21	2343	0	0	0
T22	3729	0	0	0
T29	2099	0	0	0
T33	0	62212	0	0
T34	0	1968	0	0
T39	0	7879	0	0
T42	0	685	0	0
T43	0	33269	0	0
T45	0	34	0	0
T144	0	59431	0	0
T191	0	32651	0	0

CtrlPrio_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349657095	2006971	0	0
T2	46364	1270	0	0
T3	2711	0	0	0
T4	0	6034	0	0
T6	15619	0	0	0
T10	1175	0	0	0
T18	1998	0	0	0
T19	110708	0	0	0
T20	5922	0	0	0
T21	2343	0	0	0
T22	3729	0	0	0
T29	2099	0	0	0
T33	0	62212	0	0
T34	0	1968	0	0
T39	0	7879	0	0
T42	0	685	0	0
T43	0	33269	0	0
T45	0	34	0	0
T144	0	59431	0	0
T191	0	32651	0	0

HostTransIdleChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349657095	22495967	0	0
T2	46364	15510	0	0
T3	2711	20	0	0
T4	0	87582	0	0
T6	15619	286	0	0
T10	1175	0	0	0
T18	1998	0	0	0
T19	110708	0	0	0
T20	5922	50	0	0
T21	2343	0	0	0
T22	3729	0	0	0
T29	2099	0	0	0
T38	0	356	0	0
T39	0	107056	0	0
T42	0	15330	0	0
T43	0	432021	0	0
T44	0	17	0	0

NoRemainder_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	987	987	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

OneHotReqs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349657095	348853006	0	0
T1	561728	561662	0	0
T2	46364	46305	0	0
T3	2711	2536	0	0
T6	15619	15537	0	0
T10	1175	917	0	0
T18	1998	1927	0	0
T19	110708	110536	0	0
T20	5922	5777	0	0
T21	2343	2272	0	0
T22	3729	3008	0	0

Pow2Multiple_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	987	987	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

RdTxnCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349490887	348686798	0	0
T1	561728	561662	0	0
T2	46364	46305	0	0
T3	2711	2536	0	0
T6	15619	15537	0	0
T10	1175	917	0	0
T18	1998	1927	0	0
T19	110708	110536	0	0
T20	5922	5777	0	0
T21	2343	2272	0	0
T22	3729	3008	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349657095	348853006	0	0
T1	561728	561662	0	0
T2	46364	46305	0	0
T3	2711	2536	0	0
T6	15619	15537	0	0
T10	1175	917	0	0
T18	1998	1927	0	0
T19	110708	110536	0	0
T20	5922	5777	0	0
T21	2343	2272	0	0
T22	3729	3008	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

	Line No.	Total	Covered	Percent
TOTAL		79	79	100.00
ALWAYS	154	6	6	100.00
ALWAYS	167	3	3	100.00
CONT_ASSIGN	199	1	1	100.00
CONT_ASSIGN	203	1	1	100.00
ALWAYS	206	4	4	100.00
ALWAYS	218	6	6	100.00
ALWAYS	232	6	6	100.00
CONT_ASSIGN	280	1	1	100.00
CONT_ASSIGN	283	1	1	100.00
CONT_ASSIGN	284	1	1	100.00
CONT_ASSIGN	285	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	320	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
ALWAYS	328	29	29	100.00
CONT_ASSIGN	391	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	396	1	1	100.00
CONT_ASSIGN	397	1	1	100.00
CONT_ASSIGN	398	1	1	100.00
CONT_ASSIGN	399	1	1	100.00
CONT_ASSIGN	400	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	431	1	1	100.00
CONT_ASSIGN	551	1	1	100.00
CONT_ASSIGN	579	1	1	100.00
CONT_ASSIGN	586	1	1	100.00
CONT_ASSIGN	603	1	1	100.00
CONT_ASSIGN	604	1	1	100.00
CONT_ASSIGN	605	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
154	1	1
155	1	1
156	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
167	3	3
199	1	1
203	1	1
206	1	1
207	1	1
208	1	1
209	1	1
			MISSING_ELSE
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
			MISSING_ELSE
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
280	1	1
283	1	1
284	1	1
285	1	1
290	1	1
320	1	1
324	1	1
328	1	1
329	1	1
330	1	1
331	1	1
332	1	1
334	1	1
336	1	1
337	1	1
338	1	1
339	1	1
340	1	1
341	1	1
342	1	1
343	1	1
344	1	1
			MISSING_ELSE
350	1	1
351	1	1
352	1	1
			MISSING_ELSE
359	1	1
360	1	1
361	1	1
362	1	1
			MISSING_ELSE
368	1	1
369	1	1
370	1	1
371	1	1
372	1	1
			MISSING_ELSE
377	1	1
378	1	1
391	1	1
395	1	1
396	1	1
397	1	1
398	1	1
399	1	1
400	1	1
401	1	1
418	1	1
431	1	1
551	1	1
579	1	1
586	1	1
603	1	1
604	1	1
605	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

	Total	Covered	Percent
Conditions	106	97	91.51
Logical	106	97	91.51
Non-Logical	0	0
Event	0	0

 LINE       199
 EXPRESSION (host_gnt && (muxed_part != FlashPartData))
             ----1---    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T6,T38
1	1	Covered	T189,T178,T9

 LINE       199
 SUB-EXPRESSION (muxed_part != FlashPartData)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       203
 EXPRESSION (((|host_outstanding)) & ((!ctrl_fsm_idle)))
             ----------1----------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T6,T38
1	1	Not Covered

 LINE       208
 EXPRESSION (host_gnt_err_event | host_outstanding_err_event)
             ---------1--------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T189,T178,T9

 LINE       220
 EXPRESSION (host_outstanding == '0)
            ------------1-----------

-1-	Status	Tests
0	Covered	T2,T6,T38
1	Covered	T1,T2,T3

 LINE       234
 EXPRESSION ((host_outstanding == '0) && ctrl_fsm_idle)
             ------------1-----------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T38
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       234
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T2,T6,T38
1	Covered	T1,T2,T3

 LINE       245
 EXPRESSION (host_gnt && ((!host_req_done_o)) && (host_outstanding <= flash_phy_pkg::RspOrderDepth))
             ----1---    ----------2---------    -------------------------3------------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T6,T38
1	1	0	Not Covered
1	1	1	Covered	T2,T6,T38

 LINE       245
 EXPRESSION (((!host_gnt)) && host_req_done_o && ((|host_outstanding)))
             ------1------    -------2-------    ----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T6,T38
1	0	1	Covered	T2,T6,T38
1	1	0	Covered	T138,T139,T140
1	1	1	Covered	T2,T6,T38

 LINE       284
 EXPRESSION (host_req & host_req_rdy_o)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T6,T4
1	1	Covered	T2,T6,T38

 LINE       285
 EXPRESSION (((|host_outstanding)) & rd_stage_data_valid)
             ----------1----------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T6,T38
1	1	Covered	T2,T6,T38

 LINE       320
 EXPRESSION ((phy_req & host_req) ? rd_stage_rdy : rd_stage_idle)
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T38

 LINE       320
 SUB-EXPRESSION (phy_req & host_req)
                 ---1---   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T149,T150,T151
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T6,T38

 LINE       324
 EXPRESSION (req_i & host_gnt)
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T38
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T42

 LINE       339
 EXPRESSION (ctrl_gnt && rd_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T19,T20
1	1	Covered	T1,T2,T3

 LINE       341
 EXPRESSION (ctrl_gnt && prog_i)
             ----1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T23
1	0	Covered	T1,T19,T20
1	1	Covered	T1,T4,T24

 LINE       391
 EXPRESSION ((ctrl_fsm_idle & ctrl_rsp_vld) | ((host_outstanding == '0) & host_req_done_o))
             ---------------1--------------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T138,T139,T140
1	0	Covered	T181,T190

 LINE       391
 SUB-EXPRESSION (ctrl_fsm_idle & ctrl_rsp_vld)
                 ------1------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T181,T190

 LINE       391
 SUB-EXPRESSION ((host_outstanding == '0) & host_req_done_o)
                 ------------1-----------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T38
1	0	Covered	T1,T2,T3
1	1	Covered	T138,T139,T140

 LINE       391
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (host_sel ? host_addr_i : addr_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T38

 LINE       396
 EXPRESSION (host_sel ? FlashPartData : part_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T38

 LINE       397
 EXPRESSION (host_sel ? host_scramble_en_i : scramble_en_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T38

 LINE       398
 EXPRESSION (host_sel ? host_ecc_en_i : ecc_en_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T38

 LINE       399
 EXPRESSION (ctrl_rsp_vld & rd_i)
             ------1-----   --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T19,T20
1	1	Covered	T1,T2,T3

 LINE       400
 EXPRESSION (ctrl_rsp_vld & prog_i)
             ------1-----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T23
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T24

 LINE       401
 EXPRESSION (ctrl_rsp_vld & (pg_erase_i | bk_erase_i))
             ------1-----   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T19,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T19,T20

 LINE       401
 SUB-EXPRESSION (pg_erase_i | bk_erase_i)
                 -----1----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T74,T52
1	0	Covered	T1,T19,T20

 LINE       431
 EXPRESSION ((host_gnt_rd_err & (host_outstanding == 1'b1)) | host_outstanding_rd_err)
             -----------------------1----------------------   -----------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       431
 SUB-EXPRESSION (host_gnt_rd_err & (host_outstanding == 1'b1))
                 -------1-------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T38
1	0	Not Covered
1	1	Not Covered

 LINE       431
 SUB-EXPRESSION (host_outstanding == 1'b1)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T38

 LINE       434
 EXPRESSION (phy_req & (rd_i | host_req))
             ---1---   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T19,T20
1	1	Covered	T1,T2,T3

 LINE       434
 SUB-EXPRESSION (rd_i | host_req)
                 --1-   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T6,T38
1	0	Covered	T1,T2,T3

 LINE       434
 EXPRESSION (arb_host_gnt_err ? ({flash_phy_pkg::FullDataWidth {1'b1}}) : flash_rdata)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       551
 EXPRESSION (prog_calc_req ? muxed_addr[(flash_phy_pkg::BusBankAddrW - 1):flash_phy_pkg::LsbAddrBit] : rd_calc_addr)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T39,T73

 LINE       557
 EXPRESSION (prog_calc_req | rd_calc_req)
             ------1------   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T39,T73

 LINE       557
 EXPRESSION (prog_op_req | rd_op_req)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T39,T73

 LINE       557
 EXPRESSION (prog_op_req ? ScrambleOp : DeScrambleOp)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T39,T73

 LINE       579
 EXPRESSION (fsm_err | prog_fsm_err)
             ---1---   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T16,T17
1	0	Covered	T12,T16,T17

---

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	7	7	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCtrl	344	Covered	T15
StCtrlProg	342	Covered	T15
StCtrlRead	340	Covered	T15
StDisable	338	Covered	T15
StIdle	352	Covered	T15

transitions	Line No.	Covered	Tests
StCtrl->StIdle	372	Covered	T15
StCtrlProg->StIdle	362	Covered	T15
StCtrlRead->StIdle	352	Covered	T15
StIdle->StCtrl	344	Covered	T15
StIdle->StCtrlProg	342	Covered	T15
StIdle->StCtrlRead	340	Covered	T15
StIdle->StDisable	338	Covered	T15

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

	Line No.	Total	Covered	Percent
Branches		46	45	97.83
TERNARY	320	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	396	2	2	100.00
TERNARY	397	2	2	100.00
TERNARY	398	2	2	100.00
TERNARY	551	2	2	100.00
TERNARY	434	2	1	50.00
TERNARY	557	2	2	100.00
IF	154	4	4	100.00
IF	167	2	2	100.00
IF	206	3	3	100.00
IF	218	4	4	100.00
IF	232	4	4	100.00
CASE	334	13	13	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	320	((phy_req & host_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T38
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	395	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T38
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	396	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T38
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	397	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T38
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	398	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T38
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	551	(prog_calc_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T39,T73
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	434	(arb_host_gnt_err) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	557	(prog_op_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T39,T73
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	154	if ((!rst_ni))
-2-:	156	if (ctrl_rsp_vld)
-3-:	158	if (inc_arb_cnt)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T4,T42
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	167	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	206	if ((!rst_ni))
-2-:	208	if ((host_gnt_err_event | host_outstanding_err_event))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T189,T178,T9
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	218	if ((!rst_ni))
-2-:	220	if ((host_outstanding == '0))
-3-:	222	if (host_gnt_err_event)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T9,T13,T14
0	0	0	Covered	T2,T6,T38

	LineNo.	Expression
-1-:	232	if ((!rst_ni))
-2-:	234	if (((host_outstanding == '0) && ctrl_fsm_idle))
-3-:	236	if (host_outstanding_err_event)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T9,T13,T14
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	334	case (state_q)
-2-:	337	if (prim_mubi_pkg::mubi4_test_true_loose(flash_disable[FsmDisableIdx]))
-3-:	339	if ((ctrl_gnt && rd_i))
-4-:	341	if ((ctrl_gnt && prog_i))
-5-:	343	if (ctrl_gnt)
-6-:	350	if (rd_stage_data_valid)
-7-:	360	if (prog_ack)
-8-:	370	if (erase_ack)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
StIdle	1	-	-	-	-	-	-	Covered	T10,T11,T12
StIdle	0	1	-	-	-	-	-	Covered	T1,T2,T3
StIdle	0	0	1	-	-	-	-	Covered	T1,T4,T24
StIdle	0	0	0	1	-	-	-	Covered	T1,T19,T20
StIdle	0	0	0	0	-	-	-	Covered	T1,T2,T3
StCtrlRead	-	-	-	-	1	-	-	Covered	T1,T2,T3
StCtrlRead	-	-	-	-	0	-	-	Covered	T1,T2,T3
StCtrlProg	-	-	-	-	-	1	-	Covered	T1,T4,T24
StCtrlProg	-	-	-	-	-	0	-	Covered	T1,T4,T24
StCtrl	-	-	-	-	-	-	1	Covered	T1,T19,T20
StCtrl	-	-	-	-	-	-	0	Covered	T1,T19,T20
StDisable	-	-	-	-	-	-	-	Covered	T11,T12,T78
default	-	-	-	-	-	-	-	Covered	T12,T16,T17

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ArbCntMax_A	349657095	2314505	0	0
CtrlPrio_A	349657095	2314501	0	0
HostTransIdleChk_A	349657095	23025982	0	0
NoRemainder_A	987	987	0	0
OneHotReqs_A	349657095	348853006	0	0
Pow2Multiple_A	987	987	0	0
RdTxnCheck_A	349490887	348686798	0	0
u_state_regs_A	349657095	348853006	0	0

ArbCntMax_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349657095	2314505	0	0
T2	46364	1715	0	0
T3	2711	0	0	0
T4	0	12604	0	0
T6	15619	0	0	0
T10	1175	0	0	0
T18	1998	0	0	0
T19	110708	0	0	0
T20	5922	0	0	0
T21	2343	0	0	0
T22	3729	0	0	0
T29	2099	0	0	0
T33	0	17716	0	0
T34	0	2679	0	0
T39	0	9509	0	0
T42	0	3033	0	0
T43	0	53354	0	0
T45	0	79	0	0
T144	0	17819	0	0
T191	0	44084	0	0

CtrlPrio_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349657095	2314501	0	0
T2	46364	1715	0	0
T3	2711	0	0	0
T4	0	12604	0	0
T6	15619	0	0	0
T10	1175	0	0	0
T18	1998	0	0	0
T19	110708	0	0	0
T20	5922	0	0	0
T21	2343	0	0	0
T22	3729	0	0	0
T29	2099	0	0	0
T33	0	17716	0	0
T34	0	2679	0	0
T39	0	9509	0	0
T42	0	3033	0	0
T43	0	53354	0	0
T45	0	79	0	0
T144	0	17819	0	0
T191	0	44084	0	0

HostTransIdleChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349657095	23025982	0	0
T2	46364	16684	0	0
T3	2711	0	0	0
T4	0	126541	0	0
T5	0	15	0	0
T6	15619	239	0	0
T10	1175	0	0	0
T18	1998	0	0	0
T19	110708	0	0	0
T20	5922	0	0	0
T21	2343	0	0	0
T22	3729	0	0	0
T25	0	75	0	0
T29	2099	0	0	0
T38	0	528	0	0
T39	0	110650	0	0
T42	0	17209	0	0
T43	0	406215	0	0
T45	0	544	0	0

NoRemainder_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	987	987	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

OneHotReqs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349657095	348853006	0	0
T1	561728	561662	0	0
T2	46364	46305	0	0
T3	2711	2536	0	0
T6	15619	15537	0	0
T10	1175	917	0	0
T18	1998	1927	0	0
T19	110708	110536	0	0
T20	5922	5777	0	0
T21	2343	2272	0	0
T22	3729	3008	0	0

Pow2Multiple_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	987	987	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

RdTxnCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349490887	348686798	0	0
T1	561728	561662	0	0
T2	46364	46305	0	0
T3	2711	2536	0	0
T6	15619	15537	0	0
T10	1175	917	0	0
T18	1998	1927	0	0
T19	110708	110536	0	0
T20	5922	5777	0	0
T21	2343	2272	0	0
T22	3729	3008	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349657095	348853006	0	0
T1	561728	561662	0	0
T2	46364	46305	0	0
T3	2711	2536	0	0
T6	15619	15537	0	0
T10	1175	917	0	0
T18	1998	1927	0	0
T19	110708	110536	0	0
T20	5922	5777	0	0
T21	2343	2272	0	0
T22	3729	3008	0	0