Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T6,T4
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T6

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1398628380	1395412024	0	0
CheckNGreaterZero_A	3948	3948	0	0
GntImpliesReady_A	1398628380	379093099	0	0
GntImpliesValid_A	1398628380	379093099	0	0
GrantKnown_A	1398628380	1395412024	0	0
IdxKnown_A	1398628380	1395412024	0	0
IndexIsCorrect_A	1398628380	379093099	0	0
NoReadyValidNoGrant_A	1398628380	154151614	0	0
Priority_A	1398628380	402975239	0	0
ReadyAndValidImplyGrant_A	1398628380	379093099	0	0
ReqAndReadyImplyGrant_A	1398628380	379093099	0	0
ReqImpliesValid_A	1398628380	402975239	0	0
ValidKnown_A	1398628380	1395412024	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1398628380	1395412024	0	0
T1	2246912	2246648	0	0
T2	185456	185220	0	0
T3	10844	10144	0	0
T6	62476	62148	0	0
T10	4700	3668	0	0
T18	7992	7708	0	0
T19	442832	442144	0	0
T20	23688	23108	0	0
T21	9372	9088	0	0
T22	14916	12032	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3948	3948	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T6	4	4	0	0
T10	4	4	0	0
T18	4	4	0	0
T19	4	4	0	0
T20	4	4	0	0
T21	4	4	0	0
T22	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1398628380	379093099	0	0
T1	2246912	1105604	0	0
T2	185456	43138	0	0
T3	10844	1438	0	0
T4	0	249680	0	0
T6	62476	2292	0	0
T10	4700	132	0	0
T18	7992	356	0	0
T19	442832	706	0	0
T20	23688	4202	0	0
T21	9372	104	0	0
T22	14916	400	0	0
T23	0	2106	0	0
T29	0	28	0	0
T38	0	400	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1398628380	379093099	0	0
T1	2246912	1105604	0	0
T2	185456	43138	0	0
T3	10844	1438	0	0
T4	0	249680	0	0
T6	62476	2292	0	0
T10	4700	132	0	0
T18	7992	356	0	0
T19	442832	706	0	0
T20	23688	4202	0	0
T21	9372	104	0	0
T22	14916	400	0	0
T23	0	2106	0	0
T29	0	28	0	0
T38	0	400	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1398628380	1395412024	0	0
T1	2246912	2246648	0	0
T2	185456	185220	0	0
T3	10844	10144	0	0
T6	62476	62148	0	0
T10	4700	3668	0	0
T18	7992	7708	0	0
T19	442832	442144	0	0
T20	23688	23108	0	0
T21	9372	9088	0	0
T22	14916	12032	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1398628380	1395412024	0	0
T1	2246912	2246648	0	0
T2	185456	185220	0	0
T3	10844	10144	0	0
T6	62476	62148	0	0
T10	4700	3668	0	0
T18	7992	7708	0	0
T19	442832	442144	0	0
T20	23688	23108	0	0
T21	9372	9088	0	0
T22	14916	12032	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1398628380	379093099	0	0
T1	2246912	1105604	0	0
T2	185456	43138	0	0
T3	10844	1438	0	0
T4	0	249680	0	0
T6	62476	2292	0	0
T10	4700	132	0	0
T18	7992	356	0	0
T19	442832	706	0	0
T20	23688	4202	0	0
T21	9372	104	0	0
T22	14916	400	0	0
T23	0	2106	0	0
T29	0	28	0	0
T38	0	400	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1398628380	154151614	0	0
T1	2246912	2966	0	0
T2	185456	55630	0	0
T3	10844	988	0	0
T4	0	144630	0	0
T6	62476	3582	0	0
T10	4700	528	0	0
T18	7992	696	0	0
T19	442832	256	0	0
T20	23688	1672	0	0
T21	9372	316	0	0
T22	14916	1600	0	0
T29	0	44	0	0
T38	0	712	0	0
T42	0	41236	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1398628380	402975239	0	0
T1	2246912	1105604	0	0
T2	185456	54004	0	0
T3	10844	1438	0	0
T4	0	273086	0	0
T6	62476	2294	0	0
T10	4700	132	0	0
T18	7992	356	0	0
T19	442832	706	0	0
T20	23688	4202	0	0
T21	9372	104	0	0
T22	14916	400	0	0
T23	0	2106	0	0
T29	0	28	0	0
T38	0	400	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1398628380	379093099	0	0
T1	2246912	1105604	0	0
T2	185456	43138	0	0
T3	10844	1438	0	0
T4	0	249680	0	0
T6	62476	2292	0	0
T10	4700	132	0	0
T18	7992	356	0	0
T19	442832	706	0	0
T20	23688	4202	0	0
T21	9372	104	0	0
T22	14916	400	0	0
T23	0	2106	0	0
T29	0	28	0	0
T38	0	400	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1398628380	379093099	0	0
T1	2246912	1105604	0	0
T2	185456	43138	0	0
T3	10844	1438	0	0
T4	0	249680	0	0
T6	62476	2292	0	0
T10	4700	132	0	0
T18	7992	356	0	0
T19	442832	706	0	0
T20	23688	4202	0	0
T21	9372	104	0	0
T22	14916	400	0	0
T23	0	2106	0	0
T29	0	28	0	0
T38	0	400	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1398628380	402975239	0	0
T1	2246912	1105604	0	0
T2	185456	54004	0	0
T3	10844	1438	0	0
T4	0	273086	0	0
T6	62476	2294	0	0
T10	4700	132	0	0
T18	7992	356	0	0
T19	442832	706	0	0
T20	23688	4202	0	0
T21	9372	104	0	0
T22	14916	400	0	0
T23	0	2106	0	0
T29	0	28	0	0
T38	0	400	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1398628380	1395412024	0	0
T1	2246912	2246648	0	0
T2	185456	185220	0	0
T3	10844	10144	0	0
T6	62476	62148	0	0
T10	4700	3668	0	0
T18	7992	7708	0	0
T19	442832	442144	0	0
T20	23688	23108	0	0
T21	9372	9088	0	0
T22	14916	12032	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T6,T38

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T6,T38
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T6,T38
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T6,T38

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T6,T38
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T6,T4
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T6,T38

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T6,T38

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	349657095	348853006	0	0
CheckNGreaterZero_A	987	987	0	0
GntImpliesReady_A	349657095	105929487	0	0
GntImpliesValid_A	349657095	105929487	0	0
GrantKnown_A	349657095	348853006	0	0
IdxKnown_A	349657095	348853006	0	0
IndexIsCorrect_A	349657095	105929487	0	0
NoReadyValidNoGrant_A	349657095	40411061	0	0
Priority_A	349657095	112001636	0	0
ReadyAndValidImplyGrant_A	349657095	105929487	0	0
ReqAndReadyImplyGrant_A	349657095	105929487	0	0
ReqImpliesValid_A	349657095	112001636	0	0
ValidKnown_A	349657095	348853006	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349657095	348853006	0	0
T1	561728	561662	0	0
T2	46364	46305	0	0
T3	2711	2536	0	0
T6	15619	15537	0	0
T10	1175	917	0	0
T18	1998	1927	0	0
T19	110708	110536	0	0
T20	5922	5777	0	0
T21	2343	2272	0	0
T22	3729	3008	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	987	987	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349657095	105929487	0	0
T1	561728	534158	0	0
T2	46364	11235	0	0
T3	2711	64	0	0
T6	15619	559	0	0
T10	1175	66	0	0
T18	1998	178	0	0
T19	110708	353	0	0
T20	5922	1884	0	0
T21	2343	44	0	0
T22	3729	200	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349657095	105929487	0	0
T1	561728	534158	0	0
T2	46364	11235	0	0
T3	2711	64	0	0
T6	15619	559	0	0
T10	1175	66	0	0
T18	1998	178	0	0
T19	110708	353	0	0
T20	5922	1884	0	0
T21	2343	44	0	0
T22	3729	200	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349657095	348853006	0	0
T1	561728	561662	0	0
T2	46364	46305	0	0
T3	2711	2536	0	0
T6	15619	15537	0	0
T10	1175	917	0	0
T18	1998	1927	0	0
T19	110708	110536	0	0
T20	5922	5777	0	0
T21	2343	2272	0	0
T22	3729	3008	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349657095	348853006	0	0
T1	561728	561662	0	0
T2	46364	46305	0	0
T3	2711	2536	0	0
T6	15619	15537	0	0
T10	1175	917	0	0
T18	1998	1927	0	0
T19	110708	110536	0	0
T20	5922	5777	0	0
T21	2343	2272	0	0
T22	3729	3008	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349657095	105929487	0	0
T1	561728	534158	0	0
T2	46364	11235	0	0
T3	2711	64	0	0
T6	15619	559	0	0
T10	1175	66	0	0
T18	1998	178	0	0
T19	110708	353	0	0
T20	5922	1884	0	0
T21	2343	44	0	0
T22	3729	200	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349657095	40411061	0	0
T1	561728	759	0	0
T2	46364	14292	0	0
T3	2711	256	0	0
T6	15619	912	0	0
T10	1175	264	0	0
T18	1998	348	0	0
T19	110708	128	0	0
T20	5922	256	0	0
T21	2343	146	0	0
T22	3729	800	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349657095	112001636	0	0
T1	561728	534158	0	0
T2	46364	14187	0	0
T3	2711	64	0	0
T6	15619	560	0	0
T10	1175	66	0	0
T18	1998	178	0	0
T19	110708	353	0	0
T20	5922	1884	0	0
T21	2343	44	0	0
T22	3729	200	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349657095	105929487	0	0
T1	561728	534158	0	0
T2	46364	11235	0	0
T3	2711	64	0	0
T6	15619	559	0	0
T10	1175	66	0	0
T18	1998	178	0	0
T19	110708	353	0	0
T20	5922	1884	0	0
T21	2343	44	0	0
T22	3729	200	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349657095	105929487	0	0
T1	561728	534158	0	0
T2	46364	11235	0	0
T3	2711	64	0	0
T6	15619	559	0	0
T10	1175	66	0	0
T18	1998	178	0	0
T19	110708	353	0	0
T20	5922	1884	0	0
T21	2343	44	0	0
T22	3729	200	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349657095	112001636	0	0
T1	561728	534158	0	0
T2	46364	14187	0	0
T3	2711	64	0	0
T6	15619	560	0	0
T10	1175	66	0	0
T18	1998	178	0	0
T19	110708	353	0	0
T20	5922	1884	0	0
T21	2343	44	0	0
T22	3729	200	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349657095	348853006	0	0
T1	561728	561662	0	0
T2	46364	46305	0	0
T3	2711	2536	0	0
T6	15619	15537	0	0
T10	1175	917	0	0
T18	1998	1927	0	0
T19	110708	110536	0	0
T20	5922	5777	0	0
T21	2343	2272	0	0
T22	3729	3008	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T6,T38

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T6,T38
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T6,T38
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T6,T38

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T6,T38
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T6,T4
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T6,T38

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T6,T38

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	349657095	348853006	0	0
CheckNGreaterZero_A	987	987	0	0
GntImpliesReady_A	349657095	105907396	0	0
GntImpliesValid_A	349657095	105907396	0	0
GrantKnown_A	349657095	348853006	0	0
IdxKnown_A	349657095	348853006	0	0
IndexIsCorrect_A	349657095	105907396	0	0
NoReadyValidNoGrant_A	349657095	40411063	0	0
Priority_A	349657095	111979543	0	0
ReadyAndValidImplyGrant_A	349657095	105907396	0	0
ReqAndReadyImplyGrant_A	349657095	105907396	0	0
ReqImpliesValid_A	349657095	111979543	0	0
ValidKnown_A	349657095	348853006	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349657095	348853006	0	0
T1	561728	561662	0	0
T2	46364	46305	0	0
T3	2711	2536	0	0
T6	15619	15537	0	0
T10	1175	917	0	0
T18	1998	1927	0	0
T19	110708	110536	0	0
T20	5922	5777	0	0
T21	2343	2272	0	0
T22	3729	3008	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	987	987	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349657095	105907396	0	0
T1	561728	534158	0	0
T2	46364	11235	0	0
T3	2711	64	0	0
T6	15619	559	0	0
T10	1175	66	0	0
T18	1998	178	0	0
T19	110708	353	0	0
T20	5922	1884	0	0
T21	2343	44	0	0
T22	3729	200	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349657095	105907396	0	0
T1	561728	534158	0	0
T2	46364	11235	0	0
T3	2711	64	0	0
T6	15619	559	0	0
T10	1175	66	0	0
T18	1998	178	0	0
T19	110708	353	0	0
T20	5922	1884	0	0
T21	2343	44	0	0
T22	3729	200	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349657095	348853006	0	0
T1	561728	561662	0	0
T2	46364	46305	0	0
T3	2711	2536	0	0
T6	15619	15537	0	0
T10	1175	917	0	0
T18	1998	1927	0	0
T19	110708	110536	0	0
T20	5922	5777	0	0
T21	2343	2272	0	0
T22	3729	3008	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349657095	348853006	0	0
T1	561728	561662	0	0
T2	46364	46305	0	0
T3	2711	2536	0	0
T6	15619	15537	0	0
T10	1175	917	0	0
T18	1998	1927	0	0
T19	110708	110536	0	0
T20	5922	5777	0	0
T21	2343	2272	0	0
T22	3729	3008	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349657095	105907396	0	0
T1	561728	534158	0	0
T2	46364	11235	0	0
T3	2711	64	0	0
T6	15619	559	0	0
T10	1175	66	0	0
T18	1998	178	0	0
T19	110708	353	0	0
T20	5922	1884	0	0
T21	2343	44	0	0
T22	3729	200	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349657095	40411063	0	0
T1	561728	759	0	0
T2	46364	14292	0	0
T3	2711	256	0	0
T6	15619	912	0	0
T10	1175	264	0	0
T18	1998	348	0	0
T19	110708	128	0	0
T20	5922	256	0	0
T21	2343	146	0	0
T22	3729	800	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349657095	111979543	0	0
T1	561728	534158	0	0
T2	46364	14187	0	0
T3	2711	64	0	0
T6	15619	560	0	0
T10	1175	66	0	0
T18	1998	178	0	0
T19	110708	353	0	0
T20	5922	1884	0	0
T21	2343	44	0	0
T22	3729	200	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349657095	105907396	0	0
T1	561728	534158	0	0
T2	46364	11235	0	0
T3	2711	64	0	0
T6	15619	559	0	0
T10	1175	66	0	0
T18	1998	178	0	0
T19	110708	353	0	0
T20	5922	1884	0	0
T21	2343	44	0	0
T22	3729	200	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349657095	105907396	0	0
T1	561728	534158	0	0
T2	46364	11235	0	0
T3	2711	64	0	0
T6	15619	559	0	0
T10	1175	66	0	0
T18	1998	178	0	0
T19	110708	353	0	0
T20	5922	1884	0	0
T21	2343	44	0	0
T22	3729	200	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349657095	111979543	0	0
T1	561728	534158	0	0
T2	46364	14187	0	0
T3	2711	64	0	0
T6	15619	560	0	0
T10	1175	66	0	0
T18	1998	178	0	0
T19	110708	353	0	0
T20	5922	1884	0	0
T21	2343	44	0	0
T22	3729	200	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349657095	348853006	0	0
T1	561728	561662	0	0
T2	46364	46305	0	0
T3	2711	2536	0	0
T6	15619	15537	0	0
T10	1175	917	0	0
T18	1998	1927	0	0
T19	110708	110536	0	0
T20	5922	5777	0	0
T21	2343	2272	0	0
T22	3729	3008	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T42
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T42
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T6

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	349657095	348853006	0	0
CheckNGreaterZero_A	987	987	0	0
GntImpliesReady_A	349657095	83628108	0	0
GntImpliesValid_A	349657095	83628108	0	0
GrantKnown_A	349657095	348853006	0	0
IdxKnown_A	349657095	348853006	0	0
IndexIsCorrect_A	349657095	83628108	0	0
NoReadyValidNoGrant_A	349657095	36664745	0	0
Priority_A	349657095	89497030	0	0
ReadyAndValidImplyGrant_A	349657095	83628108	0	0
ReqAndReadyImplyGrant_A	349657095	83628108	0	0
ReqImpliesValid_A	349657095	89497030	0	0
ValidKnown_A	349657095	348853006	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349657095	348853006	0	0
T1	561728	561662	0	0
T2	46364	46305	0	0
T3	2711	2536	0	0
T6	15619	15537	0	0
T10	1175	917	0	0
T18	1998	1927	0	0
T19	110708	110536	0	0
T20	5922	5777	0	0
T21	2343	2272	0	0
T22	3729	3008	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	987	987	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349657095	83628108	0	0
T1	561728	18644	0	0
T2	46364	10334	0	0
T3	2711	655	0	0
T4	0	124840	0	0
T6	15619	587	0	0
T10	1175	0	0	0
T18	1998	0	0	0
T19	110708	0	0	0
T20	5922	217	0	0
T21	2343	8	0	0
T22	3729	0	0	0
T23	0	1053	0	0
T29	0	14	0	0
T38	0	200	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349657095	83628108	0	0
T1	561728	18644	0	0
T2	46364	10334	0	0
T3	2711	655	0	0
T4	0	124840	0	0
T6	15619	587	0	0
T10	1175	0	0	0
T18	1998	0	0	0
T19	110708	0	0	0
T20	5922	217	0	0
T21	2343	8	0	0
T22	3729	0	0	0
T23	0	1053	0	0
T29	0	14	0	0
T38	0	200	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349657095	348853006	0	0
T1	561728	561662	0	0
T2	46364	46305	0	0
T3	2711	2536	0	0
T6	15619	15537	0	0
T10	1175	917	0	0
T18	1998	1927	0	0
T19	110708	110536	0	0
T20	5922	5777	0	0
T21	2343	2272	0	0
T22	3729	3008	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349657095	348853006	0	0
T1	561728	561662	0	0
T2	46364	46305	0	0
T3	2711	2536	0	0
T6	15619	15537	0	0
T10	1175	917	0	0
T18	1998	1927	0	0
T19	110708	110536	0	0
T20	5922	5777	0	0
T21	2343	2272	0	0
T22	3729	3008	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349657095	83628108	0	0
T1	561728	18644	0	0
T2	46364	10334	0	0
T3	2711	655	0	0
T4	0	124840	0	0
T6	15619	587	0	0
T10	1175	0	0	0
T18	1998	0	0	0
T19	110708	0	0	0
T20	5922	217	0	0
T21	2343	8	0	0
T22	3729	0	0	0
T23	0	1053	0	0
T29	0	14	0	0
T38	0	200	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349657095	36664745	0	0
T1	561728	724	0	0
T2	46364	13523	0	0
T3	2711	238	0	0
T4	0	72315	0	0
T6	15619	879	0	0
T10	1175	0	0	0
T18	1998	0	0	0
T19	110708	0	0	0
T20	5922	580	0	0
T21	2343	12	0	0
T22	3729	0	0	0
T29	0	22	0	0
T38	0	356	0	0
T42	0	20618	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349657095	89497030	0	0
T1	561728	18644	0	0
T2	46364	12815	0	0
T3	2711	655	0	0
T4	0	136543	0	0
T6	15619	587	0	0
T10	1175	0	0	0
T18	1998	0	0	0
T19	110708	0	0	0
T20	5922	217	0	0
T21	2343	8	0	0
T22	3729	0	0	0
T23	0	1053	0	0
T29	0	14	0	0
T38	0	200	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349657095	83628108	0	0
T1	561728	18644	0	0
T2	46364	10334	0	0
T3	2711	655	0	0
T4	0	124840	0	0
T6	15619	587	0	0
T10	1175	0	0	0
T18	1998	0	0	0
T19	110708	0	0	0
T20	5922	217	0	0
T21	2343	8	0	0
T22	3729	0	0	0
T23	0	1053	0	0
T29	0	14	0	0
T38	0	200	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349657095	83628108	0	0
T1	561728	18644	0	0
T2	46364	10334	0	0
T3	2711	655	0	0
T4	0	124840	0	0
T6	15619	587	0	0
T10	1175	0	0	0
T18	1998	0	0	0
T19	110708	0	0	0
T20	5922	217	0	0
T21	2343	8	0	0
T22	3729	0	0	0
T23	0	1053	0	0
T29	0	14	0	0
T38	0	200	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349657095	89497030	0	0
T1	561728	18644	0	0
T2	46364	12815	0	0
T3	2711	655	0	0
T4	0	136543	0	0
T6	15619	587	0	0
T10	1175	0	0	0
T18	1998	0	0	0
T19	110708	0	0	0
T20	5922	217	0	0
T21	2343	8	0	0
T22	3729	0	0	0
T23	0	1053	0	0
T29	0	14	0	0
T38	0	200	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349657095	348853006	0	0
T1	561728	561662	0	0
T2	46364	46305	0	0
T3	2711	2536	0	0
T6	15619	15537	0	0
T10	1175	917	0	0
T18	1998	1927	0	0
T19	110708	110536	0	0
T20	5922	5777	0	0
T21	2343	2272	0	0
T22	3729	3008	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T42
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T42
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T6

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	349657095	348853006	0	0
CheckNGreaterZero_A	987	987	0	0
GntImpliesReady_A	349657095	83628108	0	0
GntImpliesValid_A	349657095	83628108	0	0
GrantKnown_A	349657095	348853006	0	0
IdxKnown_A	349657095	348853006	0	0
IndexIsCorrect_A	349657095	83628108	0	0
NoReadyValidNoGrant_A	349657095	36664745	0	0
Priority_A	349657095	89497030	0	0
ReadyAndValidImplyGrant_A	349657095	83628108	0	0
ReqAndReadyImplyGrant_A	349657095	83628108	0	0
ReqImpliesValid_A	349657095	89497030	0	0
ValidKnown_A	349657095	348853006	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349657095	348853006	0	0
T1	561728	561662	0	0
T2	46364	46305	0	0
T3	2711	2536	0	0
T6	15619	15537	0	0
T10	1175	917	0	0
T18	1998	1927	0	0
T19	110708	110536	0	0
T20	5922	5777	0	0
T21	2343	2272	0	0
T22	3729	3008	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	987	987	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349657095	83628108	0	0
T1	561728	18644	0	0
T2	46364	10334	0	0
T3	2711	655	0	0
T4	0	124840	0	0
T6	15619	587	0	0
T10	1175	0	0	0
T18	1998	0	0	0
T19	110708	0	0	0
T20	5922	217	0	0
T21	2343	8	0	0
T22	3729	0	0	0
T23	0	1053	0	0
T29	0	14	0	0
T38	0	200	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349657095	83628108	0	0
T1	561728	18644	0	0
T2	46364	10334	0	0
T3	2711	655	0	0
T4	0	124840	0	0
T6	15619	587	0	0
T10	1175	0	0	0
T18	1998	0	0	0
T19	110708	0	0	0
T20	5922	217	0	0
T21	2343	8	0	0
T22	3729	0	0	0
T23	0	1053	0	0
T29	0	14	0	0
T38	0	200	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349657095	348853006	0	0
T1	561728	561662	0	0
T2	46364	46305	0	0
T3	2711	2536	0	0
T6	15619	15537	0	0
T10	1175	917	0	0
T18	1998	1927	0	0
T19	110708	110536	0	0
T20	5922	5777	0	0
T21	2343	2272	0	0
T22	3729	3008	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349657095	348853006	0	0
T1	561728	561662	0	0
T2	46364	46305	0	0
T3	2711	2536	0	0
T6	15619	15537	0	0
T10	1175	917	0	0
T18	1998	1927	0	0
T19	110708	110536	0	0
T20	5922	5777	0	0
T21	2343	2272	0	0
T22	3729	3008	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349657095	83628108	0	0
T1	561728	18644	0	0
T2	46364	10334	0	0
T3	2711	655	0	0
T4	0	124840	0	0
T6	15619	587	0	0
T10	1175	0	0	0
T18	1998	0	0	0
T19	110708	0	0	0
T20	5922	217	0	0
T21	2343	8	0	0
T22	3729	0	0	0
T23	0	1053	0	0
T29	0	14	0	0
T38	0	200	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349657095	36664745	0	0
T1	561728	724	0	0
T2	46364	13523	0	0
T3	2711	238	0	0
T4	0	72315	0	0
T6	15619	879	0	0
T10	1175	0	0	0
T18	1998	0	0	0
T19	110708	0	0	0
T20	5922	580	0	0
T21	2343	12	0	0
T22	3729	0	0	0
T29	0	22	0	0
T38	0	356	0	0
T42	0	20618	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349657095	89497030	0	0
T1	561728	18644	0	0
T2	46364	12815	0	0
T3	2711	655	0	0
T4	0	136543	0	0
T6	15619	587	0	0
T10	1175	0	0	0
T18	1998	0	0	0
T19	110708	0	0	0
T20	5922	217	0	0
T21	2343	8	0	0
T22	3729	0	0	0
T23	0	1053	0	0
T29	0	14	0	0
T38	0	200	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349657095	83628108	0	0
T1	561728	18644	0	0
T2	46364	10334	0	0
T3	2711	655	0	0
T4	0	124840	0	0
T6	15619	587	0	0
T10	1175	0	0	0
T18	1998	0	0	0
T19	110708	0	0	0
T20	5922	217	0	0
T21	2343	8	0	0
T22	3729	0	0	0
T23	0	1053	0	0
T29	0	14	0	0
T38	0	200	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349657095	83628108	0	0
T1	561728	18644	0	0
T2	46364	10334	0	0
T3	2711	655	0	0
T4	0	124840	0	0
T6	15619	587	0	0
T10	1175	0	0	0
T18	1998	0	0	0
T19	110708	0	0	0
T20	5922	217	0	0
T21	2343	8	0	0
T22	3729	0	0	0
T23	0	1053	0	0
T29	0	14	0	0
T38	0	200	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349657095	89497030	0	0
T1	561728	18644	0	0
T2	46364	12815	0	0
T3	2711	655	0	0
T4	0	136543	0	0
T6	15619	587	0	0
T10	1175	0	0	0
T18	1998	0	0	0
T19	110708	0	0	0
T20	5922	217	0	0
T21	2343	8	0	0
T22	3729	0	0	0
T23	0	1053	0	0
T29	0	14	0	0
T38	0	200	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349657095	348853006	0	0
T1	561728	561662	0	0
T2	46364	46305	0	0
T3	2711	2536	0	0
T6	15619	15537	0	0
T10	1175	917	0	0
T18	1998	1927	0	0
T19	110708	110536	0	0
T20	5922	5777	0	0
T21	2343	2272	0	0
T22	3729	3008	0	0