Unified Coverage Report :: Module :: tlul_fifo_sync

Module : tlul_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00		100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg_core.u_socket.fifo_h	100.00		100.00			100.00
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d	100.00		100.00			100.00
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d	100.00		100.00			100.00
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d	100.00		100.00			100.00

---

Module Instance : tb.dut.u_reg_core.u_socket.fifo_h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00		100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.33	100.00	93.33			100.00	100.00	u_socket

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
reqfifo	100.00	100.00					100.00
rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00		100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.33	100.00	93.33			100.00	100.00	u_socket

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
reqfifo	100.00	100.00					100.00
rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00		100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.33	100.00	93.33			100.00	100.00	u_socket

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
reqfifo	100.00	100.00					100.00
rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00		100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.33	100.00	93.33			100.00	100.00	u_socket

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
reqfifo	100.00	100.00					100.00
rspfifo	100.00	100.00					100.00

Cond Coverage for Module : tlul_fifo_sync

	Total	Covered	Percent
Conditions	4	4	100.00
Logical	4	4	100.00
Non-Logical	0	0
Event	0	0

 LINE       66
 SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
                 -----------------1----------------

-1-	Status	Tests
0	Covered	T15,T26,T1
1	Covered	T15,T26,T1

 LINE       66
 SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T15,T26,T1
1	Covered	T15,T26,T1

---

Branch Coverage for Module : tlul_fifo_sync

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	66	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	((tl_d_i.d_opcode == AccessAckData)) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T26,T1
0	Covered	T15,T26,T1

Cond Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h

	Total	Covered	Percent
Conditions	4	4	100.00
Logical	4	4	100.00
Non-Logical	0	0
Event	0	0

 LINE       66
 SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
                 -----------------1----------------

-1-	Status	Tests
0	Covered	T15,T26,T1
1	Covered	T15,T26,T1

 LINE       66
 SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T15,T26,T1
1	Covered	T15,T26,T1

---

Branch Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	66	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	((tl_d_i.d_opcode == AccessAckData)) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T26,T1
0	Covered	T15,T26,T1

Cond Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d

	Total	Covered	Percent
Conditions	4	4	100.00
Logical	4	4	100.00
Non-Logical	0	0
Event	0	0

 LINE       66
 SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
                 -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T3,T23
1	Covered	T15,T26,T1

 LINE       66
 SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T15,T26,T1
1	Covered	T15,T26,T1

---

Branch Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	66	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	((tl_d_i.d_opcode == AccessAckData)) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T26,T1
0	Covered	T1,T3,T23

Cond Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d

	Total	Covered	Percent
Conditions	4	4	100.00
Logical	4	4	100.00
Non-Logical	0	0
Event	0	0

 LINE       66
 SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
                 -----------------1----------------

-1-	Status	Tests
0	Covered	T165,T204,T205
1	Covered	T15,T26,T1

 LINE       66
 SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T15,T26,T1
1	Covered	T15,T26,T1

---

Branch Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	66	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	((tl_d_i.d_opcode == AccessAckData)) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T26,T1
0	Covered	T165,T204,T205

Cond Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d

	Total	Covered	Percent
Conditions	4	4	100.00
Logical	4	4	100.00
Non-Logical	0	0
Event	0	0

 LINE       66
 SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
                 -----------------1----------------

-1-	Status	Tests
0	Covered	T15,T26,T1
1	Covered	T15,T26,T1

 LINE       66
 SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T15,T26,T1
1	Covered	T15,T26,T1

---

Branch Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	66	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	((tl_d_i.d_opcode == AccessAckData)) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T26,T1
0	Covered	T15,T26,T1