Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	93.75	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	91.67	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.67	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	2	14	87.50

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	2	14	87.50	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	17633519	1		T1	71		T2	8476		T3	67
full_word	5776961	1		T1	52		T2	25977		T3	39

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	23410330	1		T1	123		T2	34453		T3	106
auto[TlIntgErrCmd]	44	1		T200	6		T203	2		T220	2
auto[TlIntgErrData]	50	1		T200	7		T203	10		T220	4
auto[TlIntgErrBoth]	56	1		T200	7		T203	8		T220	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	20052740	1		T1	58		T2	8025		T3	59
auto[1]	3357740	1		T1	65		T2	26428		T3	47

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	2	14	87.50	2

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER
[auto[TlIntgErrCmd]]	[full_word]	[auto[1]]	0	1	1
[auto[TlIntgErrData]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	17162027	1		T1	58		T2	4048		T3	59
auto[TlIntgErrNone]	partial	auto[1]	471357	1		T1	13		T2	4428		T3	8
auto[TlIntgErrNone]	full_word	auto[0]	2890649	1		T2	3977		T4	315		T5	19715
auto[TlIntgErrNone]	full_word	auto[1]	2886297	1		T1	52		T2	22000		T3	39
auto[TlIntgErrCmd]	partial	auto[0]	17	1		T200	2		T203	1		T220	2
auto[TlIntgErrCmd]	partial	auto[1]	26	1		T200	4		T203	1		T223	7
auto[TlIntgErrCmd]	full_word	auto[0]	1	1		T235	1		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	22	1		T200	2		T203	5		T220	1
auto[TlIntgErrData]	partial	auto[1]	25	1		T200	5		T203	4		T220	3
auto[TlIntgErrData]	full_word	auto[1]	3	1		T203	1		T242	1		T235	1
auto[TlIntgErrBoth]	partial	auto[0]	18	1		T200	2		T203	1		T220	1
auto[TlIntgErrBoth]	partial	auto[1]	27	1		T200	3		T203	5		T220	2
auto[TlIntgErrBoth]	full_word	auto[0]	6	1		T200	2		T203	1		T223	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1		T203	1		T220	1		T223	1

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	8196	1		T200	17		T203	18		T204	4
full_word	3199414	1		T4	2		T5	16255		T7	243

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3207465	1		T4	2		T5	16255		T7	243
auto[TlIntgErrCmd]	51	1		T200	4		T203	8		T220	4
auto[TlIntgErrData]	47	1		T200	5		T203	5		T220	2
auto[TlIntgErrBoth]	47	1		T200	10		T203	7		T220	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3197438	1		T4	2		T5	16255		T7	243
auto[1]	10172	1		T200	14		T203	11		T204	5

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER
[auto[TlIntgErrCmd]]	[full_word]	[auto[1]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	470	1		T221	46		T222	36		T224	5
auto[TlIntgErrNone]	partial	auto[1]	7590	1		T204	4		T221	759		T222	510
auto[TlIntgErrNone]	full_word	auto[0]	3196903	1		T4	2		T5	16255		T7	243
auto[TlIntgErrNone]	full_word	auto[1]	2502	1		T204	1		T221	261		T222	168
auto[TlIntgErrCmd]	partial	auto[0]	16	1		T200	1		T203	2		T220	1
auto[TlIntgErrCmd]	partial	auto[1]	33	1		T200	3		T203	5		T220	3
auto[TlIntgErrCmd]	full_word	auto[0]	2	1		T203	1		T235	1		-	-
auto[TlIntgErrData]	partial	auto[0]	27	1		T200	3		T203	2		T220	1
auto[TlIntgErrData]	partial	auto[1]	16	1		T200	1		T203	3		T223	1
auto[TlIntgErrData]	full_word	auto[0]	2	1		T242	1		T263	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	2	1		T200	1		T220	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	17	1		T200	1		T203	4		T223	6
auto[TlIntgErrBoth]	partial	auto[1]	27	1		T200	8		T203	2		T220	3
auto[TlIntgErrBoth]	full_word	auto[0]	1	1		T242	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	2	1		T200	1		T203	1		-	-