Unified Coverage Report :: Module :: flash_ctrl_phy_cov_if

Module : flash_ctrl_phy_cov_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.68	100.00	92.00			94.74	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_cov_0/flash_ctrl_phy_cov_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_phy_cov_if	96.18	100.00	90.00			94.74	100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_phy_cov_if	96.68	100.00	92.00			94.74	100.00

---

Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_phy_cov_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.18	100.00	90.00			94.74	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.18	100.00	90.00			94.74	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.55	96.48	92.86		93.75	91.11		gen_prim_flash_banks[1].u_prim_flash_bank

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_phy_cov_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.68	100.00	92.00			94.74	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.68	100.00	92.00			94.74	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.55	96.48	92.86		93.75	91.11		gen_prim_flash_banks[0].u_prim_flash_bank

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : flash_ctrl_phy_cov_if

	Line No.	Total	Covered	Percent
TOTAL		24	24	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
ROUTINE	39	6	6	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	46	1	1	100.00
ALWAYS	49	9	9	100.00
ALWAYS	63	3	3	100.00
CONT_ASSIGN	70	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_cov_0/flash_ctrl_phy_cov_if.sv' or '../src/lowrisc_dv_flash_ctrl_cov_0/flash_ctrl_phy_cov_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
30	1	1
32	1	1
39	2	2
			MISSING_ELSE
40	2	2
			MISSING_ELSE
41	2	2
			MISSING_ELSE
44	1	1
45	1	1
46	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
55	1	1
56	1	1
57	1	1
58	1	1
63	2	2
64	1	1
70	1	1

---

Cond Coverage for Module : flash_ctrl_phy_cov_if

	Total	Covered	Percent
Conditions	50	46	92.00
Logical	50	46	92.00
Non-Logical	0	0
Event	0	0

 LINE       30
 EXPRESSION (rd_req | prog_req | pg_erase_req | bk_erase_req)
             ---1--   ----2---   ------3-----   ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T7,T45,T46
0	0	1	0	Covered	T12,T7,T21
0	1	0	0	Covered	T2,T6,T7
1	0	0	0	Covered	T1,T2,T3

 LINE       32
 EXPRESSION (any_req & ack)
             ---1---   -2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T6,T7
1	1	Covered	T1,T2,T3

 LINE       41
 EXPRESSION (pg_erase_req | bk_erase_req)
             ------1-----   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T118,T160,T161
0	1	Covered	T7,T45,T46
1	0	Covered	T12,T7,T21

 LINE       44
 EXPRESSION (any_vld_req ? get_cmd() : NONE)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       45
 EXPRESSION ((cur_cmd == READ) ? addr : rd_addr_d)
             --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       45
 SUB-EXPRESSION (cur_cmd == READ)
                --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       46
 EXPRESSION (((cur_cmd != READ) && (cur_cmd_d == READ)) ? rd_addr : prv_rd_addr_d)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       46
 SUB-EXPRESSION ((cur_cmd != READ) && (cur_cmd_d == READ))
                 --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       46
 SUB-EXPRESSION (cur_cmd != READ)
                --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       46
 SUB-EXPRESSION (cur_cmd_d == READ)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       58
 EXPRESSION ((any_req & ack) ? cur_cmd : prv_cmd)
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       58
 SUB-EXPRESSION (any_req & ack)
                 ---1---   -2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T6,T7
1	1	Covered	T1,T2,T3

 LINE       63
 EXPRESSION (((~rst_ni)) | ((~rd_buf_en)))
             -----1-----   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Not Covered

 LINE       64
 EXPRESSION ((any_req & ack) ? 0 : ((idle_cnt == 32'hffffffff) ? 32'hffffffff : ((idle_cnt + 32'b1))))
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       64
 SUB-EXPRESSION (any_req & ack)
                 ---1---   -2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T6,T7
1	1	Covered	T2,T4,T5

 LINE       64
 SUB-EXPRESSION ((idle_cnt == 32'hffffffff) ? 32'hffffffff : ((idle_cnt + 32'b1)))
                 -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       64
 SUB-EXPRESSION (idle_cnt == 32'hffffffff)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       70
 EXPRESSION ((cur_cmd == READ) && (prv_cmd == READ))
             --------1--------    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       70
 SUB-EXPRESSION (cur_cmd == READ)
                --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       70
 SUB-EXPRESSION (prv_cmd == READ)
                --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Module : flash_ctrl_phy_cov_if

	Line No.	Total	Covered	Percent
Branches		19	18	94.74
TERNARY	44	2	2	100.00
TERNARY	45	2	2	100.00
TERNARY	46	2	2	100.00
IF	49	3	3	100.00
IF	63	4	3	75.00
IF	39	2	2	100.00
IF	40	2	2	100.00
IF	41	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_cov_0/flash_ctrl_phy_cov_if.sv' or '../src/lowrisc_dv_flash_ctrl_cov_0/flash_ctrl_phy_cov_if.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	44	(any_vld_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	45	((cur_cmd == READ)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	46	(((cur_cmd != READ) && (cur_cmd_d == READ))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	49	if ((~rst_ni))
-2-:	58	((any_req & ack)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	63	if (((~rst_ni) | (~rd_buf_en)))
-2-:	64	((any_req & ack)) ? 
-3-:	64	((idle_cnt == 32'hffffffff)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T4,T5
0	0	1	Not Covered
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	39	if (rd_req)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	40	if (prog_req)

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	41	if ((pg_erase_req | bk_erase_req))

Branches:

-1-	Status	Tests
1	Covered	T12,T7,T21
0	Covered	T1,T2,T3

---

Assert Coverage for Module : flash_ctrl_phy_cov_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NoSameAddrRead_A	620393522	4200416	0	0

NoSameAddrRead_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	620393522	4200416	0	0
T4	4518	127	0	0
T5	259594	25501	0	0
T6	837258	0	0	0
T7	278362	166	0	0
T8	0	23955	0	0
T12	7714	0	0	0
T13	2552	0	0	0
T18	1968	0	0	0
T19	0	25211	0	0
T23	0	44481	0	0
T24	0	512	0	0
T25	0	44924	0	0
T33	4396	43	0	0
T40	1802	0	0	0
T41	0	23492	0	0
T42	2506	0	0	0
T43	2612	0	0	0
T45	0	1176	0	0
T46	0	53	0	0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_phy_cov_if

	Line No.	Total	Covered	Percent
TOTAL		24	24	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
ROUTINE	39	6	6	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	46	1	1	100.00
ALWAYS	49	9	9	100.00
ALWAYS	63	3	3	100.00
CONT_ASSIGN	70	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_cov_0/flash_ctrl_phy_cov_if.sv' or '../src/lowrisc_dv_flash_ctrl_cov_0/flash_ctrl_phy_cov_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
30	1	1
32	1	1
39	2	2
			MISSING_ELSE
40	2	2
			MISSING_ELSE
41	2	2
			MISSING_ELSE
44	1	1
45	1	1
46	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
55	1	1
56	1	1
57	1	1
58	1	1
63	2	2
64	1	1
70	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_phy_cov_if

	Total	Covered	Percent
Conditions	50	45	90.00
Logical	50	45	90.00
Non-Logical	0	0
Event	0	0

 LINE       30
 EXPRESSION (rd_req | prog_req | pg_erase_req | bk_erase_req)
             ---1--   ----2---   ------3-----   ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T46,T51,T52
0	0	1	0	Covered	T7,T50,T45
0	1	0	0	Covered	T2,T6,T7
1	0	0	0	Covered	T4,T5,T7

 LINE       32
 EXPRESSION (any_req & ack)
             ---1---   -2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T6,T7
1	1	Covered	T2,T4,T5

 LINE       41
 EXPRESSION (pg_erase_req | bk_erase_req)
             ------1-----   ------2-----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T46,T51,T52
1	0	Covered	T7,T50,T45

 LINE       44
 EXPRESSION (any_vld_req ? get_cmd() : NONE)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       45
 EXPRESSION ((cur_cmd == READ) ? addr : rd_addr_d)
             --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T7

 LINE       45
 SUB-EXPRESSION (cur_cmd == READ)
                --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T7

 LINE       46
 EXPRESSION (((cur_cmd != READ) && (cur_cmd_d == READ)) ? rd_addr : prv_rd_addr_d)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T7

 LINE       46
 SUB-EXPRESSION ((cur_cmd != READ) && (cur_cmd_d == READ))
                 --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T7

 LINE       46
 SUB-EXPRESSION (cur_cmd != READ)
                --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       46
 SUB-EXPRESSION (cur_cmd_d == READ)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T7

 LINE       58
 EXPRESSION ((any_req & ack) ? cur_cmd : prv_cmd)
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       58
 SUB-EXPRESSION (any_req & ack)
                 ---1---   -2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T6,T7
1	1	Covered	T2,T4,T5

 LINE       63
 EXPRESSION (((~rst_ni)) | ((~rd_buf_en)))
             -----1-----   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Not Covered

 LINE       64
 EXPRESSION ((any_req & ack) ? 0 : ((idle_cnt == 32'hffffffff) ? 32'hffffffff : ((idle_cnt + 32'b1))))
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       64
 SUB-EXPRESSION (any_req & ack)
                 ---1---   -2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T6,T7
1	1	Covered	T2,T4,T5

 LINE       64
 SUB-EXPRESSION ((idle_cnt == 32'hffffffff) ? 32'hffffffff : ((idle_cnt + 32'b1)))
                 -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       64
 SUB-EXPRESSION (idle_cnt == 32'hffffffff)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       70
 EXPRESSION ((cur_cmd == READ) && (prv_cmd == READ))
             --------1--------    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T7
1	0	Covered	T4,T5,T7
1	1	Covered	T4,T5,T7

 LINE       70
 SUB-EXPRESSION (cur_cmd == READ)
                --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T7

 LINE       70
 SUB-EXPRESSION (prv_cmd == READ)
                --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T7

---

Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_phy_cov_if

	Line No.	Total	Covered	Percent
Branches		19	18	94.74
TERNARY	44	2	2	100.00
TERNARY	45	2	2	100.00
TERNARY	46	2	2	100.00
IF	49	3	3	100.00
IF	63	4	3	75.00
IF	39	2	2	100.00
IF	40	2	2	100.00
IF	41	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_cov_0/flash_ctrl_phy_cov_if.sv' or '../src/lowrisc_dv_flash_ctrl_cov_0/flash_ctrl_phy_cov_if.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	44	(any_vld_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	45	((cur_cmd == READ)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	46	(((cur_cmd != READ) && (cur_cmd_d == READ))) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	49	if ((~rst_ni))
-2-:	58	((any_req & ack)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	63	if (((~rst_ni) | (~rd_buf_en)))
-2-:	64	((any_req & ack)) ? 
-3-:	64	((idle_cnt == 32'hffffffff)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T4,T5
0	0	1	Not Covered
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	39	if (rd_req)

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	40	if (prog_req)

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	41	if ((pg_erase_req | bk_erase_req))

Branches:

-1-	Status	Tests
1	Covered	T7,T50,T45
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_phy_cov_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NoSameAddrRead_A	310196761	1878913	0	0

NoSameAddrRead_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310196761	1878913	0	0
T4	4518	127	0	0
T5	129797	11919	0	0
T6	418629	0	0	0
T7	139181	92	0	0
T8	0	10440	0	0
T12	3857	0	0	0
T13	1276	0	0	0
T18	984	0	0	0
T19	0	12644	0	0
T23	0	22866	0	0
T25	0	22057	0	0
T33	2198	43	0	0
T41	0	12356	0	0
T42	1253	0	0	0
T43	1306	0	0	0
T45	0	343	0	0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_phy_cov_if

	Line No.	Total	Covered	Percent
TOTAL		24	24	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
ROUTINE	39	6	6	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	46	1	1	100.00
ALWAYS	49	9	9	100.00
ALWAYS	63	3	3	100.00
CONT_ASSIGN	70	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_cov_0/flash_ctrl_phy_cov_if.sv' or '../src/lowrisc_dv_flash_ctrl_cov_0/flash_ctrl_phy_cov_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
30	1	1
32	1	1
39	2	2
			MISSING_ELSE
40	2	2
			MISSING_ELSE
41	2	2
			MISSING_ELSE
44	1	1
45	1	1
46	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
55	1	1
56	1	1
57	1	1
58	1	1
63	2	2
64	1	1
70	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_phy_cov_if

	Total	Covered	Percent
Conditions	50	46	92.00
Logical	50	46	92.00
Non-Logical	0	0
Event	0	0

 LINE       30
 EXPRESSION (rd_req | prog_req | pg_erase_req | bk_erase_req)
             ---1--   ----2---   ------3-----   ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T7,T45,T46
0	0	1	0	Covered	T12,T7,T21
0	1	0	0	Covered	T2,T6,T7
1	0	0	0	Covered	T1,T2,T3

 LINE       32
 EXPRESSION (any_req & ack)
             ---1---   -2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T6,T7
1	1	Covered	T1,T2,T3

 LINE       41
 EXPRESSION (pg_erase_req | bk_erase_req)
             ------1-----   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T118,T160,T161
0	1	Covered	T7,T45,T46
1	0	Covered	T12,T7,T21

 LINE       44
 EXPRESSION (any_vld_req ? get_cmd() : NONE)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       45
 EXPRESSION ((cur_cmd == READ) ? addr : rd_addr_d)
             --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       45
 SUB-EXPRESSION (cur_cmd == READ)
                --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       46
 EXPRESSION (((cur_cmd != READ) && (cur_cmd_d == READ)) ? rd_addr : prv_rd_addr_d)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       46
 SUB-EXPRESSION ((cur_cmd != READ) && (cur_cmd_d == READ))
                 --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       46
 SUB-EXPRESSION (cur_cmd != READ)
                --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       46
 SUB-EXPRESSION (cur_cmd_d == READ)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       58
 EXPRESSION ((any_req & ack) ? cur_cmd : prv_cmd)
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       58
 SUB-EXPRESSION (any_req & ack)
                 ---1---   -2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T6,T7
1	1	Covered	T1,T2,T3

 LINE       63
 EXPRESSION (((~rst_ni)) | ((~rd_buf_en)))
             -----1-----   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Not Covered

 LINE       64
 EXPRESSION ((any_req & ack) ? 0 : ((idle_cnt == 32'hffffffff) ? 32'hffffffff : ((idle_cnt + 32'b1))))
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T6

 LINE       64
 SUB-EXPRESSION (any_req & ack)
                 ---1---   -2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T6,T7
1	1	Covered	T2,T5,T6

 LINE       64
 SUB-EXPRESSION ((idle_cnt == 32'hffffffff) ? 32'hffffffff : ((idle_cnt + 32'b1)))
                 -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       64
 SUB-EXPRESSION (idle_cnt == 32'hffffffff)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       70
 EXPRESSION ((cur_cmd == READ) && (prv_cmd == READ))
             --------1--------    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       70
 SUB-EXPRESSION (cur_cmd == READ)
                --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       70
 SUB-EXPRESSION (prv_cmd == READ)
                --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_phy_cov_if

	Line No.	Total	Covered	Percent
Branches		19	18	94.74
TERNARY	44	2	2	100.00
TERNARY	45	2	2	100.00
TERNARY	46	2	2	100.00
IF	49	3	3	100.00
IF	63	4	3	75.00
IF	39	2	2	100.00
IF	40	2	2	100.00
IF	41	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_cov_0/flash_ctrl_phy_cov_if.sv' or '../src/lowrisc_dv_flash_ctrl_cov_0/flash_ctrl_phy_cov_if.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	44	(any_vld_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	45	((cur_cmd == READ)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	46	(((cur_cmd != READ) && (cur_cmd_d == READ))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	49	if ((~rst_ni))
-2-:	58	((any_req & ack)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	63	if (((~rst_ni) | (~rd_buf_en)))
-2-:	64	((any_req & ack)) ? 
-3-:	64	((idle_cnt == 32'hffffffff)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T5,T6
0	0	1	Not Covered
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	39	if (rd_req)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	40	if (prog_req)

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	41	if ((pg_erase_req | bk_erase_req))

Branches:

-1-	Status	Tests
1	Covered	T12,T7,T21
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_phy_cov_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NoSameAddrRead_A	310196761	2321503	0	0

NoSameAddrRead_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310196761	2321503	0	0
T5	129797	13582	0	0
T6	418629	0	0	0
T7	139181	74	0	0
T8	0	13515	0	0
T12	3857	0	0	0
T13	1276	0	0	0
T18	984	0	0	0
T19	0	12567	0	0
T23	0	21615	0	0
T24	0	512	0	0
T25	0	22867	0	0
T33	2198	0	0	0
T40	1802	0	0	0
T41	0	11136	0	0
T42	1253	0	0	0
T43	1306	0	0	0
T45	0	833	0	0
T46	0	53	0	0