Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T7

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T7
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T7
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T7

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T7
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T7,T8
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T7

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T7

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1240787044	1237869828	0	0
CheckNGreaterZero_A	3440	3440	0	0
GntImpliesReady_A	1240787044	346638434	0	0
GntImpliesValid_A	1240787044	346638434	0	0
GrantKnown_A	1240787044	1237869828	0	0
IdxKnown_A	1240787044	1237869828	0	0
IndexIsCorrect_A	1240787044	346638434	0	0
NoReadyValidNoGrant_A	1240787044	142229720	0	0
Priority_A	1240787044	367792068	0	0
ReadyAndValidImplyGrant_A	1240787044	346638434	0	0
ReqAndReadyImplyGrant_A	1240787044	346638434	0	0
ReqImpliesValid_A	1240787044	367792068	0	0
ValidKnown_A	1240787044	1237869828	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1240787044	1237869828	0	0
T1	5624	5304	0	0
T2	1691692	1691656	0	0
T3	6260	5112	0	0
T4	18072	17448	0	0
T5	519188	518588	0	0
T6	1674516	1674492	0	0
T7	556724	556448	0	0
T12	15428	12636	0	0
T13	5104	4208	0	0
T18	3936	3608	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3440	3440	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T7	4	4	0	0
T12	4	4	0	0
T13	4	4	0	0
T18	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1240787044	346638434	0	0
T1	2812	64	0	0
T2	1691692	841640	0	0
T3	6260	134	0	0
T4	18072	668	0	0
T5	519188	67132	0	0
T6	1674516	830532	0	0
T7	556724	270550	0	0
T8	0	26262	0	0
T12	15428	376	0	0
T13	5104	134	0	0
T18	3936	64	0	0
T19	0	31670	0	0
T33	0	374	0	0
T41	0	30114	0	0
T42	2506	0	0	0
T50	0	255794	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1240787044	346638434	0	0
T1	2812	64	0	0
T2	1691692	841640	0	0
T3	6260	134	0	0
T4	18072	668	0	0
T5	519188	67132	0	0
T6	1674516	830532	0	0
T7	556724	270550	0	0
T8	0	26262	0	0
T12	15428	376	0	0
T13	5104	134	0	0
T18	3936	64	0	0
T19	0	31670	0	0
T33	0	374	0	0
T41	0	30114	0	0
T42	2506	0	0	0
T50	0	255794	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1240787044	1237869828	0	0
T1	5624	5304	0	0
T2	1691692	1691656	0	0
T3	6260	5112	0	0
T4	18072	17448	0	0
T5	519188	518588	0	0
T6	1674516	1674492	0	0
T7	556724	556448	0	0
T12	15428	12636	0	0
T13	5104	4208	0	0
T18	3936	3608	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1240787044	1237869828	0	0
T1	5624	5304	0	0
T2	1691692	1691656	0	0
T3	6260	5112	0	0
T4	18072	17448	0	0
T5	519188	518588	0	0
T6	1674516	1674492	0	0
T7	556724	556448	0	0
T12	15428	12636	0	0
T13	5104	4208	0	0
T18	3936	3608	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1240787044	346638434	0	0
T1	2812	64	0	0
T2	1691692	841640	0	0
T3	6260	134	0	0
T4	18072	668	0	0
T5	519188	67132	0	0
T6	1674516	830532	0	0
T7	556724	270550	0	0
T8	0	26262	0	0
T12	15428	376	0	0
T13	5104	134	0	0
T18	3936	64	0	0
T19	0	31670	0	0
T33	0	374	0	0
T41	0	30114	0	0
T42	2506	0	0	0
T50	0	255794	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1240787044	142229720	0	0
T1	2812	256	0	0
T2	845846	3392	0	0
T3	3130	536	0	0
T4	18072	1814	0	0
T5	519188	180582	0	0
T6	1674516	3392	0	0
T7	556724	1434	0	0
T8	0	870994	0	0
T12	15428	1408	0	0
T13	5104	536	0	0
T18	3936	256	0	0
T19	0	982412	0	0
T23	0	99338	0	0
T33	4396	392	0	0
T41	0	971304	0	0
T42	2506	0	0	0
T43	2612	0	0	0
T45	0	2026	0	0
T50	0	1048576	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1240787044	367792068	0	0
T1	2812	64	0	0
T2	1691692	841640	0	0
T3	6260	134	0	0
T4	18072	668	0	0
T5	519188	70830	0	0
T6	1674516	830532	0	0
T7	556724	270656	0	0
T8	0	218732	0	0
T12	15428	376	0	0
T13	5104	134	0	0
T18	3936	64	0	0
T19	0	336722	0	0
T33	0	374	0	0
T41	0	316724	0	0
T42	2506	0	0	0
T50	0	255794	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1240787044	346638434	0	0
T1	2812	64	0	0
T2	1691692	841640	0	0
T3	6260	134	0	0
T4	18072	668	0	0
T5	519188	67132	0	0
T6	1674516	830532	0	0
T7	556724	270550	0	0
T8	0	26262	0	0
T12	15428	376	0	0
T13	5104	134	0	0
T18	3936	64	0	0
T19	0	31670	0	0
T33	0	374	0	0
T41	0	30114	0	0
T42	2506	0	0	0
T50	0	255794	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1240787044	346638434	0	0
T1	2812	64	0	0
T2	1691692	841640	0	0
T3	6260	134	0	0
T4	18072	668	0	0
T5	519188	67132	0	0
T6	1674516	830532	0	0
T7	556724	270550	0	0
T8	0	26262	0	0
T12	15428	376	0	0
T13	5104	134	0	0
T18	3936	64	0	0
T19	0	31670	0	0
T33	0	374	0	0
T41	0	30114	0	0
T42	2506	0	0	0
T50	0	255794	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1240787044	367792068	0	0
T1	2812	64	0	0
T2	1691692	841640	0	0
T3	6260	134	0	0
T4	18072	668	0	0
T5	519188	70830	0	0
T6	1674516	830532	0	0
T7	556724	270656	0	0
T8	0	218732	0	0
T12	15428	376	0	0
T13	5104	134	0	0
T18	3936	64	0	0
T19	0	336722	0	0
T33	0	374	0	0
T41	0	316724	0	0
T42	2506	0	0	0
T50	0	255794	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1240787044	1237869828	0	0
T1	5624	5304	0	0
T2	1691692	1691656	0	0
T3	6260	5112	0	0
T4	18072	17448	0	0
T5	519188	518588	0	0
T6	1674516	1674492	0	0
T7	556724	556448	0	0
T12	15428	12636	0	0
T13	5104	4208	0	0
T18	3936	3608	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T7,T8

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T7,T8
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T7,T8
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T7,T8

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T7,T8
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T7,T8
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T7,T8

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T7,T8

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	310196761	309467457	0	0
CheckNGreaterZero_A	860	860	0	0
GntImpliesReady_A	310196761	96728254	0	0
GntImpliesValid_A	310196761	96728254	0	0
GrantKnown_A	310196761	309467457	0	0
IdxKnown_A	310196761	309467457	0	0
IndexIsCorrect_A	310196761	96728254	0	0
NoReadyValidNoGrant_A	310196761	37239108	0	0
Priority_A	310196761	102028329	0	0
ReadyAndValidImplyGrant_A	310196761	96728254	0	0
ReqAndReadyImplyGrant_A	310196761	96728254	0	0
ReqImpliesValid_A	310196761	102028329	0	0
ValidKnown_A	310196761	309467457	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310196761	309467457	0	0
T1	1406	1326	0	0
T2	422923	422914	0	0
T3	1565	1278	0	0
T4	4518	4362	0	0
T5	129797	129647	0	0
T6	418629	418623	0	0
T7	139181	139112	0	0
T12	3857	3159	0	0
T13	1276	1052	0	0
T18	984	902	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	860	860	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T18	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310196761	96728254	0	0
T1	1406	32	0	0
T2	422923	212403	0	0
T3	1565	67	0	0
T4	4518	64	0	0
T5	129797	18283	0	0
T6	418629	260811	0	0
T7	139181	133905	0	0
T12	3857	188	0	0
T13	1276	67	0	0
T18	984	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310196761	96728254	0	0
T1	1406	32	0	0
T2	422923	212403	0	0
T3	1565	67	0	0
T4	4518	64	0	0
T5	129797	18283	0	0
T6	418629	260811	0	0
T7	139181	133905	0	0
T12	3857	188	0	0
T13	1276	67	0	0
T18	984	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310196761	309467457	0	0
T1	1406	1326	0	0
T2	422923	422914	0	0
T3	1565	1278	0	0
T4	4518	4362	0	0
T5	129797	129647	0	0
T6	418629	418623	0	0
T7	139181	139112	0	0
T12	3857	3159	0	0
T13	1276	1052	0	0
T18	984	902	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310196761	309467457	0	0
T1	1406	1326	0	0
T2	422923	422914	0	0
T3	1565	1278	0	0
T4	4518	4362	0	0
T5	129797	129647	0	0
T6	418629	418623	0	0
T7	139181	139112	0	0
T12	3857	3159	0	0
T13	1276	1052	0	0
T18	984	902	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310196761	96728254	0	0
T1	1406	32	0	0
T2	422923	212403	0	0
T3	1565	67	0	0
T4	4518	64	0	0
T5	129797	18283	0	0
T6	418629	260811	0	0
T7	139181	133905	0	0
T12	3857	188	0	0
T13	1276	67	0	0
T18	984	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310196761	37239108	0	0
T1	1406	128	0	0
T2	422923	1696	0	0
T3	1565	268	0	0
T4	4518	256	0	0
T5	129797	48951	0	0
T6	418629	1696	0	0
T7	139181	357	0	0
T12	3857	704	0	0
T13	1276	268	0	0
T18	984	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310196761	102028329	0	0
T1	1406	32	0	0
T2	422923	212403	0	0
T3	1565	67	0	0
T4	4518	64	0	0
T5	129797	19267	0	0
T6	418629	260811	0	0
T7	139181	133927	0	0
T12	3857	188	0	0
T13	1276	67	0	0
T18	984	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310196761	96728254	0	0
T1	1406	32	0	0
T2	422923	212403	0	0
T3	1565	67	0	0
T4	4518	64	0	0
T5	129797	18283	0	0
T6	418629	260811	0	0
T7	139181	133905	0	0
T12	3857	188	0	0
T13	1276	67	0	0
T18	984	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310196761	96728254	0	0
T1	1406	32	0	0
T2	422923	212403	0	0
T3	1565	67	0	0
T4	4518	64	0	0
T5	129797	18283	0	0
T6	418629	260811	0	0
T7	139181	133905	0	0
T12	3857	188	0	0
T13	1276	67	0	0
T18	984	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310196761	102028329	0	0
T1	1406	32	0	0
T2	422923	212403	0	0
T3	1565	67	0	0
T4	4518	64	0	0
T5	129797	19267	0	0
T6	418629	260811	0	0
T7	139181	133927	0	0
T12	3857	188	0	0
T13	1276	67	0	0
T18	984	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310196761	309467457	0	0
T1	1406	1326	0	0
T2	422923	422914	0	0
T3	1565	1278	0	0
T4	4518	4362	0	0
T5	129797	129647	0	0
T6	418629	418623	0	0
T7	139181	139112	0	0
T12	3857	3159	0	0
T13	1276	1052	0	0
T18	984	902	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T7,T8

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T7,T8
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T7,T8
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T7,T8

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T7,T8
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T7,T8
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T7,T8

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T7,T8

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	310196761	309467457	0	0
CheckNGreaterZero_A	860	860	0	0
GntImpliesReady_A	310196761	96699120	0	0
GntImpliesValid_A	310196761	96699120	0	0
GrantKnown_A	310196761	309467457	0	0
IdxKnown_A	310196761	309467457	0	0
IndexIsCorrect_A	310196761	96699120	0	0
NoReadyValidNoGrant_A	310196761	37239108	0	0
Priority_A	310196761	101999195	0	0
ReadyAndValidImplyGrant_A	310196761	96699120	0	0
ReqAndReadyImplyGrant_A	310196761	96699120	0	0
ReqImpliesValid_A	310196761	101999195	0	0
ValidKnown_A	310196761	309467457	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310196761	309467457	0	0
T1	1406	1326	0	0
T2	422923	422914	0	0
T3	1565	1278	0	0
T4	4518	4362	0	0
T5	129797	129647	0	0
T6	418629	418623	0	0
T7	139181	139112	0	0
T12	3857	3159	0	0
T13	1276	1052	0	0
T18	984	902	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	860	860	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T18	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310196761	96699120	0	0
T1	1406	32	0	0
T2	422923	212403	0	0
T3	1565	67	0	0
T4	4518	64	0	0
T5	129797	18283	0	0
T6	418629	260811	0	0
T7	139181	133905	0	0
T12	3857	188	0	0
T13	1276	67	0	0
T18	984	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310196761	96699120	0	0
T1	1406	32	0	0
T2	422923	212403	0	0
T3	1565	67	0	0
T4	4518	64	0	0
T5	129797	18283	0	0
T6	418629	260811	0	0
T7	139181	133905	0	0
T12	3857	188	0	0
T13	1276	67	0	0
T18	984	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310196761	309467457	0	0
T1	1406	1326	0	0
T2	422923	422914	0	0
T3	1565	1278	0	0
T4	4518	4362	0	0
T5	129797	129647	0	0
T6	418629	418623	0	0
T7	139181	139112	0	0
T12	3857	3159	0	0
T13	1276	1052	0	0
T18	984	902	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310196761	309467457	0	0
T1	1406	1326	0	0
T2	422923	422914	0	0
T3	1565	1278	0	0
T4	4518	4362	0	0
T5	129797	129647	0	0
T6	418629	418623	0	0
T7	139181	139112	0	0
T12	3857	3159	0	0
T13	1276	1052	0	0
T18	984	902	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310196761	96699120	0	0
T1	1406	32	0	0
T2	422923	212403	0	0
T3	1565	67	0	0
T4	4518	64	0	0
T5	129797	18283	0	0
T6	418629	260811	0	0
T7	139181	133905	0	0
T12	3857	188	0	0
T13	1276	67	0	0
T18	984	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310196761	37239108	0	0
T1	1406	128	0	0
T2	422923	1696	0	0
T3	1565	268	0	0
T4	4518	256	0	0
T5	129797	48951	0	0
T6	418629	1696	0	0
T7	139181	357	0	0
T12	3857	704	0	0
T13	1276	268	0	0
T18	984	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310196761	101999195	0	0
T1	1406	32	0	0
T2	422923	212403	0	0
T3	1565	67	0	0
T4	4518	64	0	0
T5	129797	19267	0	0
T6	418629	260811	0	0
T7	139181	133927	0	0
T12	3857	188	0	0
T13	1276	67	0	0
T18	984	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310196761	96699120	0	0
T1	1406	32	0	0
T2	422923	212403	0	0
T3	1565	67	0	0
T4	4518	64	0	0
T5	129797	18283	0	0
T6	418629	260811	0	0
T7	139181	133905	0	0
T12	3857	188	0	0
T13	1276	67	0	0
T18	984	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310196761	96699120	0	0
T1	1406	32	0	0
T2	422923	212403	0	0
T3	1565	67	0	0
T4	4518	64	0	0
T5	129797	18283	0	0
T6	418629	260811	0	0
T7	139181	133905	0	0
T12	3857	188	0	0
T13	1276	67	0	0
T18	984	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310196761	101999195	0	0
T1	1406	32	0	0
T2	422923	212403	0	0
T3	1565	67	0	0
T4	4518	64	0	0
T5	129797	19267	0	0
T6	418629	260811	0	0
T7	139181	133927	0	0
T12	3857	188	0	0
T13	1276	67	0	0
T18	984	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310196761	309467457	0	0
T1	1406	1326	0	0
T2	422923	422914	0	0
T3	1565	1278	0	0
T4	4518	4362	0	0
T5	129797	129647	0	0
T6	418629	418623	0	0
T7	139181	139112	0	0
T12	3857	3159	0	0
T13	1276	1052	0	0
T18	984	902	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
1	0	Covered	T4,T5,T7

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T7
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T7
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Covered	T2,T4,T5
1	1	Covered	T4,T5,T7

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T7
1	1	Covered	T2,T4,T5

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T7,T8
1	1	Covered	T2,T4,T5

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T7

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T7

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	310196761	309467457	0	0
CheckNGreaterZero_A	860	860	0	0
GntImpliesReady_A	310196761	76605530	0	0
GntImpliesValid_A	310196761	76605530	0	0
GrantKnown_A	310196761	309467457	0	0
IdxKnown_A	310196761	309467457	0	0
IndexIsCorrect_A	310196761	76605530	0	0
NoReadyValidNoGrant_A	310196761	33875752	0	0
Priority_A	310196761	81882272	0	0
ReadyAndValidImplyGrant_A	310196761	76605530	0	0
ReqAndReadyImplyGrant_A	310196761	76605530	0	0
ReqImpliesValid_A	310196761	81882272	0	0
ValidKnown_A	310196761	309467457	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310196761	309467457	0	0
T1	1406	1326	0	0
T2	422923	422914	0	0
T3	1565	1278	0	0
T4	4518	4362	0	0
T5	129797	129647	0	0
T6	418629	418623	0	0
T7	139181	139112	0	0
T12	3857	3159	0	0
T13	1276	1052	0	0
T18	984	902	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	860	860	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T18	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310196761	76605530	0	0
T2	422923	208417	0	0
T3	1565	0	0	0
T4	4518	270	0	0
T5	129797	15283	0	0
T6	418629	154455	0	0
T7	139181	1370	0	0
T8	0	13131	0	0
T12	3857	0	0	0
T13	1276	0	0	0
T18	984	0	0	0
T19	0	15835	0	0
T33	0	187	0	0
T41	0	15057	0	0
T42	1253	0	0	0
T50	0	127897	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310196761	76605530	0	0
T2	422923	208417	0	0
T3	1565	0	0	0
T4	4518	270	0	0
T5	129797	15283	0	0
T6	418629	154455	0	0
T7	139181	1370	0	0
T8	0	13131	0	0
T12	3857	0	0	0
T13	1276	0	0	0
T18	984	0	0	0
T19	0	15835	0	0
T33	0	187	0	0
T41	0	15057	0	0
T42	1253	0	0	0
T50	0	127897	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310196761	309467457	0	0
T1	1406	1326	0	0
T2	422923	422914	0	0
T3	1565	1278	0	0
T4	4518	4362	0	0
T5	129797	129647	0	0
T6	418629	418623	0	0
T7	139181	139112	0	0
T12	3857	3159	0	0
T13	1276	1052	0	0
T18	984	902	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310196761	309467457	0	0
T1	1406	1326	0	0
T2	422923	422914	0	0
T3	1565	1278	0	0
T4	4518	4362	0	0
T5	129797	129647	0	0
T6	418629	418623	0	0
T7	139181	139112	0	0
T12	3857	3159	0	0
T13	1276	1052	0	0
T18	984	902	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310196761	76605530	0	0
T2	422923	208417	0	0
T3	1565	0	0	0
T4	4518	270	0	0
T5	129797	15283	0	0
T6	418629	154455	0	0
T7	139181	1370	0	0
T8	0	13131	0	0
T12	3857	0	0	0
T13	1276	0	0	0
T18	984	0	0	0
T19	0	15835	0	0
T33	0	187	0	0
T41	0	15057	0	0
T42	1253	0	0	0
T50	0	127897	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310196761	33875752	0	0
T4	4518	651	0	0
T5	129797	41340	0	0
T6	418629	0	0	0
T7	139181	360	0	0
T8	0	435497	0	0
T12	3857	0	0	0
T13	1276	0	0	0
T18	984	0	0	0
T19	0	491206	0	0
T23	0	49669	0	0
T33	2198	196	0	0
T41	0	485652	0	0
T42	1253	0	0	0
T43	1306	0	0	0
T45	0	1013	0	0
T50	0	524288	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310196761	81882272	0	0
T2	422923	208417	0	0
T3	1565	0	0	0
T4	4518	270	0	0
T5	129797	16148	0	0
T6	418629	154455	0	0
T7	139181	1401	0	0
T8	0	109366	0	0
T12	3857	0	0	0
T13	1276	0	0	0
T18	984	0	0	0
T19	0	168361	0	0
T33	0	187	0	0
T41	0	158362	0	0
T42	1253	0	0	0
T50	0	127897	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310196761	76605530	0	0
T2	422923	208417	0	0
T3	1565	0	0	0
T4	4518	270	0	0
T5	129797	15283	0	0
T6	418629	154455	0	0
T7	139181	1370	0	0
T8	0	13131	0	0
T12	3857	0	0	0
T13	1276	0	0	0
T18	984	0	0	0
T19	0	15835	0	0
T33	0	187	0	0
T41	0	15057	0	0
T42	1253	0	0	0
T50	0	127897	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310196761	76605530	0	0
T2	422923	208417	0	0
T3	1565	0	0	0
T4	4518	270	0	0
T5	129797	15283	0	0
T6	418629	154455	0	0
T7	139181	1370	0	0
T8	0	13131	0	0
T12	3857	0	0	0
T13	1276	0	0	0
T18	984	0	0	0
T19	0	15835	0	0
T33	0	187	0	0
T41	0	15057	0	0
T42	1253	0	0	0
T50	0	127897	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310196761	81882272	0	0
T2	422923	208417	0	0
T3	1565	0	0	0
T4	4518	270	0	0
T5	129797	16148	0	0
T6	418629	154455	0	0
T7	139181	1401	0	0
T8	0	109366	0	0
T12	3857	0	0	0
T13	1276	0	0	0
T18	984	0	0	0
T19	0	168361	0	0
T33	0	187	0	0
T41	0	158362	0	0
T42	1253	0	0	0
T50	0	127897	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310196761	309467457	0	0
T1	1406	1326	0	0
T2	422923	422914	0	0
T3	1565	1278	0	0
T4	4518	4362	0	0
T5	129797	129647	0	0
T6	418629	418623	0	0
T7	139181	139112	0	0
T12	3857	3159	0	0
T13	1276	1052	0	0
T18	984	902	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
1	0	Covered	T4,T5,T7

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T7
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T7
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Covered	T2,T4,T5
1	1	Covered	T4,T5,T7

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T7
1	1	Covered	T2,T4,T5

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T7,T8
1	1	Covered	T2,T4,T5

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T7

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T7

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	310196761	309467457	0	0
CheckNGreaterZero_A	860	860	0	0
GntImpliesReady_A	310196761	76605530	0	0
GntImpliesValid_A	310196761	76605530	0	0
GrantKnown_A	310196761	309467457	0	0
IdxKnown_A	310196761	309467457	0	0
IndexIsCorrect_A	310196761	76605530	0	0
NoReadyValidNoGrant_A	310196761	33875752	0	0
Priority_A	310196761	81882272	0	0
ReadyAndValidImplyGrant_A	310196761	76605530	0	0
ReqAndReadyImplyGrant_A	310196761	76605530	0	0
ReqImpliesValid_A	310196761	81882272	0	0
ValidKnown_A	310196761	309467457	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310196761	309467457	0	0
T1	1406	1326	0	0
T2	422923	422914	0	0
T3	1565	1278	0	0
T4	4518	4362	0	0
T5	129797	129647	0	0
T6	418629	418623	0	0
T7	139181	139112	0	0
T12	3857	3159	0	0
T13	1276	1052	0	0
T18	984	902	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	860	860	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T18	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310196761	76605530	0	0
T2	422923	208417	0	0
T3	1565	0	0	0
T4	4518	270	0	0
T5	129797	15283	0	0
T6	418629	154455	0	0
T7	139181	1370	0	0
T8	0	13131	0	0
T12	3857	0	0	0
T13	1276	0	0	0
T18	984	0	0	0
T19	0	15835	0	0
T33	0	187	0	0
T41	0	15057	0	0
T42	1253	0	0	0
T50	0	127897	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310196761	76605530	0	0
T2	422923	208417	0	0
T3	1565	0	0	0
T4	4518	270	0	0
T5	129797	15283	0	0
T6	418629	154455	0	0
T7	139181	1370	0	0
T8	0	13131	0	0
T12	3857	0	0	0
T13	1276	0	0	0
T18	984	0	0	0
T19	0	15835	0	0
T33	0	187	0	0
T41	0	15057	0	0
T42	1253	0	0	0
T50	0	127897	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310196761	309467457	0	0
T1	1406	1326	0	0
T2	422923	422914	0	0
T3	1565	1278	0	0
T4	4518	4362	0	0
T5	129797	129647	0	0
T6	418629	418623	0	0
T7	139181	139112	0	0
T12	3857	3159	0	0
T13	1276	1052	0	0
T18	984	902	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310196761	309467457	0	0
T1	1406	1326	0	0
T2	422923	422914	0	0
T3	1565	1278	0	0
T4	4518	4362	0	0
T5	129797	129647	0	0
T6	418629	418623	0	0
T7	139181	139112	0	0
T12	3857	3159	0	0
T13	1276	1052	0	0
T18	984	902	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310196761	76605530	0	0
T2	422923	208417	0	0
T3	1565	0	0	0
T4	4518	270	0	0
T5	129797	15283	0	0
T6	418629	154455	0	0
T7	139181	1370	0	0
T8	0	13131	0	0
T12	3857	0	0	0
T13	1276	0	0	0
T18	984	0	0	0
T19	0	15835	0	0
T33	0	187	0	0
T41	0	15057	0	0
T42	1253	0	0	0
T50	0	127897	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310196761	33875752	0	0
T4	4518	651	0	0
T5	129797	41340	0	0
T6	418629	0	0	0
T7	139181	360	0	0
T8	0	435497	0	0
T12	3857	0	0	0
T13	1276	0	0	0
T18	984	0	0	0
T19	0	491206	0	0
T23	0	49669	0	0
T33	2198	196	0	0
T41	0	485652	0	0
T42	1253	0	0	0
T43	1306	0	0	0
T45	0	1013	0	0
T50	0	524288	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310196761	81882272	0	0
T2	422923	208417	0	0
T3	1565	0	0	0
T4	4518	270	0	0
T5	129797	16148	0	0
T6	418629	154455	0	0
T7	139181	1401	0	0
T8	0	109366	0	0
T12	3857	0	0	0
T13	1276	0	0	0
T18	984	0	0	0
T19	0	168361	0	0
T33	0	187	0	0
T41	0	158362	0	0
T42	1253	0	0	0
T50	0	127897	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310196761	76605530	0	0
T2	422923	208417	0	0
T3	1565	0	0	0
T4	4518	270	0	0
T5	129797	15283	0	0
T6	418629	154455	0	0
T7	139181	1370	0	0
T8	0	13131	0	0
T12	3857	0	0	0
T13	1276	0	0	0
T18	984	0	0	0
T19	0	15835	0	0
T33	0	187	0	0
T41	0	15057	0	0
T42	1253	0	0	0
T50	0	127897	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310196761	76605530	0	0
T2	422923	208417	0	0
T3	1565	0	0	0
T4	4518	270	0	0
T5	129797	15283	0	0
T6	418629	154455	0	0
T7	139181	1370	0	0
T8	0	13131	0	0
T12	3857	0	0	0
T13	1276	0	0	0
T18	984	0	0	0
T19	0	15835	0	0
T33	0	187	0	0
T41	0	15057	0	0
T42	1253	0	0	0
T50	0	127897	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310196761	81882272	0	0
T2	422923	208417	0	0
T3	1565	0	0	0
T4	4518	270	0	0
T5	129797	16148	0	0
T6	418629	154455	0	0
T7	139181	1401	0	0
T8	0	109366	0	0
T12	3857	0	0	0
T13	1276	0	0	0
T18	984	0	0	0
T19	0	168361	0	0
T33	0	187	0	0
T41	0	158362	0	0
T42	1253	0	0	0
T50	0	127897	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310196761	309467457	0	0
T1	1406	1326	0	0
T2	422923	422914	0	0
T3	1565	1278	0	0
T4	4518	4362	0	0
T5	129797	129647	0	0
T6	418629	418623	0	0
T7	139181	139112	0	0
T12	3857	3159	0	0
T13	1276	1052	0	0
T18	984	902	0	0