Unified Coverage Report :: Module :: flash_ctrl_core_csr_assert_fpv

Module : flash_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_flash_ctrl_csr_assert_0/flash_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.flash_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.flash_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.36	97.14	92.91	98.44		100.00	98.33	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : flash_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	87	87	100.00	87	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	87	87	100.00	87	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	311579167	1132	0	0
addr_rd_A	311579167	687	0	0
bank0_info0_page_cfg_0_rd_A	311579167	2269	0	0
bank0_info0_page_cfg_1_rd_A	311579167	2043	0	0
bank0_info0_page_cfg_2_rd_A	311579167	1900	0	0
bank0_info0_page_cfg_3_rd_A	311579167	2227	0	0
bank0_info0_page_cfg_4_rd_A	311579167	2594	0	0
bank0_info0_page_cfg_5_rd_A	311579167	2387	0	0
bank0_info0_page_cfg_6_rd_A	311579167	2503	0	0
bank0_info0_page_cfg_7_rd_A	311579167	1904	0	0
bank0_info0_page_cfg_8_rd_A	311579167	2462	0	0
bank0_info0_page_cfg_9_rd_A	311579167	2321	0	0
bank0_info0_regwen_0_rd_A	311579167	1070	0	0
bank0_info0_regwen_1_rd_A	311579167	1377	0	0
bank0_info0_regwen_2_rd_A	311579167	1155	0	0
bank0_info0_regwen_3_rd_A	311579167	1650	0	0
bank0_info0_regwen_4_rd_A	311579167	1358	0	0
bank0_info0_regwen_5_rd_A	311579167	1662	0	0
bank0_info0_regwen_6_rd_A	311579167	1344	0	0
bank0_info0_regwen_7_rd_A	311579167	1771	0	0
bank0_info0_regwen_8_rd_A	311579167	1707	0	0
bank0_info0_regwen_9_rd_A	311579167	1175	0	0
bank0_info1_page_cfg_rd_A	311579167	1789	0	0
bank0_info1_regwen_rd_A	311579167	652	0	0
bank0_info2_page_cfg_0_rd_A	311579167	1724	0	0
bank0_info2_page_cfg_1_rd_A	311579167	2326	0	0
bank0_info2_regwen_0_rd_A	311579167	1541	0	0
bank0_info2_regwen_1_rd_A	311579167	1165	0	0
bank1_info0_page_cfg_0_rd_A	311579167	1920	0	0
bank1_info0_page_cfg_1_rd_A	311579167	2121	0	0
bank1_info0_page_cfg_2_rd_A	311579167	2056	0	0
bank1_info0_page_cfg_3_rd_A	311579167	2019	0	0
bank1_info0_page_cfg_4_rd_A	311579167	1825	0	0
bank1_info0_page_cfg_5_rd_A	311579167	2055	0	0
bank1_info0_page_cfg_6_rd_A	311579167	2571	0	0
bank1_info0_page_cfg_7_rd_A	311579167	2528	0	0
bank1_info0_page_cfg_8_rd_A	311579167	2043	0	0
bank1_info0_page_cfg_9_rd_A	311579167	1999	0	0
bank1_info0_regwen_0_rd_A	311579167	1702	0	0
bank1_info0_regwen_1_rd_A	311579167	1611	0	0
bank1_info0_regwen_2_rd_A	311579167	863	0	0
bank1_info0_regwen_3_rd_A	311579167	1722	0	0
bank1_info0_regwen_4_rd_A	311579167	1522	0	0
bank1_info0_regwen_5_rd_A	311579167	1695	0	0
bank1_info0_regwen_6_rd_A	311579167	1334	0	0
bank1_info0_regwen_7_rd_A	311579167	1648	0	0
bank1_info0_regwen_8_rd_A	311579167	1629	0	0
bank1_info0_regwen_9_rd_A	311579167	1079	0	0
bank1_info1_page_cfg_rd_A	311579167	2022	0	0
bank1_info1_regwen_rd_A	311579167	1429	0	0
bank1_info2_page_cfg_0_rd_A	311579167	2676	0	0
bank1_info2_page_cfg_1_rd_A	311579167	2268	0	0
bank1_info2_regwen_0_rd_A	311579167	1721	0	0
bank1_info2_regwen_1_rd_A	311579167	1581	0	0
bank_cfg_regwen_rd_A	311579167	1322	0	0
default_region_rd_A	311579167	2100	0	0
exec_rd_A	311579167	1152	0	0
fifo_lvl_rd_A	311579167	762	0	0
fifo_rst_rd_A	311579167	1360	0	0
hw_info_cfg_override_rd_A	311579167	1762	0	0
intr_enable_rd_A	311579167	1933	0	0
mp_region_0_rd_A	311579167	1501	0	0
mp_region_1_rd_A	311579167	1553	0	0
mp_region_2_rd_A	311579167	1004	0	0
mp_region_3_rd_A	311579167	1860	0	0
mp_region_4_rd_A	311579167	1868	0	0
mp_region_5_rd_A	311579167	1314	0	0
mp_region_6_rd_A	311579167	1674	0	0
mp_region_7_rd_A	311579167	1304	0	0
mp_region_cfg_0_rd_A	311579167	1685	0	0
mp_region_cfg_1_rd_A	311579167	2478	0	0
mp_region_cfg_2_rd_A	311579167	2241	0	0
mp_region_cfg_3_rd_A	311579167	2041	0	0
mp_region_cfg_4_rd_A	311579167	2296	0	0
mp_region_cfg_5_rd_A	311579167	2303	0	0
mp_region_cfg_6_rd_A	311579167	2589	0	0
mp_region_cfg_7_rd_A	311579167	2050	0	0
phy_alert_cfg_rd_A	311579167	1275	0	0
region_cfg_regwen_0_rd_A	311579167	1671	0	0
region_cfg_regwen_1_rd_A	311579167	1503	0	0
region_cfg_regwen_2_rd_A	311579167	1662	0	0
region_cfg_regwen_3_rd_A	311579167	1703	0	0
region_cfg_regwen_4_rd_A	311579167	1579	0	0
region_cfg_regwen_5_rd_A	311579167	1684	0	0
region_cfg_regwen_6_rd_A	311579167	1056	0	0
region_cfg_regwen_7_rd_A	311579167	1558	0	0
scratch_rd_A	311579167	1582	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	1132	0	0
T203	44057	3	0	0
T204	2115	1	0	0
T221	0	44	0	0
T222	0	16	0	0
T223	0	1	0	0
T233	0	327	0	0
T234	0	169	0	0
T235	0	2	0	0
T236	0	181	0	0
T242	0	3	0	0
T251	807	0	0	0
T252	3618	0	0	0
T253	1021	0	0	0
T254	915	0	0	0
T255	1260	0	0	0
T278	73554	0	0	0
T279	3258	0	0	0
T280	1349	0	0	0

addr_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	687	0	0
T53	21520	32	0	0
T54	5759	0	0	0
T55	7048	0	0	0
T200	84433	75	0	0
T208	1068	0	0	0
T209	1546	0	0	0
T223	0	37	0	0
T224	0	7	0	0
T235	0	34	0	0
T238	942	0	0	0
T239	15366	0	0	0
T240	11496	60	0	0
T242	0	84	0	0
T252	0	8	0	0
T278	0	277	0	0
T281	0	5	0	0
T282	1342	0	0	0

bank0_info0_page_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	2269	0	0
T53	21520	37	0	0
T54	5759	0	0	0
T55	7048	0	0	0
T200	84433	250	0	0
T208	1068	0	0	0
T209	1546	0	0	0
T223	0	108	0	0
T224	0	4	0	0
T235	0	102	0	0
T238	942	0	0	0
T239	15366	0	0	0
T240	11496	27	0	0
T242	0	255	0	0
T252	0	5	0	0
T278	0	299	0	0
T281	0	2	0	0
T282	1342	0	0	0

bank0_info0_page_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	2043	0	0
T53	21520	48	0	0
T54	5759	0	0	0
T55	7048	0	0	0
T200	84433	322	0	0
T208	1068	0	0	0
T209	1546	0	0	0
T223	0	139	0	0
T224	0	7	0	0
T235	0	153	0	0
T238	942	0	0	0
T239	15366	0	0	0
T240	11496	34	0	0
T242	0	229	0	0
T252	0	17	0	0
T278	0	272	0	0
T281	0	12	0	0
T282	1342	0	0	0

bank0_info0_page_cfg_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	1900	0	0
T53	21520	82	0	0
T54	5759	0	0	0
T55	7048	0	0	0
T200	84433	306	0	0
T208	1068	0	0	0
T209	1546	0	0	0
T223	0	103	0	0
T224	0	12	0	0
T235	0	223	0	0
T238	942	0	0	0
T239	15366	0	0	0
T240	11496	7	0	0
T242	0	342	0	0
T243	0	227	0	0
T252	0	15	0	0
T281	0	27	0	0
T282	1342	0	0	0

bank0_info0_page_cfg_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	2227	0	0
T53	21520	22	0	0
T54	5759	0	0	0
T55	7048	0	0	0
T200	84433	268	0	0
T208	1068	0	0	0
T209	1546	0	0	0
T223	0	173	0	0
T224	0	7	0	0
T235	0	129	0	0
T238	942	0	0	0
T239	15366	0	0	0
T240	11496	9	0	0
T242	0	323	0	0
T252	0	25	0	0
T278	0	213	0	0
T281	0	1	0	0
T282	1342	0	0	0

bank0_info0_page_cfg_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	2594	0	0
T53	21520	40	0	0
T54	5759	0	0	0
T55	7048	0	0	0
T200	84433	344	0	0
T208	1068	0	0	0
T209	1546	0	0	0
T223	0	195	0	0
T224	0	10	0	0
T235	0	170	0	0
T238	942	0	0	0
T239	15366	0	0	0
T240	11496	13	0	0
T242	0	387	0	0
T243	0	162	0	0
T252	0	26	0	0
T278	0	254	0	0
T282	1342	0	0	0

bank0_info0_page_cfg_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	2387	0	0
T53	21520	76	0	0
T54	5759	0	0	0
T55	7048	0	0	0
T200	84433	264	0	0
T208	1068	0	0	0
T209	1546	0	0	0
T223	0	153	0	0
T224	0	1	0	0
T235	0	153	0	0
T238	942	0	0	0
T239	15366	0	0	0
T240	11496	17	0	0
T242	0	231	0	0
T252	0	22	0	0
T278	0	293	0	0
T281	0	6	0	0
T282	1342	0	0	0

bank0_info0_page_cfg_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	2503	0	0
T53	21520	26	0	0
T54	5759	0	0	0
T55	7048	0	0	0
T200	84433	397	0	0
T208	1068	0	0	0
T209	1546	0	0	0
T223	0	165	0	0
T224	0	10	0	0
T235	0	209	0	0
T238	942	0	0	0
T239	15366	0	0	0
T240	11496	23	0	0
T242	0	340	0	0
T243	0	214	0	0
T252	0	19	0	0
T281	0	11	0	0
T282	1342	0	0	0

bank0_info0_page_cfg_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	1904	0	0
T53	21520	34	0	0
T54	5759	0	0	0
T55	7048	0	0	0
T200	84433	259	0	0
T208	1068	0	0	0
T209	1546	0	0	0
T223	0	179	0	0
T224	0	10	0	0
T235	0	153	0	0
T238	942	0	0	0
T239	15366	0	0	0
T240	11496	24	0	0
T242	0	280	0	0
T252	0	4	0	0
T278	0	266	0	0
T281	0	7	0	0
T282	1342	0	0	0

bank0_info0_page_cfg_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	2462	0	0
T53	21520	58	0	0
T54	5759	0	0	0
T55	7048	0	0	0
T200	84433	220	0	0
T208	1068	0	0	0
T209	1546	0	0	0
T223	0	174	0	0
T224	0	10	0	0
T235	0	148	0	0
T238	942	0	0	0
T239	15366	0	0	0
T240	11496	20	0	0
T242	0	307	0	0
T252	0	6	0	0
T278	0	293	0	0
T281	0	18	0	0
T282	1342	0	0	0

bank0_info0_page_cfg_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	2321	0	0
T53	21520	75	0	0
T54	5759	0	0	0
T55	7048	0	0	0
T200	84433	348	0	0
T208	1068	0	0	0
T209	1546	0	0	0
T223	0	172	0	0
T224	0	5	0	0
T235	0	145	0	0
T238	942	0	0	0
T239	15366	0	0	0
T240	11496	11	0	0
T242	0	217	0	0
T243	0	184	0	0
T252	0	3	0	0
T278	0	226	0	0
T282	1342	0	0	0

bank0_info0_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	1070	0	0
T53	21520	46	0	0
T54	5759	0	0	0
T55	7048	0	0	0
T200	84433	62	0	0
T208	1068	0	0	0
T209	1546	0	0	0
T223	0	24	0	0
T224	0	2	0	0
T235	0	40	0	0
T238	942	0	0	0
T239	15366	0	0	0
T240	11496	29	0	0
T242	0	87	0	0
T243	0	41	0	0
T278	0	229	0	0
T281	0	7	0	0
T282	1342	0	0	0

bank0_info0_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	1377	0	0
T53	21520	41	0	0
T54	5759	0	0	0
T55	7048	0	0	0
T200	84433	106	0	0
T208	1068	0	0	0
T209	1546	0	0	0
T223	0	46	0	0
T224	0	7	0	0
T235	0	43	0	0
T238	942	0	0	0
T239	15366	0	0	0
T240	11496	32	0	0
T242	0	75	0	0
T243	0	45	0	0
T282	1342	0	0	0
T283	0	917	0	0
T284	0	65	0	0

bank0_info0_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	1155	0	0
T53	21520	27	0	0
T54	5759	0	0	0
T55	7048	0	0	0
T200	84433	81	0	0
T208	1068	0	0	0
T209	1546	0	0	0
T223	0	34	0	0
T224	0	4	0	0
T235	0	81	0	0
T238	942	0	0	0
T239	15366	0	0	0
T240	11496	35	0	0
T242	0	100	0	0
T252	0	8	0	0
T278	0	232	0	0
T281	0	3	0	0
T282	1342	0	0	0

bank0_info0_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	1650	0	0
T53	21520	71	0	0
T54	5759	0	0	0
T55	7048	0	0	0
T200	84433	78	0	0
T208	1068	0	0	0
T209	1546	0	0	0
T223	0	34	0	0
T224	0	5	0	0
T235	0	50	0	0
T238	942	0	0	0
T239	15366	0	0	0
T240	11496	21	0	0
T242	0	94	0	0
T252	0	7	0	0
T278	0	295	0	0
T281	0	4	0	0
T282	1342	0	0	0

bank0_info0_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	1358	0	0
T53	21520	44	0	0
T54	5759	0	0	0
T55	7048	0	0	0
T200	84433	72	0	0
T208	1068	0	0	0
T209	1546	0	0	0
T223	0	31	0	0
T224	0	5	0	0
T235	0	51	0	0
T238	942	0	0	0
T239	15366	0	0	0
T240	11496	23	0	0
T242	0	90	0	0
T243	0	48	0	0
T252	0	6	0	0
T282	1342	0	0	0
T283	0	959	0	0

bank0_info0_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	1662	0	0
T53	21520	50	0	0
T54	5759	0	0	0
T55	7048	0	0	0
T200	84433	70	0	0
T208	1068	0	0	0
T209	1546	0	0	0
T223	0	32	0	0
T224	0	7	0	0
T235	0	47	0	0
T238	942	0	0	0
T239	15366	0	0	0
T240	11496	31	0	0
T242	0	76	0	0
T243	0	61	0	0
T252	0	2	0	0
T278	0	244	0	0
T282	1342	0	0	0

bank0_info0_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	1344	0	0
T53	21520	58	0	0
T54	5759	0	0	0
T55	7048	0	0	0
T200	84433	75	0	0
T208	1068	0	0	0
T209	1546	0	0	0
T223	0	25	0	0
T224	0	11	0	0
T235	0	44	0	0
T238	942	0	0	0
T239	15366	0	0	0
T240	11496	17	0	0
T242	0	61	0	0
T243	0	65	0	0
T252	0	5	0	0
T282	1342	0	0	0
T283	0	953	0	0

bank0_info0_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	1771	0	0
T53	21520	73	0	0
T54	5759	0	0	0
T55	7048	0	0	0
T200	84433	67	0	0
T208	1068	0	0	0
T209	1546	0	0	0
T223	0	51	0	0
T224	0	9	0	0
T235	0	25	0	0
T238	942	0	0	0
T239	15366	0	0	0
T240	11496	0	0	0
T242	0	71	0	0
T243	0	62	0	0
T252	0	8	0	0
T278	0	258	0	0
T281	0	9	0	0
T282	1342	0	0	0

bank0_info0_regwen_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	1707	0	0
T53	21520	21	0	0
T54	5759	0	0	0
T55	7048	0	0	0
T200	84433	68	0	0
T208	1068	0	0	0
T209	1546	0	0	0
T223	0	47	0	0
T224	0	10	0	0
T235	0	45	0	0
T238	942	0	0	0
T239	15366	0	0	0
T240	11496	29	0	0
T242	0	79	0	0
T252	0	5	0	0
T278	0	342	0	0
T281	0	2	0	0
T282	1342	0	0	0

bank0_info0_regwen_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	1175	0	0
T53	21520	34	0	0
T54	5759	0	0	0
T55	7048	0	0	0
T200	84433	89	0	0
T208	1068	0	0	0
T209	1546	0	0	0
T223	0	55	0	0
T224	0	7	0	0
T235	0	56	0	0
T238	942	0	0	0
T239	15366	0	0	0
T240	11496	29	0	0
T242	0	89	0	0
T243	0	35	0	0
T278	0	297	0	0
T281	0	9	0	0
T282	1342	0	0	0

bank0_info1_page_cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	1789	0	0
T53	21520	55	0	0
T54	5759	0	0	0
T55	7048	0	0	0
T200	84433	328	0	0
T208	1068	0	0	0
T209	1546	0	0	0
T223	0	218	0	0
T224	0	4	0	0
T235	0	147	0	0
T238	942	0	0	0
T239	15366	0	0	0
T240	11496	15	0	0
T242	0	340	0	0
T243	0	132	0	0
T252	0	2	0	0
T281	0	15	0	0
T282	1342	0	0	0

bank0_info1_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	652	0	0
T53	21520	66	0	0
T54	5759	0	0	0
T55	7048	0	0	0
T200	84433	63	0	0
T208	1068	0	0	0
T209	1546	0	0	0
T223	0	43	0	0
T224	0	7	0	0
T235	0	38	0	0
T238	942	0	0	0
T239	15366	0	0	0
T240	11496	26	0	0
T242	0	95	0	0
T252	0	6	0	0
T278	0	230	0	0
T281	0	5	0	0
T282	1342	0	0	0

bank0_info2_page_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	1724	0	0
T53	21520	24	0	0
T54	5759	0	0	0
T55	7048	0	0	0
T200	84433	357	0	0
T208	1068	0	0	0
T209	1546	0	0	0
T223	0	141	0	0
T224	0	11	0	0
T235	0	153	0	0
T238	942	0	0	0
T239	15366	0	0	0
T240	11496	24	0	0
T242	0	288	0	0
T243	0	166	0	0
T252	0	25	0	0
T281	0	8	0	0
T282	1342	0	0	0

bank0_info2_page_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	2326	0	0
T53	21520	35	0	0
T54	5759	0	0	0
T55	7048	0	0	0
T200	84433	346	0	0
T208	1068	0	0	0
T209	1546	0	0	0
T223	0	152	0	0
T224	0	7	0	0
T235	0	181	0	0
T238	942	0	0	0
T239	15366	0	0	0
T240	11496	31	0	0
T242	0	348	0	0
T243	0	166	0	0
T252	0	31	0	0
T281	0	9	0	0
T282	1342	0	0	0

bank0_info2_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	1541	0	0
T53	21520	19	0	0
T54	5759	0	0	0
T55	7048	0	0	0
T200	84433	72	0	0
T208	1068	0	0	0
T209	1546	0	0	0
T223	0	61	0	0
T224	0	14	0	0
T235	0	35	0	0
T238	942	0	0	0
T239	15366	0	0	0
T240	11496	20	0	0
T242	0	70	0	0
T243	0	43	0	0
T252	0	6	0	0
T278	0	223	0	0
T282	1342	0	0	0

bank0_info2_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	1165	0	0
T53	21520	56	0	0
T54	5759	0	0	0
T55	7048	0	0	0
T200	84433	86	0	0
T208	1068	0	0	0
T209	1546	0	0	0
T223	0	47	0	0
T224	0	8	0	0
T235	0	63	0	0
T238	942	0	0	0
T239	15366	0	0	0
T240	11496	3	0	0
T242	0	69	0	0
T252	0	2	0	0
T278	0	219	0	0
T281	0	1	0	0
T282	1342	0	0	0

bank1_info0_page_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	1920	0	0
T200	84433	381	0	0
T201	62219	0	0	0
T202	2815	0	0	0
T208	1068	0	0	0
T209	1546	0	0	0
T210	1850	0	0	0
T223	0	126	0	0
T224	0	8	0	0
T235	0	90	0	0
T238	942	0	0	0
T239	15366	0	0	0
T240	11496	41	0	0
T241	1048	0	0	0
T242	0	247	0	0
T243	0	165	0	0
T252	0	2	0	0
T278	0	290	0	0
T281	0	13	0	0

bank1_info0_page_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	2121	0	0
T53	21520	30	0	0
T54	5759	0	0	0
T55	7048	0	0	0
T200	84433	470	0	0
T208	1068	0	0	0
T209	1546	0	0	0
T223	0	154	0	0
T224	0	4	0	0
T235	0	179	0	0
T238	942	0	0	0
T239	15366	0	0	0
T240	11496	11	0	0
T242	0	267	0	0
T252	0	4	0	0
T278	0	266	0	0
T281	0	18	0	0
T282	1342	0	0	0

bank1_info0_page_cfg_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	2056	0	0
T53	21520	51	0	0
T54	5759	0	0	0
T55	7048	0	0	0
T200	84433	417	0	0
T208	1068	0	0	0
T209	1546	0	0	0
T223	0	177	0	0
T224	0	12	0	0
T235	0	167	0	0
T238	942	0	0	0
T239	15366	0	0	0
T240	11496	28	0	0
T242	0	332	0	0
T252	0	5	0	0
T278	0	250	0	0
T281	0	19	0	0
T282	1342	0	0	0

bank1_info0_page_cfg_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	2019	0	0
T53	21520	54	0	0
T54	5759	0	0	0
T55	7048	0	0	0
T200	84433	373	0	0
T208	1068	0	0	0
T209	1546	0	0	0
T223	0	173	0	0
T224	0	9	0	0
T235	0	147	0	0
T238	942	0	0	0
T239	15366	0	0	0
T240	11496	16	0	0
T242	0	305	0	0
T243	0	135	0	0
T252	0	1	0	0
T278	0	255	0	0
T282	1342	0	0	0

bank1_info0_page_cfg_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	1825	0	0
T53	21520	58	0	0
T54	5759	0	0	0
T55	7048	0	0	0
T200	84433	265	0	0
T208	1068	0	0	0
T209	1546	0	0	0
T223	0	117	0	0
T224	0	13	0	0
T235	0	161	0	0
T238	942	0	0	0
T239	15366	0	0	0
T240	11496	6	0	0
T242	0	254	0	0
T243	0	180	0	0
T278	0	247	0	0
T281	0	20	0	0
T282	1342	0	0	0

bank1_info0_page_cfg_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	2055	0	0
T53	21520	40	0	0
T54	5759	0	0	0
T55	7048	0	0	0
T200	84433	407	0	0
T208	1068	0	0	0
T209	1546	0	0	0
T223	0	63	0	0
T224	0	15	0	0
T235	0	181	0	0
T238	942	0	0	0
T239	15366	0	0	0
T240	11496	0	0	0
T242	0	427	0	0
T243	0	118	0	0
T252	0	8	0	0
T278	0	234	0	0
T281	0	19	0	0
T282	1342	0	0	0

bank1_info0_page_cfg_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	2571	0	0
T53	21520	73	0	0
T54	5759	0	0	0
T55	7048	0	0	0
T200	84433	351	0	0
T208	1068	0	0	0
T209	1546	0	0	0
T223	0	201	0	0
T224	0	8	0	0
T235	0	199	0	0
T238	942	0	0	0
T239	15366	0	0	0
T240	11496	38	0	0
T242	0	267	0	0
T252	0	31	0	0
T278	0	244	0	0
T281	0	3	0	0
T282	1342	0	0	0

bank1_info0_page_cfg_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	2528	0	0
T53	21520	29	0	0
T54	5759	0	0	0
T55	7048	0	0	0
T200	84433	299	0	0
T208	1068	0	0	0
T209	1546	0	0	0
T223	0	135	0	0
T224	0	5	0	0
T235	0	132	0	0
T238	942	0	0	0
T239	15366	0	0	0
T240	11496	32	0	0
T242	0	303	0	0
T252	0	6	0	0
T278	0	305	0	0
T281	0	25	0	0
T282	1342	0	0	0

bank1_info0_page_cfg_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	2043	0	0
T53	21520	27	0	0
T54	5759	0	0	0
T55	7048	0	0	0
T200	84433	328	0	0
T208	1068	0	0	0
T209	1546	0	0	0
T223	0	154	0	0
T224	0	11	0	0
T235	0	165	0	0
T238	942	0	0	0
T239	15366	0	0	0
T240	11496	21	0	0
T242	0	242	0	0
T243	0	122	0	0
T252	0	29	0	0
T282	1342	0	0	0
T283	0	902	0	0

bank1_info0_page_cfg_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	1999	0	0
T53	21520	41	0	0
T54	5759	0	0	0
T55	7048	0	0	0
T200	84433	231	0	0
T208	1068	0	0	0
T209	1546	0	0	0
T223	0	141	0	0
T224	0	15	0	0
T235	0	163	0	0
T238	942	0	0	0
T239	15366	0	0	0
T240	11496	22	0	0
T242	0	360	0	0
T252	0	29	0	0
T278	0	294	0	0
T281	0	16	0	0
T282	1342	0	0	0

bank1_info0_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	1702	0	0
T53	21520	30	0	0
T54	5759	0	0	0
T55	7048	0	0	0
T200	84433	79	0	0
T208	1068	0	0	0
T209	1546	0	0	0
T223	0	48	0	0
T224	0	8	0	0
T235	0	50	0	0
T238	942	0	0	0
T239	15366	0	0	0
T240	11496	21	0	0
T242	0	86	0	0
T243	0	45	0	0
T278	0	222	0	0
T282	1342	0	0	0
T283	0	1053	0	0

bank1_info0_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	1611	0	0
T53	21520	21	0	0
T54	5759	0	0	0
T55	7048	0	0	0
T200	84433	76	0	0
T208	1068	0	0	0
T209	1546	0	0	0
T223	0	47	0	0
T224	0	10	0	0
T235	0	70	0	0
T238	942	0	0	0
T239	15366	0	0	0
T240	11496	33	0	0
T242	0	86	0	0
T243	0	20	0	0
T252	0	1	0	0
T278	0	216	0	0
T282	1342	0	0	0

bank1_info0_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	863	0	0
T53	21520	43	0	0
T54	5759	0	0	0
T55	7048	0	0	0
T200	84433	96	0	0
T208	1068	0	0	0
T209	1546	0	0	0
T223	0	53	0	0
T224	0	1	0	0
T235	0	47	0	0
T238	942	0	0	0
T239	15366	0	0	0
T240	11496	8	0	0
T242	0	102	0	0
T243	0	37	0	0
T252	0	1	0	0
T281	0	1	0	0
T282	1342	0	0	0

bank1_info0_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	1722	0	0
T53	21520	57	0	0
T54	5759	0	0	0
T55	7048	0	0	0
T200	84433	98	0	0
T208	1068	0	0	0
T209	1546	0	0	0
T223	0	59	0	0
T224	0	3	0	0
T235	0	33	0	0
T238	942	0	0	0
T239	15366	0	0	0
T240	11496	5	0	0
T242	0	86	0	0
T252	0	3	0	0
T278	0	263	0	0
T281	0	7	0	0
T282	1342	0	0	0

bank1_info0_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	1522	0	0
T53	21520	43	0	0
T54	5759	0	0	0
T55	7048	0	0	0
T200	84433	82	0	0
T208	1068	0	0	0
T209	1546	0	0	0
T223	0	24	0	0
T224	0	9	0	0
T235	0	55	0	0
T238	942	0	0	0
T239	15366	0	0	0
T240	11496	31	0	0
T242	0	79	0	0
T252	0	9	0	0
T278	0	210	0	0
T281	0	2	0	0
T282	1342	0	0	0

bank1_info0_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	1695	0	0
T53	21520	34	0	0
T54	5759	0	0	0
T55	7048	0	0	0
T200	84433	89	0	0
T208	1068	0	0	0
T209	1546	0	0	0
T223	0	27	0	0
T224	0	9	0	0
T235	0	52	0	0
T238	942	0	0	0
T239	15366	0	0	0
T240	11496	20	0	0
T242	0	86	0	0
T252	0	3	0	0
T278	0	248	0	0
T281	0	1	0	0
T282	1342	0	0	0

bank1_info0_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	1334	0	0
T53	21520	48	0	0
T54	5759	0	0	0
T55	7048	0	0	0
T200	84433	64	0	0
T208	1068	0	0	0
T209	1546	0	0	0
T223	0	47	0	0
T224	0	2	0	0
T235	0	39	0	0
T238	942	0	0	0
T239	15366	0	0	0
T240	11496	25	0	0
T242	0	83	0	0
T243	0	30	0	0
T252	0	2	0	0
T281	0	5	0	0
T282	1342	0	0	0

bank1_info0_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	1648	0	0
T53	21520	45	0	0
T54	5759	0	0	0
T55	7048	0	0	0
T200	84433	98	0	0
T208	1068	0	0	0
T209	1546	0	0	0
T223	0	72	0	0
T224	0	5	0	0
T235	0	41	0	0
T238	942	0	0	0
T239	15366	0	0	0
T240	11496	10	0	0
T242	0	89	0	0
T243	0	42	0	0
T252	0	5	0	0
T278	0	227	0	0
T282	1342	0	0	0

bank1_info0_regwen_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	1629	0	0
T53	21520	56	0	0
T54	5759	0	0	0
T55	7048	0	0	0
T200	84433	74	0	0
T208	1068	0	0	0
T209	1546	0	0	0
T223	0	43	0	0
T224	0	12	0	0
T235	0	38	0	0
T238	942	0	0	0
T239	15366	0	0	0
T240	11496	4	0	0
T242	0	68	0	0
T252	0	6	0	0
T278	0	266	0	0
T281	0	6	0	0
T282	1342	0	0	0

bank1_info0_regwen_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	1079	0	0
T53	21520	30	0	0
T54	5759	0	0	0
T55	7048	0	0	0
T200	84433	78	0	0
T208	1068	0	0	0
T209	1546	0	0	0
T223	0	39	0	0
T224	0	14	0	0
T235	0	32	0	0
T238	942	0	0	0
T239	15366	0	0	0
T240	11496	12	0	0
T242	0	66	0	0
T243	0	46	0	0
T278	0	244	0	0
T281	0	1	0	0
T282	1342	0	0	0

bank1_info1_page_cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	2022	0	0
T53	21520	81	0	0
T54	5759	0	0	0
T55	7048	0	0	0
T200	84433	316	0	0
T208	1068	0	0	0
T209	1546	0	0	0
T223	0	135	0	0
T224	0	10	0	0
T235	0	204	0	0
T238	942	0	0	0
T239	15366	0	0	0
T240	11496	3	0	0
T242	0	259	0	0
T243	0	165	0	0
T252	0	21	0	0
T278	0	257	0	0
T282	1342	0	0	0

bank1_info1_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	1429	0	0
T53	21520	69	0	0
T54	5759	0	0	0
T55	7048	0	0	0
T200	84433	65	0	0
T208	1068	0	0	0
T209	1546	0	0	0
T223	0	55	0	0
T224	0	2	0	0
T235	0	37	0	0
T238	942	0	0	0
T239	15366	0	0	0
T240	11496	23	0	0
T242	0	90	0	0
T243	0	55	0	0
T281	0	3	0	0
T282	1342	0	0	0
T283	0	988	0	0

bank1_info2_page_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	2676	0	0
T53	21520	38	0	0
T54	5759	0	0	0
T55	7048	0	0	0
T200	84433	330	0	0
T208	1068	0	0	0
T209	1546	0	0	0
T223	0	164	0	0
T224	0	15	0	0
T235	0	246	0	0
T238	942	0	0	0
T239	15366	0	0	0
T240	11496	28	0	0
T242	0	362	0	0
T252	0	5	0	0
T278	0	239	0	0
T281	0	12	0	0
T282	1342	0	0	0

bank1_info2_page_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	2268	0	0
T53	21520	35	0	0
T54	5759	0	0	0
T55	7048	0	0	0
T200	84433	303	0	0
T208	1068	0	0	0
T209	1546	0	0	0
T223	0	201	0	0
T224	0	3	0	0
T235	0	148	0	0
T238	942	0	0	0
T239	15366	0	0	0
T240	11496	26	0	0
T242	0	364	0	0
T243	0	158	0	0
T252	0	28	0	0
T281	0	3	0	0
T282	1342	0	0	0

bank1_info2_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	1721	0	0
T53	21520	61	0	0
T54	5759	0	0	0
T55	7048	0	0	0
T200	84433	80	0	0
T208	1068	0	0	0
T209	1546	0	0	0
T223	0	45	0	0
T224	0	8	0	0
T235	0	52	0	0
T238	942	0	0	0
T239	15366	0	0	0
T240	11496	29	0	0
T242	0	77	0	0
T243	0	33	0	0
T252	0	6	0	0
T278	0	237	0	0
T282	1342	0	0	0

bank1_info2_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	1581	0	0
T53	21520	40	0	0
T54	5759	0	0	0
T55	7048	0	0	0
T200	84433	62	0	0
T208	1068	0	0	0
T209	1546	0	0	0
T223	0	28	0	0
T224	0	5	0	0
T235	0	43	0	0
T238	942	0	0	0
T239	15366	0	0	0
T240	11496	26	0	0
T242	0	73	0	0
T243	0	29	0	0
T252	0	9	0	0
T278	0	255	0	0
T282	1342	0	0	0

bank_cfg_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	1322	0	0
T53	21520	82	0	0
T54	5759	0	0	0
T55	7048	0	0	0
T200	84433	73	0	0
T208	1068	0	0	0
T209	1546	0	0	0
T223	0	37	0	0
T224	0	5	0	0
T235	0	40	0	0
T238	942	0	0	0
T239	15366	0	0	0
T240	11496	36	0	0
T242	0	71	0	0
T243	0	44	0	0
T252	0	4	0	0
T282	1342	0	0	0
T283	0	900	0	0

default_region_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	2100	0	0
T53	21520	23	0	0
T54	5759	0	0	0
T55	7048	0	0	0
T200	84433	249	0	0
T208	1068	0	0	0
T209	1546	0	0	0
T223	0	181	0	0
T224	0	13	0	0
T235	0	129	0	0
T238	942	0	0	0
T239	15366	0	0	0
T240	11496	17	0	0
T242	0	281	0	0
T243	0	135	0	0
T252	0	2	0	0
T281	0	27	0	0
T282	1342	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	1152	0	0
T53	21520	13	0	0
T54	5759	0	0	0
T55	7048	0	0	0
T200	84433	82	0	0
T208	1068	0	0	0
T209	1546	0	0	0
T223	0	18	0	0
T224	0	13	0	0
T235	0	49	0	0
T238	942	0	0	0
T239	15366	0	0	0
T240	11496	22	0	0
T242	0	102	0	0
T252	0	1	0	0
T278	0	254	0	0
T281	0	6	0	0
T282	1342	0	0	0

fifo_lvl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	762	0	0
T53	21520	51	0	0
T54	5759	0	0	0
T55	7048	0	0	0
T200	84433	98	0	0
T208	1068	0	0	0
T209	1546	0	0	0
T223	0	74	0	0
T224	0	7	0	0
T235	0	66	0	0
T238	942	0	0	0
T239	15366	0	0	0
T240	11496	5	0	0
T242	0	123	0	0
T252	0	9	0	0
T278	0	226	0	0
T281	0	1	0	0
T282	1342	0	0	0

fifo_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	1360	0	0
T53	21520	45	0	0
T54	5759	0	0	0
T55	7048	0	0	0
T200	84433	53	0	0
T208	1068	0	0	0
T209	1546	0	0	0
T223	0	43	0	0
T224	0	11	0	0
T235	0	16	0	0
T238	942	0	0	0
T239	15366	0	0	0
T240	11496	14	0	0
T242	0	81	0	0
T243	0	66	0	0
T252	0	1	0	0
T281	0	2	0	0
T282	1342	0	0	0

hw_info_cfg_override_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	1762	0	0
T53	21520	51	0	0
T54	5759	0	0	0
T55	7048	0	0	0
T200	84433	122	0	0
T208	1068	0	0	0
T209	1546	0	0	0
T223	0	66	0	0
T224	0	8	0	0
T235	0	46	0	0
T238	942	0	0	0
T239	15366	0	0	0
T240	11496	29	0	0
T242	0	133	0	0
T243	0	78	0	0
T252	0	3	0	0
T278	0	257	0	0
T282	1342	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	1933	0	0
T53	21520	48	0	0
T54	5759	0	0	0
T55	7048	0	0	0
T200	84433	279	0	0
T208	1068	0	0	0
T209	1546	0	0	0
T223	0	180	0	0
T224	0	8	0	0
T235	0	176	0	0
T238	942	0	0	0
T239	15366	0	0	0
T240	11496	16	0	0
T242	0	255	0	0
T243	0	96	0	0
T252	0	5	0	0
T278	0	282	0	0
T282	1342	0	0	0

mp_region_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	1501	0	0
T53	21520	21	0	0
T54	5759	0	0	0
T55	7048	0	0	0
T200	84433	108	0	0
T208	1068	0	0	0
T209	1546	0	0	0
T223	0	81	0	0
T224	0	5	0	0
T235	0	56	0	0
T238	942	0	0	0
T239	15366	0	0	0
T240	11496	7	0	0
T242	0	112	0	0
T243	0	51	0	0
T252	0	2	0	0
T282	1342	0	0	0
T283	0	971	0	0

mp_region_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	1553	0	0
T53	21520	90	0	0
T54	5759	0	0	0
T55	7048	0	0	0
T200	84433	175	0	0
T208	1068	0	0	0
T209	1546	0	0	0
T223	0	51	0	0
T224	0	15	0	0
T235	0	56	0	0
T238	942	0	0	0
T239	15366	0	0	0
T240	11496	22	0	0
T242	0	117	0	0
T243	0	54	0	0
T252	0	3	0	0
T282	1342	0	0	0
T283	0	940	0	0

mp_region_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	1004	0	0
T53	21520	27	0	0
T54	5759	0	0	0
T55	7048	0	0	0
T200	84433	134	0	0
T208	1068	0	0	0
T209	1546	0	0	0
T223	0	31	0	0
T224	0	3	0	0
T235	0	67	0	0
T238	942	0	0	0
T239	15366	0	0	0
T240	11496	14	0	0
T242	0	117	0	0
T243	0	65	0	0
T282	1342	0	0	0
T283	0	512	0	0
T284	0	34	0	0

mp_region_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	1860	0	0
T53	21520	63	0	0
T54	5759	0	0	0
T55	7048	0	0	0
T200	84433	115	0	0
T208	1068	0	0	0
T209	1546	0	0	0
T223	0	51	0	0
T224	0	7	0	0
T235	0	72	0	0
T238	942	0	0	0
T239	15366	0	0	0
T240	11496	39	0	0
T242	0	103	0	0
T243	0	65	0	0
T252	0	7	0	0
T278	0	316	0	0
T282	1342	0	0	0

mp_region_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	1868	0	0
T53	21520	27	0	0
T54	5759	0	0	0
T55	7048	0	0	0
T200	84433	116	0	0
T208	1068	0	0	0
T209	1546	0	0	0
T223	0	93	0	0
T224	0	16	0	0
T235	0	40	0	0
T238	942	0	0	0
T239	15366	0	0	0
T240	11496	34	0	0
T242	0	128	0	0
T243	0	76	0	0
T252	0	1	0	0
T278	0	299	0	0
T282	1342	0	0	0

mp_region_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	1314	0	0
T53	21520	58	0	0
T54	5759	0	0	0
T55	7048	0	0	0
T200	84433	120	0	0
T208	1068	0	0	0
T209	1546	0	0	0
T223	0	51	0	0
T224	0	8	0	0
T235	0	63	0	0
T238	942	0	0	0
T239	15366	0	0	0
T240	11496	48	0	0
T242	0	102	0	0
T252	0	13	0	0
T278	0	229	0	0
T281	0	5	0	0
T282	1342	0	0	0

mp_region_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	1674	0	0
T53	21520	19	0	0
T54	5759	0	0	0
T55	7048	0	0	0
T200	84433	62	0	0
T208	1068	0	0	0
T209	1546	0	0	0
T223	0	74	0	0
T224	0	7	0	0
T235	0	48	0	0
T238	942	0	0	0
T239	15366	0	0	0
T240	11496	18	0	0
T242	0	99	0	0
T243	0	53	0	0
T278	0	300	0	0
T282	1342	0	0	0
T283	0	968	0	0

mp_region_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	1304	0	0
T53	21520	17	0	0
T54	5759	0	0	0
T55	7048	0	0	0
T200	84433	114	0	0
T208	1068	0	0	0
T209	1546	0	0	0
T223	0	65	0	0
T224	0	2	0	0
T235	0	68	0	0
T238	942	0	0	0
T239	15366	0	0	0
T240	11496	16	0	0
T242	0	156	0	0
T243	0	76	0	0
T252	0	9	0	0
T278	0	253	0	0
T282	1342	0	0	0

mp_region_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	1685	0	0
T53	21520	60	0	0
T54	5759	0	0	0
T55	7048	0	0	0
T200	84433	234	0	0
T208	1068	0	0	0
T209	1546	0	0	0
T223	0	192	0	0
T224	0	7	0	0
T235	0	182	0	0
T238	942	0	0	0
T239	15366	0	0	0
T240	11496	11	0	0
T242	0	303	0	0
T243	0	186	0	0
T252	0	22	0	0
T281	0	2	0	0
T282	1342	0	0	0

mp_region_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	2478	0	0
T53	21520	57	0	0
T54	5759	0	0	0
T55	7048	0	0	0
T200	84433	372	0	0
T208	1068	0	0	0
T209	1546	0	0	0
T223	0	99	0	0
T224	0	15	0	0
T235	0	248	0	0
T238	942	0	0	0
T239	15366	0	0	0
T240	11496	48	0	0
T242	0	219	0	0
T252	0	18	0	0
T278	0	258	0	0
T281	0	14	0	0
T282	1342	0	0	0

mp_region_cfg_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	2241	0	0
T53	21520	41	0	0
T54	5759	0	0	0
T55	7048	0	0	0
T200	84433	397	0	0
T208	1068	0	0	0
T209	1546	0	0	0
T223	0	198	0	0
T224	0	6	0	0
T235	0	137	0	0
T238	942	0	0	0
T239	15366	0	0	0
T240	11496	37	0	0
T242	0	298	0	0
T243	0	155	0	0
T252	0	4	0	0
T281	0	14	0	0
T282	1342	0	0	0

mp_region_cfg_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	2041	0	0
T53	21520	26	0	0
T54	5759	0	0	0
T55	7048	0	0	0
T200	84433	315	0	0
T208	1068	0	0	0
T209	1546	0	0	0
T223	0	179	0	0
T224	0	12	0	0
T235	0	202	0	0
T238	942	0	0	0
T239	15366	0	0	0
T240	11496	14	0	0
T242	0	288	0	0
T252	0	3	0	0
T278	0	254	0	0
T281	0	17	0	0
T282	1342	0	0	0

mp_region_cfg_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	2296	0	0
T53	21520	51	0	0
T54	5759	0	0	0
T55	7048	0	0	0
T200	84433	274	0	0
T208	1068	0	0	0
T209	1546	0	0	0
T223	0	179	0	0
T224	0	12	0	0
T235	0	103	0	0
T238	942	0	0	0
T239	15366	0	0	0
T240	11496	15	0	0
T242	0	250	0	0
T243	0	163	0	0
T252	0	8	0	0
T278	0	268	0	0
T282	1342	0	0	0

mp_region_cfg_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	2303	0	0
T53	21520	24	0	0
T54	5759	0	0	0
T55	7048	0	0	0
T200	84433	282	0	0
T208	1068	0	0	0
T209	1546	0	0	0
T223	0	160	0	0
T224	0	8	0	0
T235	0	141	0	0
T238	942	0	0	0
T239	15366	0	0	0
T240	11496	34	0	0
T242	0	309	0	0
T243	0	126	0	0
T252	0	27	0	0
T278	0	263	0	0
T282	1342	0	0	0

mp_region_cfg_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	2589	0	0
T53	21520	55	0	0
T54	5759	0	0	0
T55	7048	0	0	0
T200	84433	380	0	0
T208	1068	0	0	0
T209	1546	0	0	0
T223	0	187	0	0
T224	0	8	0	0
T235	0	172	0	0
T238	942	0	0	0
T239	15366	0	0	0
T240	11496	30	0	0
T242	0	251	0	0
T252	0	36	0	0
T278	0	316	0	0
T281	0	21	0	0
T282	1342	0	0	0

mp_region_cfg_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	2050	0	0
T53	21520	44	0	0
T54	5759	0	0	0
T55	7048	0	0	0
T200	84433	326	0	0
T208	1068	0	0	0
T209	1546	0	0	0
T223	0	121	0	0
T224	0	15	0	0
T235	0	215	0	0
T238	942	0	0	0
T239	15366	0	0	0
T240	11496	24	0	0
T242	0	288	0	0
T252	0	7	0	0
T278	0	280	0	0
T281	0	10	0	0
T282	1342	0	0	0

phy_alert_cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	1275	0	0
T53	21520	34	0	0
T54	5759	0	0	0
T55	7048	0	0	0
T200	84433	0	0	0
T208	1068	0	0	0
T209	1546	0	0	0
T224	0	8	0	0
T238	942	0	0	0
T239	15366	0	0	0
T240	11496	0	0	0
T278	0	240	0	0
T282	1342	0	0	0
T283	0	960	0	0
T284	0	33	0	0

region_cfg_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	1671	0	0
T53	21520	55	0	0
T54	5759	0	0	0
T55	7048	0	0	0
T200	84433	78	0	0
T208	1068	0	0	0
T209	1546	0	0	0
T223	0	40	0	0
T224	0	4	0	0
T235	0	34	0	0
T238	942	0	0	0
T239	15366	0	0	0
T240	11496	4	0	0
T242	0	80	0	0
T252	0	8	0	0
T278	0	208	0	0
T281	0	3	0	0
T282	1342	0	0	0

region_cfg_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	1503	0	0
T53	21520	47	0	0
T54	5759	0	0	0
T55	7048	0	0	0
T200	84433	79	0	0
T208	1068	0	0	0
T209	1546	0	0	0
T223	0	48	0	0
T224	0	7	0	0
T235	0	13	0	0
T238	942	0	0	0
T239	15366	0	0	0
T240	11496	6	0	0
T242	0	88	0	0
T243	0	32	0	0
T252	0	5	0	0
T278	0	275	0	0
T282	1342	0	0	0

region_cfg_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	1662	0	0
T53	21520	23	0	0
T54	5759	0	0	0
T55	7048	0	0	0
T200	84433	74	0	0
T208	1068	0	0	0
T209	1546	0	0	0
T223	0	40	0	0
T224	0	10	0	0
T235	0	73	0	0
T238	942	0	0	0
T239	15366	0	0	0
T240	11496	7	0	0
T242	0	72	0	0
T243	0	24	0	0
T278	0	268	0	0
T281	0	6	0	0
T282	1342	0	0	0

region_cfg_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	1703	0	0
T53	21520	25	0	0
T54	5759	0	0	0
T55	7048	0	0	0
T200	84433	97	0	0
T208	1068	0	0	0
T209	1546	0	0	0
T223	0	35	0	0
T224	0	8	0	0
T235	0	46	0	0
T238	942	0	0	0
T239	15366	0	0	0
T240	11496	41	0	0
T242	0	63	0	0
T252	0	4	0	0
T278	0	247	0	0
T281	0	5	0	0
T282	1342	0	0	0

region_cfg_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	1579	0	0
T53	21520	62	0	0
T54	5759	0	0	0
T55	7048	0	0	0
T200	84433	68	0	0
T208	1068	0	0	0
T209	1546	0	0	0
T223	0	60	0	0
T224	0	8	0	0
T235	0	39	0	0
T238	942	0	0	0
T239	15366	0	0	0
T240	11496	5	0	0
T242	0	82	0	0
T243	0	28	0	0
T278	0	232	0	0
T282	1342	0	0	0
T283	0	964	0	0

region_cfg_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	1684	0	0
T53	21520	43	0	0
T54	5759	0	0	0
T55	7048	0	0	0
T200	84433	90	0	0
T208	1068	0	0	0
T209	1546	0	0	0
T223	0	39	0	0
T224	0	11	0	0
T235	0	28	0	0
T238	942	0	0	0
T239	15366	0	0	0
T240	11496	13	0	0
T242	0	93	0	0
T243	0	50	0	0
T278	0	272	0	0
T281	0	1	0	0
T282	1342	0	0	0

region_cfg_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	1056	0	0
T53	21520	30	0	0
T54	5759	0	0	0
T55	7048	0	0	0
T200	84433	80	0	0
T208	1068	0	0	0
T209	1546	0	0	0
T223	0	36	0	0
T224	0	1	0	0
T235	0	69	0	0
T238	942	0	0	0
T239	15366	0	0	0
T240	11496	7	0	0
T242	0	61	0	0
T243	0	41	0	0
T252	0	1	0	0
T278	0	264	0	0
T282	1342	0	0	0

region_cfg_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	1558	0	0
T53	21520	5	0	0
T54	5759	0	0	0
T55	7048	0	0	0
T200	84433	82	0	0
T208	1068	0	0	0
T209	1546	0	0	0
T223	0	52	0	0
T224	0	13	0	0
T235	0	25	0	0
T238	942	0	0	0
T239	15366	0	0	0
T240	11496	0	0	0
T242	0	65	0	0
T243	0	42	0	0
T252	0	5	0	0
T278	0	288	0	0
T281	0	2	0	0
T282	1342	0	0	0

scratch_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311579167	1582	0	0
T53	21520	32	0	0
T54	5759	0	0	0
T55	7048	0	0	0
T200	84433	89	0	0
T208	1068	0	0	0
T209	1546	0	0	0
T223	0	54	0	0
T224	0	3	0	0
T235	0	18	0	0
T238	942	0	0	0
T239	15366	0	0	0
T240	11496	31	0	0
T242	0	96	0	0
T252	0	3	0	0
T278	0	239	0	0
T281	0	6	0	0
T282	1342	0	0	0