Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	20339396	1		T1	444		T2	128419		T3	290
full_word	6954035	1		T1	213		T2	24531		T3	249

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	27293121	1		T1	657		T2	152950		T3	539
auto[TlIntgErrCmd]	106	1		T172	6		T216	5		T321	3
auto[TlIntgErrData]	100	1		T170	6		T172	5		T216	7
auto[TlIntgErrBoth]	104	1		T170	4		T172	9		T216	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	23316489	1		T1	555		T2	134802		T3	433
auto[1]	3976942	1		T1	102		T2	18148		T3	106

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	19724098	1		T1	413		T2	127171		T3	274
auto[TlIntgErrNone]	partial	auto[1]	615015	1		T1	31		T2	1248		T3	16
auto[TlIntgErrNone]	full_word	auto[0]	3592254	1		T1	142		T2	7631		T3	159
auto[TlIntgErrNone]	full_word	auto[1]	3361754	1		T1	71		T2	16900		T3	90
auto[TlIntgErrCmd]	partial	auto[0]	45	1		T172	2		T321	2		T267	3
auto[TlIntgErrCmd]	partial	auto[1]	54	1		T172	3		T216	5		T321	1
auto[TlIntgErrCmd]	full_word	auto[0]	3	1		T327	1		T325	1		T320	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1		T172	1		T267	1		T270	1
auto[TlIntgErrData]	partial	auto[0]	44	1		T170	2		T267	3		T322	3
auto[TlIntgErrData]	partial	auto[1]	48	1		T170	4		T172	5		T216	5
auto[TlIntgErrData]	full_word	auto[0]	3	1		T216	1		T270	1		T327	1
auto[TlIntgErrData]	full_word	auto[1]	5	1		T216	1		T270	1		T328	1
auto[TlIntgErrBoth]	partial	auto[0]	37	1		T172	3		T216	2		T321	1
auto[TlIntgErrBoth]	partial	auto[1]	55	1		T170	3		T172	6		T216	4
auto[TlIntgErrBoth]	full_word	auto[0]	5	1		T267	1		T271	1		T329	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1		T170	1		T216	2		T323	1

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	32720	1		T169	702		T170	8		T171	590
full_word	4079905	1		T1	7		T5	15909		T19	354

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4112332	1		T1	7		T5	15909		T19	354
auto[TlIntgErrCmd]	94	1		T170	4		T172	4		T216	7
auto[TlIntgErrData]	105	1		T170	3		T172	7		T216	10
auto[TlIntgErrBoth]	94	1		T170	1		T172	8		T216	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	4072260	1		T1	7		T5	15909		T19	354
auto[1]	40365	1		T169	807		T170	6		T171	658

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	2074	1		T169	15		T171	51		T195	43
auto[TlIntgErrNone]	partial	auto[1]	30372	1		T169	687		T171	539		T195	566
auto[TlIntgErrNone]	full_word	auto[0]	4070079	1		T1	7		T5	15909		T19	354
auto[TlIntgErrNone]	full_word	auto[1]	9807	1		T169	120		T171	119		T195	285
auto[TlIntgErrCmd]	partial	auto[0]	27	1		T170	2		T172	1		T216	6
auto[TlIntgErrCmd]	partial	auto[1]	60	1		T170	2		T172	3		T216	1
auto[TlIntgErrCmd]	full_word	auto[0]	3	1		T322	1		T328	1		T326	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1		T267	1		T270	1		T324	2
auto[TlIntgErrData]	partial	auto[0]	43	1		T172	2		T216	4		T321	1
auto[TlIntgErrData]	partial	auto[1]	56	1		T170	3		T172	5		T216	5
auto[TlIntgErrData]	full_word	auto[0]	3	1		T216	1		T322	1		T330	1
auto[TlIntgErrData]	full_word	auto[1]	3	1		T329	1		T331	1		T328	1
auto[TlIntgErrBoth]	partial	auto[0]	29	1		T172	4		T321	1		T267	3
auto[TlIntgErrBoth]	partial	auto[1]	59	1		T170	1		T172	3		T216	3
auto[TlIntgErrBoth]	full_word	auto[0]	2	1		T172	1		T332	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1		T270	2		T323	1		T330	1