Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.u_to_prog_fifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
78.54 93.44 65.77 69.23 85.71


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
73.52 82.67 63.51 66.67 81.25


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.22 97.14 92.20 98.44 100.00 98.33 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_err 67.62 76.92 68.57 25.00 100.00
u_reqfifo 87.85 95.00 73.08 83.33 100.00
u_rsp_gen 91.67 83.33 100.00
u_rspfifo 68.01 91.43 51.85 68.75 60.00
u_sram_byte 100.00 100.00
u_sramreqfifo 64.11 86.11 47.83 62.50 60.00
u_tlul_data_integ_enc_data 0.00 0.00
u_tlul_data_integ_enc_instr 0.00 0.00



Module Instance : tb.dut.u_to_rd_fifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.49 95.38 77.39 85.19 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
88.53 85.78 76.15 100.00 80.72 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.22 97.14 92.20 98.44 100.00 98.33 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_err 66.91 76.92 65.71 25.00 100.00
u_reqfifo 87.85 95.00 73.08 83.33 100.00
u_rsp_gen 91.67 83.33 100.00
u_rspfifo 97.84 100.00 89.19 100.00 100.00 100.00
u_sram_byte 100.00 100.00
u_sramreqfifo 86.89 95.00 69.23 83.33 100.00
u_tlul_data_integ_enc_data 0.00 0.00
u_tlul_data_integ_enc_instr 0.00 0.00



Module Instance : tb.dut.u_tl_adapter_eflash

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.53 98.46 87.07 92.59 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.95 90.00 83.54 100.00 91.21 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.22 97.14 92.20 98.44 100.00 98.33 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_cmd_intg_check.u_cmd_intg_chk 100.00 100.00 100.00 100.00
u_err 69.05 76.92 74.29 25.00 100.00
u_reqfifo 95.19 100.00 80.77 100.00 100.00
u_rsp_gen 100.00 100.00 100.00
u_rspfifo 96.32 100.00 85.29 100.00 100.00
u_sram_byte 100.00 100.00
u_sramreqfifo 95.19 100.00 80.77 100.00 100.00
u_tlul_data_integ_enc_data 0.00 0.00
u_tlul_data_integ_enc_instr 0.00 0.00

Line Coverage for Module : tlul_adapter_sram ( parameter SramAw=1,SramDw=32,Outstanding=1,ByteAccess=0,ErrOnWrite=0,ErrOnRead=1,CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,EnableDataIntgPt=1,SecFifoPtr=0,WidthMult=1,DataOutW=39,DataBitWidth=2,WoffsetWidth=1,DataWidth=39 )
Line Coverage for Module self-instances :
SCORELINE
78.54 93.44
tb.dut.u_to_prog_fifo

Line No.TotalCoveredPercent
TOTAL615793.44
ALWAYS9333100.00
CONT_ASSIGN10211100.00
CONT_ASSIGN10711100.00
CONT_ASSIGN11411100.00
CONT_ASSIGN12511100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN22211100.00
CONT_ASSIGN22311100.00
CONT_ASSIGN22411100.00
ALWAYS2298675.00
ALWAYS2496583.33
CONT_ASSIGN26311100.00
CONT_ASSIGN26711100.00
CONT_ASSIGN28611100.00
CONT_ASSIGN29111100.00
CONT_ASSIGN29711100.00
CONT_ASSIGN30111100.00
CONT_ASSIGN32111100.00
CONT_ASSIGN32211100.00
CONT_ASSIGN32311100.00
CONT_ASSIGN32411100.00
ALWAYS35466100.00
ALWAYS36655100.00
CONT_ASSIGN37711100.00
CONT_ASSIGN37811100.00
CONT_ASSIGN38711100.00
CONT_ASSIGN38811100.00
CONT_ASSIGN39011100.00
CONT_ASSIGN39111100.00
CONT_ASSIGN39811100.00
CONT_ASSIGN40111100.00
CONT_ASSIGN40511100.00
CONT_ASSIGN40600
CONT_ASSIGN40800
CONT_ASSIGN41500
ALWAYS4213266.67
CONT_ASSIGN44211100.00
CONT_ASSIGN44711100.00
CONT_ASSIGN45200
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
93 1 1
94 1 1
95 1 1
96 unreachable
MISSING_ELSE
102 1 1
107 1 1
114 1 1
125 1 1
139 1 1
151 1 1
222 1 1
223 1 1
224 1 1
229 1 1
231 1 1
232 1 1
234 0 1
235 1 1
236 0 1
239 1 1
242 1 1
249 1 1
251 1 1
252 1 1
253 0 1
255 1 1
258 1 1
263 1 1
267 1 1
286 1 1
291 1 1
297 1 1
301 1 1
321 1 1
322 1 1
323 1 1
324 1 1
354 1 1
355 1 1
357 1 1
358 1 1
359 1 1
360 1 1
MISSING_ELSE
366 1 1
367 1 1
369 1 1
370 1 1
371 1 1
MISSING_ELSE
377 1 1
378 1 1
387 1 1
388 1 1
390 1 1
391 1 1
398 1 1
401 1 1
405 1 1
406 unreachable
408 unreachable
415 unreachable
421 1 1
425 1 1
427 0 1
MISSING_ELSE
442 1 1
447 1 1
452 unreachable


Line Coverage for Module : tlul_adapter_sram ( parameter SramAw=1,SramDw=32,Outstanding=1,ByteAccess=0,ErrOnWrite=1,ErrOnRead=0,CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,EnableDataIntgPt=1,SecFifoPtr=1,WidthMult=1,DataOutW=39,DataBitWidth=2,WoffsetWidth=1,DataWidth=39 )
Line Coverage for Module self-instances :
SCORELINE
89.49 95.38
tb.dut.u_to_rd_fifo

Line No.TotalCoveredPercent
TOTAL656295.38
ALWAYS9344100.00
CONT_ASSIGN10211100.00
CONT_ASSIGN10711100.00
CONT_ASSIGN11411100.00
CONT_ASSIGN11911100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN22211100.00
CONT_ASSIGN22311100.00
CONT_ASSIGN22411100.00
ALWAYS2298675.00
ALWAYS2496583.33
CONT_ASSIGN26311100.00
CONT_ASSIGN26711100.00
CONT_ASSIGN28611100.00
CONT_ASSIGN29111100.00
CONT_ASSIGN29711100.00
CONT_ASSIGN30111100.00
CONT_ASSIGN32111100.00
CONT_ASSIGN32211100.00
CONT_ASSIGN32311100.00
CONT_ASSIGN32411100.00
ALWAYS35466100.00
ALWAYS36655100.00
CONT_ASSIGN37711100.00
CONT_ASSIGN37811100.00
CONT_ASSIGN38711100.00
CONT_ASSIGN38811100.00
CONT_ASSIGN39011100.00
CONT_ASSIGN39111100.00
CONT_ASSIGN39811100.00
CONT_ASSIGN40111100.00
CONT_ASSIGN40511100.00
CONT_ASSIGN40611100.00
CONT_ASSIGN40811100.00
CONT_ASSIGN41511100.00
ALWAYS42133100.00
CONT_ASSIGN44211100.00
CONT_ASSIGN44711100.00
CONT_ASSIGN45200
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
93 1 1
94 1 1
95 1 1
96 1 1
MISSING_ELSE
102 1 1
107 1 1
114 1 1
119 1 1
139 1 1
151 1 1
222 1 1
223 1 1
224 1 1
229 1 1
231 1 1
232 1 1
234 0 1
235 1 1
236 1 1
239 0 1
242 1 1
249 1 1
251 1 1
252 1 1
253 1 1
255 0 1
258 1 1
263 1 1
267 1 1
286 1 1
291 1 1
297 1 1
301 1 1
321 1 1
322 1 1
323 1 1
324 1 1
354 1 1
355 1 1
357 1 1
358 1 1
359 1 1
360 1 1
MISSING_ELSE
366 1 1
367 1 1
369 1 1
370 1 1
371 1 1
MISSING_ELSE
377 1 1
378 1 1
387 1 1
388 1 1
390 1 1
391 1 1
398 1 1
401 1 1
405 1 1
406 1 1
408 1 1
415 1 1
421 1 1
425 1 1
427 1 1
MISSING_ELSE
442 1 1
447 1 1
452 unreachable


Line Coverage for Module : tlul_adapter_sram ( parameter SramAw=18,SramDw=32,Outstanding=2,ByteAccess=0,ErrOnWrite=1,ErrOnRead=0,CmdIntgCheck=1,EnableRspIntgGen=1,EnableDataIntgGen=0,EnableDataIntgPt=1,SecFifoPtr=0,WidthMult=1,DataOutW=39,DataBitWidth=2,WoffsetWidth=1,DataWidth=39 )
Line Coverage for Module self-instances :
SCORELINE
94.53 98.46
tb.dut.u_tl_adapter_eflash

Line No.TotalCoveredPercent
TOTAL656498.46
ALWAYS9344100.00
CONT_ASSIGN10211100.00
CONT_ASSIGN10711100.00
CONT_ASSIGN11411100.00
CONT_ASSIGN11911100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN22211100.00
CONT_ASSIGN22311100.00
CONT_ASSIGN22411100.00
ALWAYS2298787.50
ALWAYS24966100.00
CONT_ASSIGN26311100.00
CONT_ASSIGN26711100.00
CONT_ASSIGN28611100.00
CONT_ASSIGN29111100.00
CONT_ASSIGN29711100.00
CONT_ASSIGN30111100.00
CONT_ASSIGN32111100.00
CONT_ASSIGN32211100.00
CONT_ASSIGN32311100.00
CONT_ASSIGN32411100.00
ALWAYS35466100.00
ALWAYS36655100.00
CONT_ASSIGN37711100.00
CONT_ASSIGN37811100.00
CONT_ASSIGN38711100.00
CONT_ASSIGN38811100.00
CONT_ASSIGN39011100.00
CONT_ASSIGN39111100.00
CONT_ASSIGN39811100.00
CONT_ASSIGN40111100.00
CONT_ASSIGN40511100.00
CONT_ASSIGN40611100.00
CONT_ASSIGN40811100.00
CONT_ASSIGN41511100.00
ALWAYS42133100.00
CONT_ASSIGN44211100.00
CONT_ASSIGN44711100.00
CONT_ASSIGN45200
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
93 1 1
94 1 1
95 1 1
96 1 1
MISSING_ELSE
102 1 1
107 1 1
114 1 1
119 1 1
139 1 1
151 1 1
222 1 1
223 1 1
224 1 1
229 1 1
231 1 1
232 1 1
234 1 1
235 1 1
236 1 1
239 0 1
242 1 1
249 1 1
251 1 1
252 1 1
253 1 1
255 1 1
258 1 1
263 1 1
267 1 1
286 1 1
291 1 1
297 1 1
301 1 1
321 1 1
322 1 1
323 1 1
324 1 1
354 1 1
355 1 1
357 1 1
358 1 1
359 1 1
360 1 1
MISSING_ELSE
366 1 1
367 1 1
369 1 1
370 1 1
371 1 1
MISSING_ELSE
377 1 1
378 1 1
387 1 1
388 1 1
390 1 1
391 1 1
398 1 1
401 1 1
405 1 1
406 1 1
408 1 1
415 1 1
421 1 1
425 1 1
427 1 1
MISSING_ELSE
442 1 1
447 1 1
452 unreachable


Cond Coverage for Module : tlul_adapter_sram ( parameter SramAw=1,SramDw=32,Outstanding=1,ByteAccess=0,ErrOnWrite=0,ErrOnRead=1,CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,EnableDataIntgPt=1,SecFifoPtr=0,WidthMult=1,DataOutW=39,DataBitWidth=2,WoffsetWidth=1,DataWidth=39 )
Cond Coverage for Module self-instances :
SCORECOND
78.54 65.77
tb.dut.u_to_prog_fifo

TotalCoveredPercent
Conditions1117365.77
Logical1117365.77
Non-Logical00
Event00

 LINE       95
 EXPRESSION (intg_error || rsp_fifo_error)
             -----1----    -------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10Unreachable

 LINE       102
 EXPRESSION (intg_error | rsp_fifo_error | intg_error_q)
             -----1----   -------2------   ------3-----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001Not Covered
010Unreachable
100Unreachable

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T6,T22
10CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       125
 EXPRESSION (tl_i.a_opcode == Get)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       139
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----
-1--2--3--4--5--6-StatusTests
000000CoveredT1,T2,T4
000001Unreachable
000010CoveredT1,T2,T3
000100Not Covered
001000Not Covered
010000Unreachable
100000Not Covered

 LINE       222
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T4
11CoveredT1,T2,T4

 LINE       223
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T6,T22
11CoveredT1,T2,T4

 LINE       224
 EXPRESSION (req_o & gnt_i)
             --1--   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT9,T28,T29
11CoveredT1,T2,T4

 LINE       235
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T4
1Not Covered

 LINE       252
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T4
1Not Covered

 LINE       253
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered

 LINE       263
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101Not Covered
1110Not Covered
1111Not Covered

 LINE       263
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       291
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       291
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       297
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       297
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       297
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       301
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T4

 LINE       301
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T4

 LINE       301
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       301
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T4

 LINE       301
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T4

 LINE       301
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T4
11Not Covered

 LINE       301
 EXPRESSION ((gnt_i | error_internal) & reqfifo_wready & sramreqfifo_wready)
             ------------1-----------   -------2------   ---------3--------
-1--2--3-StatusTests
011CoveredT9,T28,T29
101CoveredT1,T2,T4
110Not Covered
111CoveredT1,T2,T3

 LINE       301
 SUB-EXPRESSION (gnt_i | error_internal)
                 --1--   -------2------
-1--2-StatusTests
00CoveredT2,T4,T9
01CoveredT1,T2,T3
10CoveredT1,T2,T4

 LINE       321
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T4
110Not Covered
111CoveredT1,T2,T4

 LINE       323
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T4

 LINE       324
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T4

 LINE       360
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T4

 LINE       360
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-
-1--2-StatusTests
01Not Covered
10Not Covered
11CoveredT1,T2,T4

 LINE       391
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       391
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       405
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T4
11Not Covered

 LINE       408
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT1,T2,T4
10Unreachable
11Unreachable

 LINE       447
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       447
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       447
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

Cond Coverage for Module : tlul_adapter_sram ( parameter SramAw=1,SramDw=32,Outstanding=1,ByteAccess=0,ErrOnWrite=1,ErrOnRead=0,CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,EnableDataIntgPt=1,SecFifoPtr=1,WidthMult=1,DataOutW=39,DataBitWidth=2,WoffsetWidth=1,DataWidth=39 )
Cond Coverage for Module self-instances :
SCORECOND
89.49 77.39
tb.dut.u_to_rd_fifo

TotalCoveredPercent
Conditions1158977.39
Logical1158977.39
Non-Logical00
Event00

 LINE       95
 EXPRESSION (intg_error || rsp_fifo_error)
             -----1----    -------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT15,T16,T17
10Unreachable

 LINE       102
 EXPRESSION (intg_error | rsp_fifo_error | intg_error_q)
             -----1----   -------2------   ------3-----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT15,T16,T17
010CoveredT15,T16,T17
100Unreachable

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T6,T22
10CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       119
 EXPRESSION (tl_i.a_opcode != Get)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       139
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----
-1--2--3--4--5--6-StatusTests
000000CoveredT1,T2,T3
000001Unreachable
000010CoveredT1,T2,T3
000100Not Covered
001000Unreachable
010000Not Covered
100000Not Covered

 LINE       222
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       223
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T22,T30
11CoveredT1,T2,T3

 LINE       224
 EXPRESSION (req_o & gnt_i)
             --1--   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT5,T8,T22
11CoveredT1,T2,T3

 LINE       235
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       252
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       253
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT15,T31,T32

 LINE       263
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101Not Covered
1110Not Covered
1111CoveredT1,T2,T3

 LINE       263
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       291
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       291
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT15,T31,T32
11CoveredT1,T2,T3

 LINE       297
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       297
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11Not Covered

 LINE       297
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       301
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       301
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11Not Covered

 LINE       301
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       301
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       301
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       301
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT15,T31,T32

 LINE       301
 EXPRESSION ((gnt_i | error_internal) & reqfifo_wready & sramreqfifo_wready)
             ------------1-----------   -------2------   ---------3--------
-1--2--3-StatusTests
011CoveredT5,T8,T22
101CoveredT33,T34,T35
110Not Covered
111CoveredT1,T2,T3

 LINE       301
 SUB-EXPRESSION (gnt_i | error_internal)
                 --1--   -------2------
-1--2-StatusTests
00CoveredT5,T8,T22
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       321
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       323
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11Not Covered

 LINE       324
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       360
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       360
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11Not Covered

 LINE       391
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       391
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       405
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       408
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT33,T34,T35
10Not Covered
11CoveredT1,T2,T3

 LINE       447
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       447
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       447
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Cond Coverage for Module : tlul_adapter_sram ( parameter SramAw=18,SramDw=32,Outstanding=2,ByteAccess=0,ErrOnWrite=1,ErrOnRead=0,CmdIntgCheck=1,EnableRspIntgGen=1,EnableDataIntgGen=0,EnableDataIntgPt=1,SecFifoPtr=0,WidthMult=1,DataOutW=39,DataBitWidth=2,WoffsetWidth=1,DataWidth=39 )
Cond Coverage for Module self-instances :
SCORECOND
94.53 87.07
tb.dut.u_tl_adapter_eflash

TotalCoveredPercent
Conditions11610187.07
Logical11610187.07
Non-Logical00
Event00

 LINE       95
 EXPRESSION (intg_error || rsp_fifo_error)
             -----1----    -------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT36,T37,T38

 LINE       102
 EXPRESSION (intg_error | rsp_fifo_error | intg_error_q)
             -----1----   -------2------   ------3-----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT36,T37,T38
010Unreachable
100CoveredT36,T37,T38

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)
-1-StatusTests
0CoveredT1,T5,T19
1CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------
-1--2-StatusTests
00CoveredT1,T5,T19
01CoveredT3,T4,T5
10CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T5

 LINE       107
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------
-1--2-StatusTests
00CoveredT5,T20,T39
01CoveredT5,T33,T40
10CoveredT3,T4,T5

 LINE       107
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------
-1-StatusTests
0CoveredT5,T33,T40
1CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------
-1-StatusTests
0CoveredT3,T4,T5
1CoveredT1,T2,T3

 LINE       119
 EXPRESSION (tl_i.a_opcode != Get)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       139
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----
-1--2--3--4--5--6-StatusTests
000000CoveredT1,T5,T19
000001CoveredT37
000010CoveredT5,T33,T41
000100CoveredT42,T43,T44
001000Unreachable
010000Not Covered
100000Not Covered

 LINE       222
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT5,T7,T8
11CoveredT1,T5,T19

 LINE       223
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT5,T20,T21
11CoveredT1,T5,T19

 LINE       224
 EXPRESSION (req_o & gnt_i)
             --1--   --2--
-1--2-StatusTests
01Not Covered
10CoveredT5,T7,T8
11CoveredT1,T5,T19

 LINE       235
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0Not Covered
1CoveredT1,T5,T19

 LINE       252
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT38
1CoveredT1,T5,T19

 LINE       253
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------
-1--2-StatusTests
00CoveredT1,T5,T19
01CoveredT42,T43,T44
10CoveredT22,T45,T46

 LINE       263
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101CoveredT42,T43,T44
1110Not Covered
1111CoveredT1,T5,T19

 LINE       263
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T5,T19

 LINE       291
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T5,T19

 LINE       291
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT22,T45,T46
11CoveredT1,T5,T19

 LINE       297
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       297
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------
-1--2-StatusTests
01CoveredT42,T43,T44
10CoveredT1,T5,T19
11Not Covered

 LINE       297
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T5,T19

 LINE       301
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT38

 LINE       301
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T5,T19
11CoveredT38

 LINE       301
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       301
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T5,T19

 LINE       301
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T5,T19

 LINE       301
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T5,T19
11CoveredT22,T45,T46

 LINE       301
 EXPRESSION ((gnt_i | error_internal) & reqfifo_wready & sramreqfifo_wready)
             ------------1-----------   -------2------   ---------3--------
-1--2--3-StatusTests
011CoveredT5,T7,T8
101CoveredT42,T43,T44
110Not Covered
111CoveredT1,T2,T3

 LINE       301
 SUB-EXPRESSION (gnt_i | error_internal)
                 --1--   -------2------
-1--2-StatusTests
00CoveredT5,T7,T8
01CoveredT1,T2,T3
10CoveredT1,T5,T19

 LINE       321
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT5,T7,T8
110CoveredT42,T43,T44
111CoveredT1,T5,T19

 LINE       323
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T5,T19
11CoveredT38

 LINE       324
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T5,T19

 LINE       360
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------
-1-StatusTests
0CoveredT1,T5,T19
1CoveredT38

 LINE       360
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-
-1--2-StatusTests
01Not Covered
10CoveredT1,T5,T19
11CoveredT38

 LINE       391
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------
-1-StatusTests
0CoveredT1,T5,T19
1CoveredT1,T2,T3

 LINE       391
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       405
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T5,T19

 LINE       408
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT1,T5,T19
10Not Covered
11CoveredT1,T5,T19

 LINE       447
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T5,T19

 LINE       447
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT42,T43,T44
11CoveredT1,T5,T19

 LINE       447
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T5,T19

Branch Coverage for Module : tlul_adapter_sram
Line No.TotalCoveredPercent
Branches 27 26 96.30
TERNARY 107 2 2 100.00
TERNARY 291 2 2 100.00
TERNARY 297 3 2 66.67
TERNARY 324 2 2 100.00
TERNARY 447 2 2 100.00
IF 93 3 3 100.00
IF 231 4 4 100.00
IF 251 3 3 100.00
IF 357 2 2 100.00
IF 369 2 2 100.00
IF 425 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 107 (((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 291 ((vld_rd_rsp & (~d_error))) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 297 ((vld_rd_rsp && reqfifo_rdata.error)) ? -2-: 297 (vld_rd_rsp) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 324 (tl_i_int.a_valid) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 447 (((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 93 if ((!rst_ni)) -2-: 95 if ((intg_error || rsp_fifo_error))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T15,T16,T17
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 231 if (reqfifo_rvalid) -2-: 232 if (reqfifo_rdata.error) -3-: 235 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2--3-StatusTests
1 1 - Covered T42,T43,T44
1 0 1 Covered T1,T2,T3
1 0 0 Covered T1,T2,T4
0 - - Covered T1,T2,T3


LineNo. Expression -1-: 251 if (reqfifo_rvalid) -2-: 252 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2-StatusTests
1 1 Covered T1,T2,T3
1 0 Covered T1,T2,T4
0 - Covered T1,T2,T3


LineNo. Expression -1-: 357 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 369 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 425 if ((|sramreqfifo_rdata.mask))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : tlul_adapter_sram
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 14 14 100.00 14 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 14 14 100.00 14 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AddrOutKnown_A 1088966640 1086423144 0 0
DataIntgOptions_A 2973 2973 0 0
ReqOutKnown_A 1088966640 1086423144 0 0
SramDwHasByteGranularity_A 2973 2973 0 0
SramDwIsMultipleOfTlulWidth_A 2973 2973 0 0
TlOutKnown_A 1088966640 1086423144 0 0
TlOutPayloadKnown_A 1088966640 12708246 0 0
TlOutPayloadKnown_AKnownEnable 1088966640 1086423144 0 0
WdataOutKnown_A 1088966640 1086423144 0 0
WeOutKnown_A 1088966640 1086423144 0 0
WmaskOutKnown_A 1088966640 1086423144 0 0
adapterNoReadOrWrite 2973 2973 0 0
rvalidHighReqFifoEmpty 1088966640 7090372 0 0
rvalidHighWhenRspFifoFull 1088301564 7084375 0 0


AddrOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1088966640 1086423144 0 0
T1 9585 9138 0 0
T2 321744 321729 0 0
T3 7029 6867 0 0
T4 782157 781938 0 0
T5 144711 144459 0 0
T9 13887 12384 0 0
T12 10725 8910 0 0
T13 1180200 1180164 0 0
T18 3885 3678 0 0
T19 83544 83379 0 0

DataIntgOptions_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2973 2973 0 0
T1 3 3 0 0
T2 3 3 0 0
T3 3 3 0 0
T4 3 3 0 0
T5 3 3 0 0
T9 3 3 0 0
T12 3 3 0 0
T13 3 3 0 0
T18 3 3 0 0
T19 3 3 0 0

ReqOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1088966640 1086423144 0 0
T1 9585 9138 0 0
T2 321744 321729 0 0
T3 7029 6867 0 0
T4 782157 781938 0 0
T5 144711 144459 0 0
T9 13887 12384 0 0
T12 10725 8910 0 0
T13 1180200 1180164 0 0
T18 3885 3678 0 0
T19 83544 83379 0 0

SramDwHasByteGranularity_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2973 2973 0 0
T1 3 3 0 0
T2 3 3 0 0
T3 3 3 0 0
T4 3 3 0 0
T5 3 3 0 0
T9 3 3 0 0
T12 3 3 0 0
T13 3 3 0 0
T18 3 3 0 0
T19 3 3 0 0

SramDwIsMultipleOfTlulWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2973 2973 0 0
T1 3 3 0 0
T2 3 3 0 0
T3 3 3 0 0
T4 3 3 0 0
T5 3 3 0 0
T9 3 3 0 0
T12 3 3 0 0
T13 3 3 0 0
T18 3 3 0 0
T19 3 3 0 0

TlOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1088966640 1086423144 0 0
T1 9585 9138 0 0
T2 321744 321729 0 0
T3 7029 6867 0 0
T4 782157 781938 0 0
T5 144711 144459 0 0
T9 13887 12384 0 0
T12 10725 8910 0 0
T13 1180200 1180164 0 0
T18 3885 3678 0 0
T19 83544 83379 0 0

TlOutPayloadKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1088966640 12708246 0 0
T1 9585 144 0 0
T2 321744 17235 0 0
T3 7029 146 0 0
T4 782157 8451 0 0
T5 144711 21645 0 0
T6 0 6618 0 0
T7 0 32032 0 0
T8 0 20861 0 0
T9 13887 26 0 0
T12 10725 0 0 0
T13 1180200 0 0 0
T18 3885 0 0 0
T19 83544 2014 0 0
T22 0 55168 0 0
T27 0 7497 0 0
T30 0 16816 0 0
T33 0 8647 0 0
T45 0 16933 0 0
T47 0 252 0 0
T48 0 4792 0 0
T49 0 7 0 0

TlOutPayloadKnown_AKnownEnable
NameAttemptsReal SuccessesFailuresIncomplete
Total 1088966640 1086423144 0 0
T1 9585 9138 0 0
T2 321744 321729 0 0
T3 7029 6867 0 0
T4 782157 781938 0 0
T5 144711 144459 0 0
T9 13887 12384 0 0
T12 10725 8910 0 0
T13 1180200 1180164 0 0
T18 3885 3678 0 0
T19 83544 83379 0 0

WdataOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1088966640 1086423144 0 0
T1 9585 9138 0 0
T2 321744 321729 0 0
T3 7029 6867 0 0
T4 782157 781938 0 0
T5 144711 144459 0 0
T9 13887 12384 0 0
T12 10725 8910 0 0
T13 1180200 1180164 0 0
T18 3885 3678 0 0
T19 83544 83379 0 0

WeOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1088966640 1086423144 0 0
T1 9585 9138 0 0
T2 321744 321729 0 0
T3 7029 6867 0 0
T4 782157 781938 0 0
T5 144711 144459 0 0
T9 13887 12384 0 0
T12 10725 8910 0 0
T13 1180200 1180164 0 0
T18 3885 3678 0 0
T19 83544 83379 0 0

WmaskOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1088966640 1086423144 0 0
T1 9585 9138 0 0
T2 321744 321729 0 0
T3 7029 6867 0 0
T4 782157 781938 0 0
T5 144711 144459 0 0
T9 13887 12384 0 0
T12 10725 8910 0 0
T13 1180200 1180164 0 0
T18 3885 3678 0 0
T19 83544 83379 0 0

adapterNoReadOrWrite
NameAttemptsReal SuccessesFailuresIncomplete
Total 2973 2973 0 0
T1 3 3 0 0
T2 3 3 0 0
T3 3 3 0 0
T4 3 3 0 0
T5 3 3 0 0
T9 3 3 0 0
T12 3 3 0 0
T13 3 3 0 0
T18 3 3 0 0
T19 3 3 0 0

rvalidHighReqFifoEmpty
NameAttemptsReal SuccessesFailuresIncomplete
Total 1088966640 7090372 0 0
T1 6390 140 0 0
T2 214496 7060 0 0
T3 4686 146 0 0
T4 521438 0 0 0
T5 96474 21645 0 0
T7 0 32032 0 0
T8 0 20861 0 0
T9 9258 0 0 0
T12 7150 0 0 0
T13 786800 0 0 0
T18 2590 0 0 0
T19 55696 1252 0 0
T22 0 47728 0 0
T30 0 16816 0 0
T45 0 16933 0 0
T47 0 252 0 0
T48 0 3152 0 0
T49 0 7 0 0

rvalidHighWhenRspFifoFull
NameAttemptsReal SuccessesFailuresIncomplete
Total 1088301564 7084375 0 0
T1 6390 140 0 0
T2 214496 7060 0 0
T3 4686 146 0 0
T4 521438 0 0 0
T5 96474 21645 0 0
T7 0 32032 0 0
T8 0 20861 0 0
T9 9258 0 0 0
T12 7150 0 0 0
T13 786800 0 0 0
T18 2590 0 0 0
T19 55696 1252 0 0
T22 0 47728 0 0
T30 0 16816 0 0
T45 0 16933 0 0
T47 0 252 0 0
T48 0 3152 0 0
T49 0 7 0 0

Line Coverage for Instance : tb.dut.u_to_prog_fifo
Line No.TotalCoveredPercent
TOTAL615793.44
ALWAYS9333100.00
CONT_ASSIGN10211100.00
CONT_ASSIGN10711100.00
CONT_ASSIGN11411100.00
CONT_ASSIGN12511100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN22211100.00
CONT_ASSIGN22311100.00
CONT_ASSIGN22411100.00
ALWAYS2298675.00
ALWAYS2496583.33
CONT_ASSIGN26311100.00
CONT_ASSIGN26711100.00
CONT_ASSIGN28611100.00
CONT_ASSIGN29111100.00
CONT_ASSIGN29711100.00
CONT_ASSIGN30111100.00
CONT_ASSIGN32111100.00
CONT_ASSIGN32211100.00
CONT_ASSIGN32311100.00
CONT_ASSIGN32411100.00
ALWAYS35466100.00
ALWAYS36655100.00
CONT_ASSIGN37711100.00
CONT_ASSIGN37811100.00
CONT_ASSIGN38711100.00
CONT_ASSIGN38811100.00
CONT_ASSIGN39011100.00
CONT_ASSIGN39111100.00
CONT_ASSIGN39811100.00
CONT_ASSIGN40111100.00
CONT_ASSIGN40511100.00
CONT_ASSIGN40600
CONT_ASSIGN40800
CONT_ASSIGN41500
ALWAYS4213266.67
CONT_ASSIGN44211100.00
CONT_ASSIGN44711100.00
CONT_ASSIGN45200
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
93 1 1
94 1 1
95 1 1
96 unreachable
MISSING_ELSE
102 1 1
107 1 1
114 1 1
125 1 1
139 1 1
151 1 1
222 1 1
223 1 1
224 1 1
229 1 1
231 1 1
232 1 1
234 0 1
235 1 1
236 0 1
239 1 1
242 1 1
249 1 1
251 1 1
252 1 1
253 0 1
255 1 1
258 1 1
263 1 1
267 1 1
286 1 1
291 1 1
297 1 1
301 1 1
321 1 1
322 1 1
323 1 1
324 1 1
354 1 1
355 1 1
357 1 1
358 1 1
359 1 1
360 1 1
MISSING_ELSE
366 1 1
367 1 1
369 1 1
370 1 1
371 1 1
MISSING_ELSE
377 1 1
378 1 1
387 1 1
388 1 1
390 1 1
391 1 1
398 1 1
401 1 1
405 1 1
406 unreachable
408 unreachable
415 unreachable
421 1 1
425 1 1
427 0 1
MISSING_ELSE
442 1 1
447 1 1
452 unreachable


Cond Coverage for Instance : tb.dut.u_to_prog_fifo
TotalCoveredPercent
Conditions1117365.77
Logical1117365.77
Non-Logical00
Event00

 LINE       95
 EXPRESSION (intg_error || rsp_fifo_error)
             -----1----    -------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10Unreachable

 LINE       102
 EXPRESSION (intg_error | rsp_fifo_error | intg_error_q)
             -----1----   -------2------   ------3-----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001Not Covered
010Unreachable
100Unreachable

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T6,T22
10CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       125
 EXPRESSION (tl_i.a_opcode == Get)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       139
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----
-1--2--3--4--5--6-StatusTests
000000CoveredT1,T2,T4
000001Unreachable
000010CoveredT1,T2,T3
000100Not Covered
001000Not Covered
010000Unreachable
100000Not Covered

 LINE       222
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T4
11CoveredT1,T2,T4

 LINE       223
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T6,T22
11CoveredT1,T2,T4

 LINE       224
 EXPRESSION (req_o & gnt_i)
             --1--   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT9,T28,T29
11CoveredT1,T2,T4

 LINE       235
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T4
1Not Covered

 LINE       252
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T4
1Not Covered

 LINE       253
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered

 LINE       263
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101Not Covered
1110Not Covered
1111Not Covered

 LINE       263
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       291
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       291
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       297
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       297
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       297
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       301
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T4

 LINE       301
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T4

 LINE       301
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       301
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T4

 LINE       301
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T4

 LINE       301
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T4
11Not Covered

 LINE       301
 EXPRESSION ((gnt_i | error_internal) & reqfifo_wready & sramreqfifo_wready)
             ------------1-----------   -------2------   ---------3--------
-1--2--3-StatusTests
011CoveredT9,T28,T29
101CoveredT1,T2,T4
110Not Covered
111CoveredT1,T2,T3

 LINE       301
 SUB-EXPRESSION (gnt_i | error_internal)
                 --1--   -------2------
-1--2-StatusTests
00CoveredT2,T4,T9
01CoveredT1,T2,T3
10CoveredT1,T2,T4

 LINE       321
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T4
110Not Covered
111CoveredT1,T2,T4

 LINE       323
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T4

 LINE       324
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T4

 LINE       360
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T4

 LINE       360
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-
-1--2-StatusTests
01Not Covered
10Not Covered
11CoveredT1,T2,T4

 LINE       391
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       391
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       405
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T4
11Not Covered

 LINE       408
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT1,T2,T4
10Unreachable
11Unreachable

 LINE       447
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       447
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       447
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

Branch Coverage for Instance : tb.dut.u_to_prog_fifo
Line No.TotalCoveredPercent
Branches 26 18 69.23
TERNARY 107 2 2 100.00
TERNARY 291 2 1 50.00
TERNARY 297 3 1 33.33
TERNARY 324 2 2 100.00
TERNARY 447 2 1 50.00
IF 93 2 2 100.00
IF 231 4 2 50.00
IF 251 3 2 66.67
IF 357 2 2 100.00
IF 369 2 2 100.00
IF 425 2 1 50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 107 (((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 291 ((vld_rd_rsp & (~d_error))) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 297 ((vld_rd_rsp && reqfifo_rdata.error)) ? -2-: 297 (vld_rd_rsp) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Not Covered
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 324 (tl_i_int.a_valid) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 447 (((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 93 if ((!rst_ni)) -2-: 95 if ((intg_error || rsp_fifo_error))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Unreachable
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 231 if (reqfifo_rvalid) -2-: 232 if (reqfifo_rdata.error) -3-: 235 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2--3-StatusTests
1 1 - Not Covered
1 0 1 Not Covered
1 0 0 Covered T1,T2,T4
0 - - Covered T1,T2,T3


LineNo. Expression -1-: 251 if (reqfifo_rvalid) -2-: 252 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2-StatusTests
1 1 Not Covered
1 0 Covered T1,T2,T4
0 - Covered T1,T2,T3


LineNo. Expression -1-: 357 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 369 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 425 if ((|sramreqfifo_rdata.mask))

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_to_prog_fifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 14 14 100.00 12 85.71
Cover properties 0 0 0
Cover sequences 0 0 0
Total 14 14 100.00 12 85.71




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AddrOutKnown_A 362988880 362141048 0 0
DataIntgOptions_A 991 991 0 0
ReqOutKnown_A 362988880 362141048 0 0
SramDwHasByteGranularity_A 991 991 0 0
SramDwIsMultipleOfTlulWidth_A 991 991 0 0
TlOutKnown_A 362988880 362141048 0 0
TlOutPayloadKnown_A 362988880 3251651 0 0
TlOutPayloadKnown_AKnownEnable 362988880 362141048 0 0
WdataOutKnown_A 362988880 362141048 0 0
WeOutKnown_A 362988880 362141048 0 0
WmaskOutKnown_A 362988880 362141048 0 0
adapterNoReadOrWrite 991 991 0 0
rvalidHighReqFifoEmpty 362988880 0 0 0
rvalidHighWhenRspFifoFull 362988880 0 0 0


AddrOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 362988880 362141048 0 0
T1 3195 3046 0 0
T2 107248 107243 0 0
T3 2343 2289 0 0
T4 260719 260646 0 0
T5 48237 48153 0 0
T9 4629 4128 0 0
T12 3575 2970 0 0
T13 393400 393388 0 0
T18 1295 1226 0 0
T19 27848 27793 0 0

DataIntgOptions_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 991 991 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0

ReqOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 362988880 362141048 0 0
T1 3195 3046 0 0
T2 107248 107243 0 0
T3 2343 2289 0 0
T4 260719 260646 0 0
T5 48237 48153 0 0
T9 4629 4128 0 0
T12 3575 2970 0 0
T13 393400 393388 0 0
T18 1295 1226 0 0
T19 27848 27793 0 0

SramDwHasByteGranularity_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 991 991 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0

SramDwIsMultipleOfTlulWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 991 991 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0

TlOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 362988880 362141048 0 0
T1 3195 3046 0 0
T2 107248 107243 0 0
T3 2343 2289 0 0
T4 260719 260646 0 0
T5 48237 48153 0 0
T9 4629 4128 0 0
T12 3575 2970 0 0
T13 393400 393388 0 0
T18 1295 1226 0 0
T19 27848 27793 0 0

TlOutPayloadKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 362988880 3251651 0 0
T1 3195 4 0 0
T2 107248 10175 0 0
T3 2343 0 0 0
T4 260719 8451 0 0
T5 48237 0 0 0
T6 0 6618 0 0
T9 4629 26 0 0
T12 3575 0 0 0
T13 393400 0 0 0
T18 1295 0 0 0
T19 27848 762 0 0
T22 0 7440 0 0
T27 0 7497 0 0
T33 0 8647 0 0
T48 0 1640 0 0

TlOutPayloadKnown_AKnownEnable
NameAttemptsReal SuccessesFailuresIncomplete
Total 362988880 362141048 0 0
T1 3195 3046 0 0
T2 107248 107243 0 0
T3 2343 2289 0 0
T4 260719 260646 0 0
T5 48237 48153 0 0
T9 4629 4128 0 0
T12 3575 2970 0 0
T13 393400 393388 0 0
T18 1295 1226 0 0
T19 27848 27793 0 0

WdataOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 362988880 362141048 0 0
T1 3195 3046 0 0
T2 107248 107243 0 0
T3 2343 2289 0 0
T4 260719 260646 0 0
T5 48237 48153 0 0
T9 4629 4128 0 0
T12 3575 2970 0 0
T13 393400 393388 0 0
T18 1295 1226 0 0
T19 27848 27793 0 0

WeOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 362988880 362141048 0 0
T1 3195 3046 0 0
T2 107248 107243 0 0
T3 2343 2289 0 0
T4 260719 260646 0 0
T5 48237 48153 0 0
T9 4629 4128 0 0
T12 3575 2970 0 0
T13 393400 393388 0 0
T18 1295 1226 0 0
T19 27848 27793 0 0

WmaskOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 362988880 362141048 0 0
T1 3195 3046 0 0
T2 107248 107243 0 0
T3 2343 2289 0 0
T4 260719 260646 0 0
T5 48237 48153 0 0
T9 4629 4128 0 0
T12 3575 2970 0 0
T13 393400 393388 0 0
T18 1295 1226 0 0
T19 27848 27793 0 0

adapterNoReadOrWrite
NameAttemptsReal SuccessesFailuresIncomplete
Total 991 991 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0

rvalidHighReqFifoEmpty
NameAttemptsReal SuccessesFailuresIncomplete
Total 362988880 0 0 0

rvalidHighWhenRspFifoFull
NameAttemptsReal SuccessesFailuresIncomplete
Total 362988880 0 0 0

Line Coverage for Instance : tb.dut.u_to_rd_fifo
Line No.TotalCoveredPercent
TOTAL656295.38
ALWAYS9344100.00
CONT_ASSIGN10211100.00
CONT_ASSIGN10711100.00
CONT_ASSIGN11411100.00
CONT_ASSIGN11911100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN22211100.00
CONT_ASSIGN22311100.00
CONT_ASSIGN22411100.00
ALWAYS2298675.00
ALWAYS2496583.33
CONT_ASSIGN26311100.00
CONT_ASSIGN26711100.00
CONT_ASSIGN28611100.00
CONT_ASSIGN29111100.00
CONT_ASSIGN29711100.00
CONT_ASSIGN30111100.00
CONT_ASSIGN32111100.00
CONT_ASSIGN32211100.00
CONT_ASSIGN32311100.00
CONT_ASSIGN32411100.00
ALWAYS35466100.00
ALWAYS36655100.00
CONT_ASSIGN37711100.00
CONT_ASSIGN37811100.00
CONT_ASSIGN38711100.00
CONT_ASSIGN38811100.00
CONT_ASSIGN39011100.00
CONT_ASSIGN39111100.00
CONT_ASSIGN39811100.00
CONT_ASSIGN40111100.00
CONT_ASSIGN40511100.00
CONT_ASSIGN40611100.00
CONT_ASSIGN40811100.00
CONT_ASSIGN41511100.00
ALWAYS42133100.00
CONT_ASSIGN44211100.00
CONT_ASSIGN44711100.00
CONT_ASSIGN45200
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
93 1 1
94 1 1
95 1 1
96 1 1
MISSING_ELSE
102 1 1
107 1 1
114 1 1
119 1 1
139 1 1
151 1 1
222 1 1
223 1 1
224 1 1
229 1 1
231 1 1
232 1 1
234 0 1
235 1 1
236 1 1
239 0 1
242 1 1
249 1 1
251 1 1
252 1 1
253 1 1
255 0 1
258 1 1
263 1 1
267 1 1
286 1 1
291 1 1
297 1 1
301 1 1
321 1 1
322 1 1
323 1 1
324 1 1
354 1 1
355 1 1
357 1 1
358 1 1
359 1 1
360 1 1
MISSING_ELSE
366 1 1
367 1 1
369 1 1
370 1 1
371 1 1
MISSING_ELSE
377 1 1
378 1 1
387 1 1
388 1 1
390 1 1
391 1 1
398 1 1
401 1 1
405 1 1
406 1 1
408 1 1
415 1 1
421 1 1
425 1 1
427 1 1
MISSING_ELSE
442 1 1
447 1 1
452 unreachable


Cond Coverage for Instance : tb.dut.u_to_rd_fifo
TotalCoveredPercent
Conditions1158977.39
Logical1158977.39
Non-Logical00
Event00

 LINE       95
 EXPRESSION (intg_error || rsp_fifo_error)
             -----1----    -------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT15,T16,T17
10Unreachable

 LINE       102
 EXPRESSION (intg_error | rsp_fifo_error | intg_error_q)
             -----1----   -------2------   ------3-----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT15,T16,T17
010CoveredT15,T16,T17
100Unreachable

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T6,T22
10CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       119
 EXPRESSION (tl_i.a_opcode != Get)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       139
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----
-1--2--3--4--5--6-StatusTests
000000CoveredT1,T2,T3
000001Unreachable
000010CoveredT1,T2,T3
000100Not Covered
001000Unreachable
010000Not Covered
100000Not Covered

 LINE       222
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       223
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T22,T30
11CoveredT1,T2,T3

 LINE       224
 EXPRESSION (req_o & gnt_i)
             --1--   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT5,T8,T22
11CoveredT1,T2,T3

 LINE       235
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       252
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       253
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT15,T31,T32

 LINE       263
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101Not Covered
1110Not Covered
1111CoveredT1,T2,T3

 LINE       263
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       291
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       291
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT15,T31,T32
11CoveredT1,T2,T3

 LINE       297
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       297
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11Not Covered

 LINE       297
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       301
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       301
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11Not Covered

 LINE       301
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       301
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       301
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       301
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT15,T31,T32

 LINE       301
 EXPRESSION ((gnt_i | error_internal) & reqfifo_wready & sramreqfifo_wready)
             ------------1-----------   -------2------   ---------3--------
-1--2--3-StatusTests
011CoveredT5,T8,T22
101CoveredT33,T34,T35
110Not Covered
111CoveredT1,T2,T3

 LINE       301
 SUB-EXPRESSION (gnt_i | error_internal)
                 --1--   -------2------
-1--2-StatusTests
00CoveredT5,T8,T22
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       321
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       323
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11Not Covered

 LINE       324
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       360
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       360
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11Not Covered

 LINE       391
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       391
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       405
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       408
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT33,T34,T35
10Not Covered
11CoveredT1,T2,T3

 LINE       447
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       447
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       447
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_to_rd_fifo
Line No.TotalCoveredPercent
Branches 27 23 85.19
TERNARY 107 2 2 100.00
TERNARY 291 2 2 100.00
TERNARY 297 3 2 66.67
TERNARY 324 2 2 100.00
TERNARY 447 2 2 100.00
IF 93 3 3 100.00
IF 231 4 2 50.00
IF 251 3 2 66.67
IF 357 2 2 100.00
IF 369 2 2 100.00
IF 425 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 107 (((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 291 ((vld_rd_rsp & (~d_error))) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 297 ((vld_rd_rsp && reqfifo_rdata.error)) ? -2-: 297 (vld_rd_rsp) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 324 (tl_i_int.a_valid) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 447 (((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 93 if ((!rst_ni)) -2-: 95 if ((intg_error || rsp_fifo_error))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T15,T16,T17
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 231 if (reqfifo_rvalid) -2-: 232 if (reqfifo_rdata.error) -3-: 235 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2--3-StatusTests
1 1 - Not Covered
1 0 1 Covered T1,T2,T3
1 0 0 Not Covered
0 - - Covered T1,T2,T3


LineNo. Expression -1-: 251 if (reqfifo_rvalid) -2-: 252 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2-StatusTests
1 1 Covered T1,T2,T3
1 0 Not Covered
0 - Covered T1,T2,T3


LineNo. Expression -1-: 357 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 369 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 425 if ((|sramreqfifo_rdata.mask))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_to_rd_fifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 14 14 100.00 14 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 14 14 100.00 14 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AddrOutKnown_A 362988880 362141048 0 0
DataIntgOptions_A 991 991 0 0
ReqOutKnown_A 362988880 362141048 0 0
SramDwHasByteGranularity_A 991 991 0 0
SramDwIsMultipleOfTlulWidth_A 991 991 0 0
TlOutKnown_A 362988880 362141048 0 0
TlOutPayloadKnown_A 362988880 4584596 0 0
TlOutPayloadKnown_AKnownEnable 362988880 362141048 0 0
WdataOutKnown_A 362988880 362141048 0 0
WeOutKnown_A 362988880 362141048 0 0
WmaskOutKnown_A 362988880 362141048 0 0
adapterNoReadOrWrite 991 991 0 0
rvalidHighReqFifoEmpty 362988880 2892716 0 0
rvalidHighWhenRspFifoFull 362323804 2886719 0 0


AddrOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 362988880 362141048 0 0
T1 3195 3046 0 0
T2 107248 107243 0 0
T3 2343 2289 0 0
T4 260719 260646 0 0
T5 48237 48153 0 0
T9 4629 4128 0 0
T12 3575 2970 0 0
T13 393400 393388 0 0
T18 1295 1226 0 0
T19 27848 27793 0 0

DataIntgOptions_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 991 991 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0

ReqOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 362988880 362141048 0 0
T1 3195 3046 0 0
T2 107248 107243 0 0
T3 2343 2289 0 0
T4 260719 260646 0 0
T5 48237 48153 0 0
T9 4629 4128 0 0
T12 3575 2970 0 0
T13 393400 393388 0 0
T18 1295 1226 0 0
T19 27848 27793 0 0

SramDwHasByteGranularity_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 991 991 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0

SramDwIsMultipleOfTlulWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 991 991 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0

TlOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 362988880 362141048 0 0
T1 3195 3046 0 0
T2 107248 107243 0 0
T3 2343 2289 0 0
T4 260719 260646 0 0
T5 48237 48153 0 0
T9 4629 4128 0 0
T12 3575 2970 0 0
T13 393400 393388 0 0
T18 1295 1226 0 0
T19 27848 27793 0 0

TlOutPayloadKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 362988880 4584596 0 0
T1 3195 133 0 0
T2 107248 7060 0 0
T3 2343 146 0 0
T4 260719 0 0 0
T5 48237 5736 0 0
T7 0 15792 0 0
T8 0 4763 0 0
T9 4629 0 0 0
T12 3575 0 0 0
T13 393400 0 0 0
T18 1295 0 0 0
T19 27848 898 0 0
T22 0 5812 0 0
T47 0 240 0 0
T48 0 3152 0 0

TlOutPayloadKnown_AKnownEnable
NameAttemptsReal SuccessesFailuresIncomplete
Total 362988880 362141048 0 0
T1 3195 3046 0 0
T2 107248 107243 0 0
T3 2343 2289 0 0
T4 260719 260646 0 0
T5 48237 48153 0 0
T9 4629 4128 0 0
T12 3575 2970 0 0
T13 393400 393388 0 0
T18 1295 1226 0 0
T19 27848 27793 0 0

WdataOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 362988880 362141048 0 0
T1 3195 3046 0 0
T2 107248 107243 0 0
T3 2343 2289 0 0
T4 260719 260646 0 0
T5 48237 48153 0 0
T9 4629 4128 0 0
T12 3575 2970 0 0
T13 393400 393388 0 0
T18 1295 1226 0 0
T19 27848 27793 0 0

WeOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 362988880 362141048 0 0
T1 3195 3046 0 0
T2 107248 107243 0 0
T3 2343 2289 0 0
T4 260719 260646 0 0
T5 48237 48153 0 0
T9 4629 4128 0 0
T12 3575 2970 0 0
T13 393400 393388 0 0
T18 1295 1226 0 0
T19 27848 27793 0 0

WmaskOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 362988880 362141048 0 0
T1 3195 3046 0 0
T2 107248 107243 0 0
T3 2343 2289 0 0
T4 260719 260646 0 0
T5 48237 48153 0 0
T9 4629 4128 0 0
T12 3575 2970 0 0
T13 393400 393388 0 0
T18 1295 1226 0 0
T19 27848 27793 0 0

adapterNoReadOrWrite
NameAttemptsReal SuccessesFailuresIncomplete
Total 991 991 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0

rvalidHighReqFifoEmpty
NameAttemptsReal SuccessesFailuresIncomplete
Total 362988880 2892716 0 0
T1 3195 133 0 0
T2 107248 7060 0 0
T3 2343 146 0 0
T4 260719 0 0 0
T5 48237 5736 0 0
T7 0 15792 0 0
T8 0 4763 0 0
T9 4629 0 0 0
T12 3575 0 0 0
T13 393400 0 0 0
T18 1295 0 0 0
T19 27848 898 0 0
T22 0 5812 0 0
T47 0 240 0 0
T48 0 3152 0 0

rvalidHighWhenRspFifoFull
NameAttemptsReal SuccessesFailuresIncomplete
Total 362323804 2886719 0 0
T1 3195 133 0 0
T2 107248 7060 0 0
T3 2343 146 0 0
T4 260719 0 0 0
T5 48237 5736 0 0
T7 0 15792 0 0
T8 0 4763 0 0
T9 4629 0 0 0
T12 3575 0 0 0
T13 393400 0 0 0
T18 1295 0 0 0
T19 27848 898 0 0
T22 0 5812 0 0
T47 0 240 0 0
T48 0 3152 0 0

Line Coverage for Instance : tb.dut.u_tl_adapter_eflash
Line No.TotalCoveredPercent
TOTAL656498.46
ALWAYS9344100.00
CONT_ASSIGN10211100.00
CONT_ASSIGN10711100.00
CONT_ASSIGN11411100.00
CONT_ASSIGN11911100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN22211100.00
CONT_ASSIGN22311100.00
CONT_ASSIGN22411100.00
ALWAYS2298787.50
ALWAYS24966100.00
CONT_ASSIGN26311100.00
CONT_ASSIGN26711100.00
CONT_ASSIGN28611100.00
CONT_ASSIGN29111100.00
CONT_ASSIGN29711100.00
CONT_ASSIGN30111100.00
CONT_ASSIGN32111100.00
CONT_ASSIGN32211100.00
CONT_ASSIGN32311100.00
CONT_ASSIGN32411100.00
ALWAYS35466100.00
ALWAYS36655100.00
CONT_ASSIGN37711100.00
CONT_ASSIGN37811100.00
CONT_ASSIGN38711100.00
CONT_ASSIGN38811100.00
CONT_ASSIGN39011100.00
CONT_ASSIGN39111100.00
CONT_ASSIGN39811100.00
CONT_ASSIGN40111100.00
CONT_ASSIGN40511100.00
CONT_ASSIGN40611100.00
CONT_ASSIGN40811100.00
CONT_ASSIGN41511100.00
ALWAYS42133100.00
CONT_ASSIGN44211100.00
CONT_ASSIGN44711100.00
CONT_ASSIGN45200
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
93 1 1
94 1 1
95 1 1
96 1 1
MISSING_ELSE
102 1 1
107 1 1
114 1 1
119 1 1
139 1 1
151 1 1
222 1 1
223 1 1
224 1 1
229 1 1
231 1 1
232 1 1
234 1 1
235 1 1
236 1 1
239 0 1
242 1 1
249 1 1
251 1 1
252 1 1
253 1 1
255 1 1
258 1 1
263 1 1
267 1 1
286 1 1
291 1 1
297 1 1
301 1 1
321 1 1
322 1 1
323 1 1
324 1 1
354 1 1
355 1 1
357 1 1
358 1 1
359 1 1
360 1 1
MISSING_ELSE
366 1 1
367 1 1
369 1 1
370 1 1
371 1 1
MISSING_ELSE
377 1 1
378 1 1
387 1 1
388 1 1
390 1 1
391 1 1
398 1 1
401 1 1
405 1 1
406 1 1
408 1 1
415 1 1
421 1 1
425 1 1
427 1 1
MISSING_ELSE
442 1 1
447 1 1
452 unreachable


Cond Coverage for Instance : tb.dut.u_tl_adapter_eflash
TotalCoveredPercent
Conditions11610187.07
Logical11610187.07
Non-Logical00
Event00

 LINE       95
 EXPRESSION (intg_error || rsp_fifo_error)
             -----1----    -------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT36,T37,T38

 LINE       102
 EXPRESSION (intg_error | rsp_fifo_error | intg_error_q)
             -----1----   -------2------   ------3-----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT36,T37,T38
010Unreachable
100CoveredT36,T37,T38

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)
-1-StatusTests
0CoveredT1,T5,T19
1CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------
-1--2-StatusTests
00CoveredT1,T5,T19
01CoveredT3,T4,T5
10CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T5

 LINE       107
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------
-1--2-StatusTests
00CoveredT5,T20,T39
01CoveredT5,T33,T40
10CoveredT3,T4,T5

 LINE       107
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------
-1-StatusTests
0CoveredT5,T33,T40
1CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------
-1-StatusTests
0CoveredT3,T4,T5
1CoveredT1,T2,T3

 LINE       119
 EXPRESSION (tl_i.a_opcode != Get)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       139
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----
-1--2--3--4--5--6-StatusTests
000000CoveredT1,T5,T19
000001CoveredT37
000010CoveredT5,T33,T41
000100CoveredT42,T43,T44
001000Unreachable
010000Not Covered
100000Not Covered

 LINE       222
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT5,T7,T8
11CoveredT1,T5,T19

 LINE       223
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT5,T20,T21
11CoveredT1,T5,T19

 LINE       224
 EXPRESSION (req_o & gnt_i)
             --1--   --2--
-1--2-StatusTests
01Not Covered
10CoveredT5,T7,T8
11CoveredT1,T5,T19

 LINE       235
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0Not Covered
1CoveredT1,T5,T19

 LINE       252
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT38
1CoveredT1,T5,T19

 LINE       253
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------
-1--2-StatusTests
00CoveredT1,T5,T19
01CoveredT42,T43,T44
10CoveredT22,T45,T46

 LINE       263
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101CoveredT42,T43,T44
1110Not Covered
1111CoveredT1,T5,T19

 LINE       263
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T5,T19

 LINE       291
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T5,T19

 LINE       291
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT22,T45,T46
11CoveredT1,T5,T19

 LINE       297
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       297
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------
-1--2-StatusTests
01CoveredT42,T43,T44
10CoveredT1,T5,T19
11Not Covered

 LINE       297
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T5,T19

 LINE       301
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT38

 LINE       301
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T5,T19
11CoveredT38

 LINE       301
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       301
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T5,T19

 LINE       301
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T5,T19

 LINE       301
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T5,T19
11CoveredT22,T45,T46

 LINE       301
 EXPRESSION ((gnt_i | error_internal) & reqfifo_wready & sramreqfifo_wready)
             ------------1-----------   -------2------   ---------3--------
-1--2--3-StatusTests
011CoveredT5,T7,T8
101CoveredT42,T43,T44
110Not Covered
111CoveredT1,T2,T3

 LINE       301
 SUB-EXPRESSION (gnt_i | error_internal)
                 --1--   -------2------
-1--2-StatusTests
00CoveredT5,T7,T8
01CoveredT1,T2,T3
10CoveredT1,T5,T19

 LINE       321
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT5,T7,T8
110CoveredT42,T43,T44
111CoveredT1,T5,T19

 LINE       323
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T5,T19
11CoveredT38

 LINE       324
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T5,T19

 LINE       360
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------
-1-StatusTests
0CoveredT1,T5,T19
1CoveredT38

 LINE       360
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-
-1--2-StatusTests
01Not Covered
10CoveredT1,T5,T19
11CoveredT38

 LINE       391
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------
-1-StatusTests
0CoveredT1,T5,T19
1CoveredT1,T2,T3

 LINE       391
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       405
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T5,T19

 LINE       408
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT1,T5,T19
10Not Covered
11CoveredT1,T5,T19

 LINE       447
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T5,T19

 LINE       447
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT42,T43,T44
11CoveredT1,T5,T19

 LINE       447
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T5,T19

Branch Coverage for Instance : tb.dut.u_tl_adapter_eflash
Line No.TotalCoveredPercent
Branches 27 25 92.59
TERNARY 107 2 2 100.00
TERNARY 291 2 2 100.00
TERNARY 297 3 2 66.67
TERNARY 324 2 2 100.00
TERNARY 447 2 2 100.00
IF 93 3 3 100.00
IF 231 4 3 75.00
IF 251 3 3 100.00
IF 357 2 2 100.00
IF 369 2 2 100.00
IF 425 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 107 (((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T5,T19


LineNo. Expression -1-: 291 ((vld_rd_rsp & (~d_error))) ?

Branches:
-1-StatusTests
1 Covered T1,T5,T19
0 Covered T1,T2,T3


LineNo. Expression -1-: 297 ((vld_rd_rsp && reqfifo_rdata.error)) ? -2-: 297 (vld_rd_rsp) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Covered T1,T5,T19
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 324 (tl_i_int.a_valid) ?

Branches:
-1-StatusTests
1 Covered T1,T5,T19
0 Covered T1,T2,T3


LineNo. Expression -1-: 447 (((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ?

Branches:
-1-StatusTests
1 Covered T1,T5,T19
0 Covered T1,T2,T3


LineNo. Expression -1-: 93 if ((!rst_ni)) -2-: 95 if ((intg_error || rsp_fifo_error))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T36,T37,T38
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 231 if (reqfifo_rvalid) -2-: 232 if (reqfifo_rdata.error) -3-: 235 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2--3-StatusTests
1 1 - Covered T42,T43,T44
1 0 1 Covered T1,T5,T19
1 0 0 Not Covered
0 - - Covered T1,T2,T3


LineNo. Expression -1-: 251 if (reqfifo_rvalid) -2-: 252 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2-StatusTests
1 1 Covered T1,T5,T19
1 0 Covered T38
0 - Covered T1,T2,T3


LineNo. Expression -1-: 357 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T1,T5,T19
0 Covered T1,T2,T3


LineNo. Expression -1-: 369 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T1,T5,T19
0 Covered T1,T2,T3


LineNo. Expression -1-: 425 if ((|sramreqfifo_rdata.mask))

Branches:
-1-StatusTests
1 Covered T1,T5,T19
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_tl_adapter_eflash
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 14 14 100.00 14 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 14 14 100.00 14 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AddrOutKnown_A 362988880 362141048 0 0
DataIntgOptions_A 991 991 0 0
ReqOutKnown_A 362988880 362141048 0 0
SramDwHasByteGranularity_A 991 991 0 0
SramDwIsMultipleOfTlulWidth_A 991 991 0 0
TlOutKnown_A 362988880 362141048 0 0
TlOutPayloadKnown_A 362988880 4871999 0 0
TlOutPayloadKnown_AKnownEnable 362988880 362141048 0 0
WdataOutKnown_A 362988880 362141048 0 0
WeOutKnown_A 362988880 362141048 0 0
WmaskOutKnown_A 362988880 362141048 0 0
adapterNoReadOrWrite 991 991 0 0
rvalidHighReqFifoEmpty 362988880 4197656 0 0
rvalidHighWhenRspFifoFull 362988880 4197656 0 0


AddrOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 362988880 362141048 0 0
T1 3195 3046 0 0
T2 107248 107243 0 0
T3 2343 2289 0 0
T4 260719 260646 0 0
T5 48237 48153 0 0
T9 4629 4128 0 0
T12 3575 2970 0 0
T13 393400 393388 0 0
T18 1295 1226 0 0
T19 27848 27793 0 0

DataIntgOptions_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 991 991 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0

ReqOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 362988880 362141048 0 0
T1 3195 3046 0 0
T2 107248 107243 0 0
T3 2343 2289 0 0
T4 260719 260646 0 0
T5 48237 48153 0 0
T9 4629 4128 0 0
T12 3575 2970 0 0
T13 393400 393388 0 0
T18 1295 1226 0 0
T19 27848 27793 0 0

SramDwHasByteGranularity_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 991 991 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0

SramDwIsMultipleOfTlulWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 991 991 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0

TlOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 362988880 362141048 0 0
T1 3195 3046 0 0
T2 107248 107243 0 0
T3 2343 2289 0 0
T4 260719 260646 0 0
T5 48237 48153 0 0
T9 4629 4128 0 0
T12 3575 2970 0 0
T13 393400 393388 0 0
T18 1295 1226 0 0
T19 27848 27793 0 0

TlOutPayloadKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 362988880 4871999 0 0
T1 3195 7 0 0
T2 107248 0 0 0
T3 2343 0 0 0
T4 260719 0 0 0
T5 48237 15909 0 0
T7 0 16240 0 0
T8 0 16098 0 0
T9 4629 0 0 0
T12 3575 0 0 0
T13 393400 0 0 0
T18 1295 0 0 0
T19 27848 354 0 0
T22 0 41916 0 0
T30 0 16816 0 0
T45 0 16933 0 0
T47 0 12 0 0
T49 0 7 0 0

TlOutPayloadKnown_AKnownEnable
NameAttemptsReal SuccessesFailuresIncomplete
Total 362988880 362141048 0 0
T1 3195 3046 0 0
T2 107248 107243 0 0
T3 2343 2289 0 0
T4 260719 260646 0 0
T5 48237 48153 0 0
T9 4629 4128 0 0
T12 3575 2970 0 0
T13 393400 393388 0 0
T18 1295 1226 0 0
T19 27848 27793 0 0

WdataOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 362988880 362141048 0 0
T1 3195 3046 0 0
T2 107248 107243 0 0
T3 2343 2289 0 0
T4 260719 260646 0 0
T5 48237 48153 0 0
T9 4629 4128 0 0
T12 3575 2970 0 0
T13 393400 393388 0 0
T18 1295 1226 0 0
T19 27848 27793 0 0

WeOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 362988880 362141048 0 0
T1 3195 3046 0 0
T2 107248 107243 0 0
T3 2343 2289 0 0
T4 260719 260646 0 0
T5 48237 48153 0 0
T9 4629 4128 0 0
T12 3575 2970 0 0
T13 393400 393388 0 0
T18 1295 1226 0 0
T19 27848 27793 0 0

WmaskOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 362988880 362141048 0 0
T1 3195 3046 0 0
T2 107248 107243 0 0
T3 2343 2289 0 0
T4 260719 260646 0 0
T5 48237 48153 0 0
T9 4629 4128 0 0
T12 3575 2970 0 0
T13 393400 393388 0 0
T18 1295 1226 0 0
T19 27848 27793 0 0

adapterNoReadOrWrite
NameAttemptsReal SuccessesFailuresIncomplete
Total 991 991 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0

rvalidHighReqFifoEmpty
NameAttemptsReal SuccessesFailuresIncomplete
Total 362988880 4197656 0 0
T1 3195 7 0 0
T2 107248 0 0 0
T3 2343 0 0 0
T4 260719 0 0 0
T5 48237 15909 0 0
T7 0 16240 0 0
T8 0 16098 0 0
T9 4629 0 0 0
T12 3575 0 0 0
T13 393400 0 0 0
T18 1295 0 0 0
T19 27848 354 0 0
T22 0 41916 0 0
T30 0 16816 0 0
T45 0 16933 0 0
T47 0 12 0 0
T49 0 7 0 0

rvalidHighWhenRspFifoFull
NameAttemptsReal SuccessesFailuresIncomplete
Total 362988880 4197656 0 0
T1 3195 7 0 0
T2 107248 0 0 0
T3 2343 0 0 0
T4 260719 0 0 0
T5 48237 15909 0 0
T7 0 16240 0 0
T8 0 16098 0 0
T9 4629 0 0 0
T12 3575 0 0 0
T13 393400 0 0 0
T18 1295 0 0 0
T19 27848 354 0 0
T22 0 41916 0 0
T30 0 16816 0 0
T45 0 16933 0 0
T47 0 12 0 0
T49 0 7 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%