Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T19

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T5,T19
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T5,T19
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T5,T19

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T19
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T7,T8
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T5,T19

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T5,T19

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1451955520	1448564192	0	0
CheckNGreaterZero_A	3964	3964	0	0
GntImpliesReady_A	1451955520	390332028	0	0
GntImpliesValid_A	1451955520	390332028	0	0
GrantKnown_A	1451955520	1448564192	0	0
IdxKnown_A	1451955520	1448564192	0	0
IndexIsCorrect_A	1451955520	390332028	0	0
NoReadyValidNoGrant_A	1451955520	159780297	0	0
Priority_A	1451955520	414487851	0	0
ReadyAndValidImplyGrant_A	1451955520	390332028	0	0
ReqAndReadyImplyGrant_A	1451955520	390332028	0	0
ReqImpliesValid_A	1451955520	414487851	0	0
ValidKnown_A	1451955520	1448564192	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451955520	1448564192	0	0
T1	12780	12184	0	0
T2	428992	428972	0	0
T3	9372	9156	0	0
T4	1042876	1042584	0	0
T5	192948	192612	0	0
T9	18516	16512	0	0
T12	14300	11880	0	0
T13	1573600	1573552	0	0
T18	5180	4904	0	0
T19	111392	111172	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3964	3964	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T9	4	4	0	0
T12	4	4	0	0
T13	4	4	0	0
T18	4	4	0	0
T19	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451955520	390332028	0	0
T1	6390	542	0	0
T2	428992	1555976	0	0
T3	9372	356	0	0
T4	1042876	480992	0	0
T5	192948	43354	0	0
T6	0	201578	0	0
T7	0	31952	0	0
T8	0	17088	0	0
T9	18516	480	0	0
T12	14300	378	0	0
T13	1573600	514658	0	0
T14	3036	0	0	0
T18	5180	64	0	0
T19	111392	37778	0	0
T22	0	158232	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451955520	390332028	0	0
T1	6390	542	0	0
T2	428992	1555976	0	0
T3	9372	356	0	0
T4	1042876	480992	0	0
T5	192948	43354	0	0
T6	0	201578	0	0
T7	0	31952	0	0
T8	0	17088	0	0
T9	18516	480	0	0
T12	14300	378	0	0
T13	1573600	514658	0	0
T14	3036	0	0	0
T18	5180	64	0	0
T19	111392	37778	0	0
T22	0	158232	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451955520	1448564192	0	0
T1	12780	12184	0	0
T2	428992	428972	0	0
T3	9372	9156	0	0
T4	1042876	1042584	0	0
T5	192948	192612	0	0
T9	18516	16512	0	0
T12	14300	11880	0	0
T13	1573600	1573552	0	0
T18	5180	4904	0	0
T19	111392	111172	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451955520	1448564192	0	0
T1	12780	12184	0	0
T2	428992	428972	0	0
T3	9372	9156	0	0
T4	1042876	1042584	0	0
T5	192948	192612	0	0
T9	18516	16512	0	0
T12	14300	11880	0	0
T13	1573600	1573552	0	0
T18	5180	4904	0	0
T19	111392	111172	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451955520	390332028	0	0
T1	6390	542	0	0
T2	428992	1555976	0	0
T3	9372	356	0	0
T4	1042876	480992	0	0
T5	192948	43354	0	0
T6	0	201578	0	0
T7	0	31952	0	0
T8	0	17088	0	0
T9	18516	480	0	0
T12	14300	378	0	0
T13	1573600	514658	0	0
T14	3036	0	0	0
T18	5180	64	0	0
T19	111392	37778	0	0
T22	0	158232	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451955520	159780297	0	0
T1	6390	986	0	0
T2	428992	7118	0	0
T3	9372	992	0	0
T4	1042876	256	0	0
T5	192948	58212	0	0
T7	0	84480	0	0
T8	0	48928	0	0
T9	18516	1536	0	0
T12	14300	1412	0	0
T13	1573600	2109952	0	0
T14	3036	0	0	0
T18	5180	256	0	0
T19	111392	4012	0	0
T22	0	154518	0	0
T27	0	8118	0	0
T30	0	84854	0	0
T41	0	4	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451955520	414487851	0	0
T1	6390	542	0	0
T2	428992	1555976	0	0
T3	9372	356	0	0
T4	1042876	480992	0	0
T5	192948	53696	0	0
T6	0	201578	0	0
T7	0	33446	0	0
T8	0	17758	0	0
T9	18516	480	0	0
T12	14300	378	0	0
T13	1573600	514658	0	0
T14	3036	0	0	0
T18	5180	64	0	0
T19	111392	37778	0	0
T22	0	181486	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451955520	390332028	0	0
T1	6390	542	0	0
T2	428992	1555976	0	0
T3	9372	356	0	0
T4	1042876	480992	0	0
T5	192948	43354	0	0
T6	0	201578	0	0
T7	0	31952	0	0
T8	0	17088	0	0
T9	18516	480	0	0
T12	14300	378	0	0
T13	1573600	514658	0	0
T14	3036	0	0	0
T18	5180	64	0	0
T19	111392	37778	0	0
T22	0	158232	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451955520	390332028	0	0
T1	6390	542	0	0
T2	428992	1555976	0	0
T3	9372	356	0	0
T4	1042876	480992	0	0
T5	192948	43354	0	0
T6	0	201578	0	0
T7	0	31952	0	0
T8	0	17088	0	0
T9	18516	480	0	0
T12	14300	378	0	0
T13	1573600	514658	0	0
T14	3036	0	0	0
T18	5180	64	0	0
T19	111392	37778	0	0
T22	0	158232	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451955520	414487851	0	0
T1	6390	542	0	0
T2	428992	1555976	0	0
T3	9372	356	0	0
T4	1042876	480992	0	0
T5	192948	53696	0	0
T6	0	201578	0	0
T7	0	33446	0	0
T8	0	17758	0	0
T9	18516	480	0	0
T12	14300	378	0	0
T13	1573600	514658	0	0
T14	3036	0	0	0
T18	5180	64	0	0
T19	111392	37778	0	0
T22	0	181486	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451955520	1448564192	0	0
T1	12780	12184	0	0
T2	428992	428972	0	0
T3	9372	9156	0	0
T4	1042876	1042584	0	0
T5	192948	192612	0	0
T9	18516	16512	0	0
T12	14300	11880	0	0
T13	1573600	1573552	0	0
T18	5180	4904	0	0
T19	111392	111172	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T19

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T5,T19
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T5,T19
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T5,T19

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T19
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T7,T8
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T5,T19

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T5,T19

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	362988880	362141048	0	0
CheckNGreaterZero_A	991	991	0	0
GntImpliesReady_A	362988880	106012094	0	0
GntImpliesValid_A	362988880	106012094	0	0
GrantKnown_A	362988880	362141048	0	0
IdxKnown_A	362988880	362141048	0	0
IndexIsCorrect_A	362988880	106012094	0	0
NoReadyValidNoGrant_A	362988880	41699856	0	0
Priority_A	362988880	112328153	0	0
ReadyAndValidImplyGrant_A	362988880	106012094	0	0
ReqAndReadyImplyGrant_A	362988880	106012094	0	0
ReqImpliesValid_A	362988880	112328153	0	0
ValidKnown_A	362988880	362141048	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362988880	362141048	0	0
T1	3195	3046	0	0
T2	107248	107243	0	0
T3	2343	2289	0	0
T4	260719	260646	0	0
T5	48237	48153	0	0
T9	4629	4128	0	0
T12	3575	2970	0	0
T13	393400	393388	0	0
T18	1295	1226	0	0
T19	27848	27793	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	991	991	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362988880	106012094	0	0
T1	3195	271	0	0
T2	107248	773968	0	0
T3	2343	178	0	0
T4	260719	140912	0	0
T5	48237	11101	0	0
T9	4629	218	0	0
T12	3575	189	0	0
T13	393400	129432	0	0
T18	1295	32	0	0
T19	27848	11809	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362988880	106012094	0	0
T1	3195	271	0	0
T2	107248	773968	0	0
T3	2343	178	0	0
T4	260719	140912	0	0
T5	48237	11101	0	0
T9	4629	218	0	0
T12	3575	189	0	0
T13	393400	129432	0	0
T18	1295	32	0	0
T19	27848	11809	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362988880	362141048	0	0
T1	3195	3046	0	0
T2	107248	107243	0	0
T3	2343	2289	0	0
T4	260719	260646	0	0
T5	48237	48153	0	0
T9	4629	4128	0	0
T12	3575	2970	0	0
T13	393400	393388	0	0
T18	1295	1226	0	0
T19	27848	27793	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362988880	362141048	0	0
T1	3195	3046	0	0
T2	107248	107243	0	0
T3	2343	2289	0	0
T4	260719	260646	0	0
T5	48237	48153	0	0
T9	4629	4128	0	0
T12	3575	2970	0	0
T13	393400	393388	0	0
T18	1295	1226	0	0
T19	27848	27793	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362988880	106012094	0	0
T1	3195	271	0	0
T2	107248	773968	0	0
T3	2343	178	0	0
T4	260719	140912	0	0
T5	48237	11101	0	0
T9	4629	218	0	0
T12	3575	189	0	0
T13	393400	129432	0	0
T18	1295	32	0	0
T19	27848	11809	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362988880	41699856	0	0
T1	3195	493	0	0
T2	107248	3371	0	0
T3	2343	496	0	0
T4	260719	128	0	0
T5	48237	14617	0	0
T9	4629	768	0	0
T12	3575	706	0	0
T13	393400	530688	0	0
T18	1295	128	0	0
T19	27848	1298	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362988880	112328153	0	0
T1	3195	271	0	0
T2	107248	773968	0	0
T3	2343	178	0	0
T4	260719	140912	0	0
T5	48237	13905	0	0
T9	4629	218	0	0
T12	3575	189	0	0
T13	393400	129432	0	0
T18	1295	32	0	0
T19	27848	11809	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362988880	106012094	0	0
T1	3195	271	0	0
T2	107248	773968	0	0
T3	2343	178	0	0
T4	260719	140912	0	0
T5	48237	11101	0	0
T9	4629	218	0	0
T12	3575	189	0	0
T13	393400	129432	0	0
T18	1295	32	0	0
T19	27848	11809	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362988880	106012094	0	0
T1	3195	271	0	0
T2	107248	773968	0	0
T3	2343	178	0	0
T4	260719	140912	0	0
T5	48237	11101	0	0
T9	4629	218	0	0
T12	3575	189	0	0
T13	393400	129432	0	0
T18	1295	32	0	0
T19	27848	11809	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362988880	112328153	0	0
T1	3195	271	0	0
T2	107248	773968	0	0
T3	2343	178	0	0
T4	260719	140912	0	0
T5	48237	13905	0	0
T9	4629	218	0	0
T12	3575	189	0	0
T13	393400	129432	0	0
T18	1295	32	0	0
T19	27848	11809	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362988880	362141048	0	0
T1	3195	3046	0	0
T2	107248	107243	0	0
T3	2343	2289	0	0
T4	260719	260646	0	0
T5	48237	48153	0	0
T9	4629	4128	0	0
T12	3575	2970	0	0
T13	393400	393388	0	0
T18	1295	1226	0	0
T19	27848	27793	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T19

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T5,T19
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T5,T19
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T5,T19

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T19
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T7,T8
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T5,T19

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T5,T19

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	362988880	362141048	0	0
CheckNGreaterZero_A	991	991	0	0
GntImpliesReady_A	362988880	105857508	0	0
GntImpliesValid_A	362988880	105857508	0	0
GrantKnown_A	362988880	362141048	0	0
IdxKnown_A	362988880	362141048	0	0
IndexIsCorrect_A	362988880	105857508	0	0
NoReadyValidNoGrant_A	362988880	41699857	0	0
Priority_A	362988880	112173566	0	0
ReadyAndValidImplyGrant_A	362988880	105857508	0	0
ReqAndReadyImplyGrant_A	362988880	105857508	0	0
ReqImpliesValid_A	362988880	112173566	0	0
ValidKnown_A	362988880	362141048	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362988880	362141048	0	0
T1	3195	3046	0	0
T2	107248	107243	0	0
T3	2343	2289	0	0
T4	260719	260646	0	0
T5	48237	48153	0	0
T9	4629	4128	0	0
T12	3575	2970	0	0
T13	393400	393388	0	0
T18	1295	1226	0	0
T19	27848	27793	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	991	991	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362988880	105857508	0	0
T1	3195	271	0	0
T2	107248	773968	0	0
T3	2343	178	0	0
T4	260719	140912	0	0
T5	48237	11101	0	0
T9	4629	218	0	0
T12	3575	189	0	0
T13	393400	129432	0	0
T18	1295	32	0	0
T19	27848	11809	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362988880	105857508	0	0
T1	3195	271	0	0
T2	107248	773968	0	0
T3	2343	178	0	0
T4	260719	140912	0	0
T5	48237	11101	0	0
T9	4629	218	0	0
T12	3575	189	0	0
T13	393400	129432	0	0
T18	1295	32	0	0
T19	27848	11809	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362988880	362141048	0	0
T1	3195	3046	0	0
T2	107248	107243	0	0
T3	2343	2289	0	0
T4	260719	260646	0	0
T5	48237	48153	0	0
T9	4629	4128	0	0
T12	3575	2970	0	0
T13	393400	393388	0	0
T18	1295	1226	0	0
T19	27848	27793	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362988880	362141048	0	0
T1	3195	3046	0	0
T2	107248	107243	0	0
T3	2343	2289	0	0
T4	260719	260646	0	0
T5	48237	48153	0	0
T9	4629	4128	0	0
T12	3575	2970	0	0
T13	393400	393388	0	0
T18	1295	1226	0	0
T19	27848	27793	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362988880	105857508	0	0
T1	3195	271	0	0
T2	107248	773968	0	0
T3	2343	178	0	0
T4	260719	140912	0	0
T5	48237	11101	0	0
T9	4629	218	0	0
T12	3575	189	0	0
T13	393400	129432	0	0
T18	1295	32	0	0
T19	27848	11809	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362988880	41699857	0	0
T1	3195	493	0	0
T2	107248	3371	0	0
T3	2343	496	0	0
T4	260719	128	0	0
T5	48237	14617	0	0
T9	4629	768	0	0
T12	3575	706	0	0
T13	393400	530688	0	0
T18	1295	128	0	0
T19	27848	1298	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362988880	112173566	0	0
T1	3195	271	0	0
T2	107248	773968	0	0
T3	2343	178	0	0
T4	260719	140912	0	0
T5	48237	13905	0	0
T9	4629	218	0	0
T12	3575	189	0	0
T13	393400	129432	0	0
T18	1295	32	0	0
T19	27848	11809	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362988880	105857508	0	0
T1	3195	271	0	0
T2	107248	773968	0	0
T3	2343	178	0	0
T4	260719	140912	0	0
T5	48237	11101	0	0
T9	4629	218	0	0
T12	3575	189	0	0
T13	393400	129432	0	0
T18	1295	32	0	0
T19	27848	11809	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362988880	105857508	0	0
T1	3195	271	0	0
T2	107248	773968	0	0
T3	2343	178	0	0
T4	260719	140912	0	0
T5	48237	11101	0	0
T9	4629	218	0	0
T12	3575	189	0	0
T13	393400	129432	0	0
T18	1295	32	0	0
T19	27848	11809	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362988880	112173566	0	0
T1	3195	271	0	0
T2	107248	773968	0	0
T3	2343	178	0	0
T4	260719	140912	0	0
T5	48237	13905	0	0
T9	4629	218	0	0
T12	3575	189	0	0
T13	393400	129432	0	0
T18	1295	32	0	0
T19	27848	11809	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362988880	362141048	0	0
T1	3195	3046	0	0
T2	107248	107243	0	0
T3	2343	2289	0	0
T4	260719	260646	0	0
T5	48237	48153	0	0
T9	4629	4128	0	0
T12	3575	2970	0	0
T13	393400	393388	0	0
T18	1295	1226	0	0
T19	27848	27793	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T13
1	0	Covered	T5,T19,T7

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T19,T7
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T19,T7
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Covered	T2,T4,T13
1	1	Covered	T5,T19,T7

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T19,T7
1	1	Covered	T2,T4,T13

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T7,T8
1	1	Covered	T2,T4,T13

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T19,T7

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T19,T7

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	362988880	362141048	0	0
CheckNGreaterZero_A	991	991	0	0
GntImpliesReady_A	362988880	89231213	0	0
GntImpliesValid_A	362988880	89231213	0	0
GrantKnown_A	362988880	362141048	0	0
IdxKnown_A	362988880	362141048	0	0
IndexIsCorrect_A	362988880	89231213	0	0
NoReadyValidNoGrant_A	362988880	38190292	0	0
Priority_A	362988880	94993066	0	0
ReadyAndValidImplyGrant_A	362988880	89231213	0	0
ReqAndReadyImplyGrant_A	362988880	89231213	0	0
ReqImpliesValid_A	362988880	94993066	0	0
ValidKnown_A	362988880	362141048	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362988880	362141048	0	0
T1	3195	3046	0	0
T2	107248	107243	0	0
T3	2343	2289	0	0
T4	260719	260646	0	0
T5	48237	48153	0	0
T9	4629	4128	0	0
T12	3575	2970	0	0
T13	393400	393388	0	0
T18	1295	1226	0	0
T19	27848	27793	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	991	991	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362988880	89231213	0	0
T2	107248	4020	0	0
T3	2343	0	0	0
T4	260719	99584	0	0
T5	48237	10576	0	0
T6	0	100789	0	0
T7	0	15976	0	0
T8	0	8544	0	0
T9	4629	22	0	0
T12	3575	0	0	0
T13	393400	127897	0	0
T14	1518	0	0	0
T18	1295	0	0	0
T19	27848	7080	0	0
T22	0	79116	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362988880	89231213	0	0
T2	107248	4020	0	0
T3	2343	0	0	0
T4	260719	99584	0	0
T5	48237	10576	0	0
T6	0	100789	0	0
T7	0	15976	0	0
T8	0	8544	0	0
T9	4629	22	0	0
T12	3575	0	0	0
T13	393400	127897	0	0
T14	1518	0	0	0
T18	1295	0	0	0
T19	27848	7080	0	0
T22	0	79116	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362988880	362141048	0	0
T1	3195	3046	0	0
T2	107248	107243	0	0
T3	2343	2289	0	0
T4	260719	260646	0	0
T5	48237	48153	0	0
T9	4629	4128	0	0
T12	3575	2970	0	0
T13	393400	393388	0	0
T18	1295	1226	0	0
T19	27848	27793	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362988880	362141048	0	0
T1	3195	3046	0	0
T2	107248	107243	0	0
T3	2343	2289	0	0
T4	260719	260646	0	0
T5	48237	48153	0	0
T9	4629	4128	0	0
T12	3575	2970	0	0
T13	393400	393388	0	0
T18	1295	1226	0	0
T19	27848	27793	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362988880	89231213	0	0
T2	107248	4020	0	0
T3	2343	0	0	0
T4	260719	99584	0	0
T5	48237	10576	0	0
T6	0	100789	0	0
T7	0	15976	0	0
T8	0	8544	0	0
T9	4629	22	0	0
T12	3575	0	0	0
T13	393400	127897	0	0
T14	1518	0	0	0
T18	1295	0	0	0
T19	27848	7080	0	0
T22	0	79116	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362988880	38190292	0	0
T2	107248	188	0	0
T3	2343	0	0	0
T4	260719	0	0	0
T5	48237	14489	0	0
T7	0	42240	0	0
T8	0	24464	0	0
T9	4629	0	0	0
T12	3575	0	0	0
T13	393400	524288	0	0
T14	1518	0	0	0
T18	1295	0	0	0
T19	27848	708	0	0
T22	0	77259	0	0
T27	0	4059	0	0
T30	0	42427	0	0
T41	0	2	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362988880	94993066	0	0
T2	107248	4020	0	0
T3	2343	0	0	0
T4	260719	99584	0	0
T5	48237	12943	0	0
T6	0	100789	0	0
T7	0	16723	0	0
T8	0	8879	0	0
T9	4629	22	0	0
T12	3575	0	0	0
T13	393400	127897	0	0
T14	1518	0	0	0
T18	1295	0	0	0
T19	27848	7080	0	0
T22	0	90743	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362988880	89231213	0	0
T2	107248	4020	0	0
T3	2343	0	0	0
T4	260719	99584	0	0
T5	48237	10576	0	0
T6	0	100789	0	0
T7	0	15976	0	0
T8	0	8544	0	0
T9	4629	22	0	0
T12	3575	0	0	0
T13	393400	127897	0	0
T14	1518	0	0	0
T18	1295	0	0	0
T19	27848	7080	0	0
T22	0	79116	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362988880	89231213	0	0
T2	107248	4020	0	0
T3	2343	0	0	0
T4	260719	99584	0	0
T5	48237	10576	0	0
T6	0	100789	0	0
T7	0	15976	0	0
T8	0	8544	0	0
T9	4629	22	0	0
T12	3575	0	0	0
T13	393400	127897	0	0
T14	1518	0	0	0
T18	1295	0	0	0
T19	27848	7080	0	0
T22	0	79116	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362988880	94993066	0	0
T2	107248	4020	0	0
T3	2343	0	0	0
T4	260719	99584	0	0
T5	48237	12943	0	0
T6	0	100789	0	0
T7	0	16723	0	0
T8	0	8879	0	0
T9	4629	22	0	0
T12	3575	0	0	0
T13	393400	127897	0	0
T14	1518	0	0	0
T18	1295	0	0	0
T19	27848	7080	0	0
T22	0	90743	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362988880	362141048	0	0
T1	3195	3046	0	0
T2	107248	107243	0	0
T3	2343	2289	0	0
T4	260719	260646	0	0
T5	48237	48153	0	0
T9	4629	4128	0	0
T12	3575	2970	0	0
T13	393400	393388	0	0
T18	1295	1226	0	0
T19	27848	27793	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T13
1	0	Covered	T5,T19,T7

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T19,T7
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T19,T7
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Covered	T2,T4,T13
1	1	Covered	T5,T19,T7

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T19,T7
1	1	Covered	T2,T4,T13

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T7,T8
1	1	Covered	T2,T4,T13

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T19,T7

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T19,T7

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	362988880	362141048	0	0
CheckNGreaterZero_A	991	991	0	0
GntImpliesReady_A	362988880	89231213	0	0
GntImpliesValid_A	362988880	89231213	0	0
GrantKnown_A	362988880	362141048	0	0
IdxKnown_A	362988880	362141048	0	0
IndexIsCorrect_A	362988880	89231213	0	0
NoReadyValidNoGrant_A	362988880	38190292	0	0
Priority_A	362988880	94993066	0	0
ReadyAndValidImplyGrant_A	362988880	89231213	0	0
ReqAndReadyImplyGrant_A	362988880	89231213	0	0
ReqImpliesValid_A	362988880	94993066	0	0
ValidKnown_A	362988880	362141048	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362988880	362141048	0	0
T1	3195	3046	0	0
T2	107248	107243	0	0
T3	2343	2289	0	0
T4	260719	260646	0	0
T5	48237	48153	0	0
T9	4629	4128	0	0
T12	3575	2970	0	0
T13	393400	393388	0	0
T18	1295	1226	0	0
T19	27848	27793	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	991	991	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362988880	89231213	0	0
T2	107248	4020	0	0
T3	2343	0	0	0
T4	260719	99584	0	0
T5	48237	10576	0	0
T6	0	100789	0	0
T7	0	15976	0	0
T8	0	8544	0	0
T9	4629	22	0	0
T12	3575	0	0	0
T13	393400	127897	0	0
T14	1518	0	0	0
T18	1295	0	0	0
T19	27848	7080	0	0
T22	0	79116	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362988880	89231213	0	0
T2	107248	4020	0	0
T3	2343	0	0	0
T4	260719	99584	0	0
T5	48237	10576	0	0
T6	0	100789	0	0
T7	0	15976	0	0
T8	0	8544	0	0
T9	4629	22	0	0
T12	3575	0	0	0
T13	393400	127897	0	0
T14	1518	0	0	0
T18	1295	0	0	0
T19	27848	7080	0	0
T22	0	79116	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362988880	362141048	0	0
T1	3195	3046	0	0
T2	107248	107243	0	0
T3	2343	2289	0	0
T4	260719	260646	0	0
T5	48237	48153	0	0
T9	4629	4128	0	0
T12	3575	2970	0	0
T13	393400	393388	0	0
T18	1295	1226	0	0
T19	27848	27793	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362988880	362141048	0	0
T1	3195	3046	0	0
T2	107248	107243	0	0
T3	2343	2289	0	0
T4	260719	260646	0	0
T5	48237	48153	0	0
T9	4629	4128	0	0
T12	3575	2970	0	0
T13	393400	393388	0	0
T18	1295	1226	0	0
T19	27848	27793	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362988880	89231213	0	0
T2	107248	4020	0	0
T3	2343	0	0	0
T4	260719	99584	0	0
T5	48237	10576	0	0
T6	0	100789	0	0
T7	0	15976	0	0
T8	0	8544	0	0
T9	4629	22	0	0
T12	3575	0	0	0
T13	393400	127897	0	0
T14	1518	0	0	0
T18	1295	0	0	0
T19	27848	7080	0	0
T22	0	79116	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362988880	38190292	0	0
T2	107248	188	0	0
T3	2343	0	0	0
T4	260719	0	0	0
T5	48237	14489	0	0
T7	0	42240	0	0
T8	0	24464	0	0
T9	4629	0	0	0
T12	3575	0	0	0
T13	393400	524288	0	0
T14	1518	0	0	0
T18	1295	0	0	0
T19	27848	708	0	0
T22	0	77259	0	0
T27	0	4059	0	0
T30	0	42427	0	0
T41	0	2	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362988880	94993066	0	0
T2	107248	4020	0	0
T3	2343	0	0	0
T4	260719	99584	0	0
T5	48237	12943	0	0
T6	0	100789	0	0
T7	0	16723	0	0
T8	0	8879	0	0
T9	4629	22	0	0
T12	3575	0	0	0
T13	393400	127897	0	0
T14	1518	0	0	0
T18	1295	0	0	0
T19	27848	7080	0	0
T22	0	90743	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362988880	89231213	0	0
T2	107248	4020	0	0
T3	2343	0	0	0
T4	260719	99584	0	0
T5	48237	10576	0	0
T6	0	100789	0	0
T7	0	15976	0	0
T8	0	8544	0	0
T9	4629	22	0	0
T12	3575	0	0	0
T13	393400	127897	0	0
T14	1518	0	0	0
T18	1295	0	0	0
T19	27848	7080	0	0
T22	0	79116	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362988880	89231213	0	0
T2	107248	4020	0	0
T3	2343	0	0	0
T4	260719	99584	0	0
T5	48237	10576	0	0
T6	0	100789	0	0
T7	0	15976	0	0
T8	0	8544	0	0
T9	4629	22	0	0
T12	3575	0	0	0
T13	393400	127897	0	0
T14	1518	0	0	0
T18	1295	0	0	0
T19	27848	7080	0	0
T22	0	79116	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362988880	94993066	0	0
T2	107248	4020	0	0
T3	2343	0	0	0
T4	260719	99584	0	0
T5	48237	12943	0	0
T6	0	100789	0	0
T7	0	16723	0	0
T8	0	8879	0	0
T9	4629	22	0	0
T12	3575	0	0	0
T13	393400	127897	0	0
T14	1518	0	0	0
T18	1295	0	0	0
T19	27848	7080	0	0
T22	0	90743	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362988880	362141048	0	0
T1	3195	3046	0	0
T2	107248	107243	0	0
T3	2343	2289	0	0
T4	260719	260646	0	0
T5	48237	48153	0	0
T9	4629	4128	0	0
T12	3575	2970	0	0
T13	393400	393388	0	0
T18	1295	1226	0	0
T19	27848	27793	0	0