SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_mem |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
gen_info_types[0].u_info_mem |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
gen_info_types[1].u_info_mem |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
gen_info_types[2].u_info_mem |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_mem |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
gen_info_types[0].u_info_mem |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
gen_info_types[1].u_info_mem |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
gen_info_types[2].u_info_mem |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 7 | 6 | 85.71 | |
CONT_ASSIGN | 42 | 1 | 0 | 0.00 |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 63 | 6 | 6 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
42 | 0 | 1 | |
52 | unreachable | ||
63 | 1 | 1 | |
64 | 1 | 1 | |
65 | 1 | 1 | |
66 | 1 | 1 | |
67 | 1 | 1 | |
==> MISSING_ELSE | |||
72 | 1 | 1 | |
MISSING_ELSE |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 3 | 3 | 100.00 | |
IF | 63 | 3 | 3 | 100.00 |
LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T3 |
0 | - | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataBitsPerMaskCheck_A | 7928 | 7928 | 0 | 0 |
gen_wmask[0].MaskCheck_A | 2147483647 | 172635295 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 7928 | 7928 | 0 | 0 |
T1 | 8 | 8 | 0 | 0 |
T2 | 8 | 8 | 0 | 0 |
T3 | 8 | 8 | 0 | 0 |
T4 | 8 | 8 | 0 | 0 |
T5 | 8 | 8 | 0 | 0 |
T9 | 8 | 8 | 0 | 0 |
T12 | 8 | 8 | 0 | 0 |
T13 | 8 | 8 | 0 | 0 |
T18 | 8 | 8 | 0 | 0 |
T19 | 8 | 8 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2147483647 | 172635295 | 0 | 0 |
T1 | 3195 | 100 | 0 | 0 |
T2 | 428992 | 2213888 | 0 | 0 |
T3 | 9372 | 0 | 0 | 0 |
T4 | 1042876 | 23350 | 0 | 0 |
T5 | 192948 | 0 | 0 | 0 |
T6 | 0 | 54450 | 0 | 0 |
T9 | 18516 | 50 | 0 | 0 |
T12 | 14300 | 9 | 0 | 0 |
T13 | 1573600 | 4874 | 0 | 0 |
T14 | 4554 | 0 | 0 | 0 |
T18 | 5180 | 0 | 0 | 0 |
T19 | 111392 | 5900 | 0 | 0 |
T22 | 0 | 1350 | 0 | 0 |
T24 | 0 | 786432 | 0 | 0 |
T27 | 136405 | 0 | 0 | 0 |
T28 | 1983 | 0 | 0 | 0 |
T45 | 53839 | 0 | 0 | 0 |
T46 | 273027 | 0 | 0 | 0 |
T47 | 0 | 3840 | 0 | 0 |
T48 | 0 | 93480 | 0 | 0 |
T49 | 5174 | 0 | 0 | 0 |
T62 | 0 | 351 | 0 | 0 |
T70 | 0 | 458752 | 0 | 0 |
T71 | 0 | 12800 | 0 | 0 |
T73 | 2954 | 0 | 0 | 0 |
T130 | 1656 | 0 | 0 | 0 |
T131 | 2219 | 0 | 0 | 0 |
T134 | 0 | 150 | 0 | 0 |
T135 | 0 | 458752 | 0 | 0 |
T136 | 0 | 589824 | 0 | 0 |
T137 | 0 | 524288 | 0 | 0 |
T138 | 0 | 65536 | 0 | 0 |
T139 | 0 | 851968 | 0 | 0 |
T140 | 39035 | 0 | 0 | 0 |
T141 | 998 | 0 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 7 | 6 | 85.71 | |
CONT_ASSIGN | 42 | 1 | 0 | 0.00 |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 63 | 6 | 6 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
42 | 0 | 1 | |
52 | unreachable | ||
63 | 1 | 1 | |
64 | 1 | 1 | |
65 | 1 | 1 | |
66 | 1 | 1 | |
67 | 1 | 1 | |
==> MISSING_ELSE | |||
72 | 1 | 1 | |
MISSING_ELSE |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 3 | 3 | 100.00 | |
IF | 63 | 3 | 3 | 100.00 |
LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | 1 | Covered | T2,T4,T13 |
1 | 0 | Covered | T1,T2,T3 |
0 | - | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataBitsPerMaskCheck_A | 991 | 991 | 0 | 0 |
gen_wmask[0].MaskCheck_A | 362988880 | 61251573 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 991 | 991 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 362988880 | 61251573 | 0 | 0 |
T2 | 107248 | 723826 | 0 | 0 |
T3 | 2343 | 0 | 0 | 0 |
T4 | 260719 | 103450 | 0 | 0 |
T5 | 48237 | 0 | 0 | 0 |
T6 | 0 | 29750 | 0 | 0 |
T9 | 4629 | 0 | 0 | 0 |
T12 | 3575 | 0 | 0 | 0 |
T13 | 393400 | 393216 | 0 | 0 |
T14 | 1518 | 0 | 0 | 0 |
T18 | 1295 | 0 | 0 | 0 |
T19 | 27848 | 3850 | 0 | 0 |
T22 | 0 | 85800 | 0 | 0 |
T27 | 0 | 4192 | 0 | 0 |
T28 | 0 | 506 | 0 | 0 |
T47 | 0 | 2048 | 0 | 0 |
T49 | 0 | 100 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 7 | 6 | 85.71 | |
CONT_ASSIGN | 42 | 1 | 0 | 0.00 |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 63 | 6 | 6 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
42 | 0 | 1 | |
52 | unreachable | ||
63 | 1 | 1 | |
64 | 1 | 1 | |
65 | 1 | 1 | |
66 | 1 | 1 | |
67 | 1 | 1 | |
==> MISSING_ELSE | |||
72 | 1 | 1 | |
MISSING_ELSE |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 3 | 3 | 100.00 | |
IF | 63 | 3 | 3 | 100.00 |
LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T3 |
0 | - | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataBitsPerMaskCheck_A | 991 | 991 | 0 | 0 |
gen_wmask[0].MaskCheck_A | 362988880 | 21695241 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 991 | 991 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 362988880 | 21695241 | 0 | 0 |
T1 | 3195 | 100 | 0 | 0 |
T2 | 107248 | 772096 | 0 | 0 |
T3 | 2343 | 0 | 0 | 0 |
T4 | 260719 | 21750 | 0 | 0 |
T5 | 48237 | 0 | 0 | 0 |
T6 | 0 | 52950 | 0 | 0 |
T9 | 4629 | 50 | 0 | 0 |
T12 | 3575 | 9 | 0 | 0 |
T13 | 393400 | 4874 | 0 | 0 |
T18 | 1295 | 0 | 0 | 0 |
T19 | 27848 | 5900 | 0 | 0 |
T47 | 0 | 3840 | 0 | 0 |
T48 | 0 | 93480 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 7 | 6 | 85.71 | |
CONT_ASSIGN | 42 | 1 | 0 | 0.00 |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 63 | 6 | 6 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
42 | 0 | 1 | |
52 | unreachable | ||
63 | 1 | 1 | |
64 | 1 | 1 | |
65 | 1 | 1 | |
66 | 1 | 1 | |
67 | 1 | 1 | |
==> MISSING_ELSE | |||
72 | 1 | 1 | |
MISSING_ELSE |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 3 | 3 | 100.00 | |
IF | 63 | 3 | 3 | 100.00 |
LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | 1 | Covered | T2,T24,T71 |
1 | 0 | Covered | T5,T7,T8 |
0 | - | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataBitsPerMaskCheck_A | 991 | 991 | 0 | 0 |
gen_wmask[0].MaskCheck_A | 362988880 | 5059423 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 991 | 991 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 362988880 | 5059423 | 0 | 0 |
T2 | 107248 | 720896 | 0 | 0 |
T3 | 2343 | 0 | 0 | 0 |
T4 | 260719 | 0 | 0 | 0 |
T5 | 48237 | 0 | 0 | 0 |
T9 | 4629 | 0 | 0 | 0 |
T12 | 3575 | 0 | 0 | 0 |
T13 | 393400 | 0 | 0 | 0 |
T14 | 1518 | 0 | 0 | 0 |
T18 | 1295 | 0 | 0 | 0 |
T19 | 27848 | 0 | 0 | 0 |
T24 | 0 | 393216 | 0 | 0 |
T62 | 0 | 351 | 0 | 0 |
T70 | 0 | 458752 | 0 | 0 |
T71 | 0 | 12800 | 0 | 0 |
T135 | 0 | 458752 | 0 | 0 |
T136 | 0 | 589824 | 0 | 0 |
T137 | 0 | 524288 | 0 | 0 |
T138 | 0 | 65536 | 0 | 0 |
T139 | 0 | 851968 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 7 | 6 | 85.71 | |
CONT_ASSIGN | 42 | 1 | 0 | 0.00 |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 63 | 6 | 6 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
42 | 0 | 1 | |
52 | unreachable | ||
63 | 1 | 1 | |
64 | 1 | 1 | |
65 | 1 | 1 | |
66 | 1 | 1 | |
67 | 1 | 1 | |
==> MISSING_ELSE | |||
72 | 1 | 1 | |
MISSING_ELSE |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 3 | 3 | 100.00 | |
IF | 63 | 3 | 3 | 100.00 |
LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | 1 | Covered | T2,T4,T6 |
1 | 0 | Covered | T1,T4,T5 |
0 | - | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataBitsPerMaskCheck_A | 991 | 991 | 0 | 0 |
gen_wmask[0].MaskCheck_A | 362988880 | 5625120 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 991 | 991 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 362988880 | 5625120 | 0 | 0 |
T2 | 107248 | 720896 | 0 | 0 |
T3 | 2343 | 0 | 0 | 0 |
T4 | 260719 | 1600 | 0 | 0 |
T5 | 48237 | 0 | 0 | 0 |
T6 | 0 | 1500 | 0 | 0 |
T9 | 4629 | 0 | 0 | 0 |
T12 | 3575 | 0 | 0 | 0 |
T13 | 393400 | 0 | 0 | 0 |
T14 | 1518 | 0 | 0 | 0 |
T18 | 1295 | 0 | 0 | 0 |
T19 | 27848 | 0 | 0 | 0 |
T22 | 0 | 1350 | 0 | 0 |
T24 | 0 | 393216 | 0 | 0 |
T39 | 0 | 1150 | 0 | 0 |
T60 | 0 | 176000 | 0 | 0 |
T126 | 0 | 550 | 0 | 0 |
T134 | 0 | 150 | 0 | 0 |
T142 | 0 | 650 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 7 | 6 | 85.71 | |
CONT_ASSIGN | 42 | 1 | 0 | 0.00 |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 63 | 6 | 6 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
42 | 0 | 1 | |
52 | unreachable | ||
63 | 1 | 1 | |
64 | 1 | 1 | |
65 | 1 | 1 | |
66 | 1 | 1 | |
67 | 1 | 1 | |
==> MISSING_ELSE | |||
72 | 1 | 1 | |
MISSING_ELSE |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 3 | 3 | 100.00 | |
IF | 63 | 3 | 3 | 100.00 |
LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | 1 | Covered | T2,T4,T13 |
1 | 0 | Covered | T2,T4,T13 |
0 | - | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataBitsPerMaskCheck_A | 991 | 991 | 0 | 0 |
gen_wmask[0].MaskCheck_A | 362988880 | 62374598 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 991 | 991 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 362988880 | 62374598 | 0 | 0 |
T2 | 107248 | 4230 | 0 | 0 |
T3 | 2343 | 0 | 0 | 0 |
T4 | 260719 | 89700 | 0 | 0 |
T5 | 48237 | 0 | 0 | 0 |
T6 | 0 | 89800 | 0 | 0 |
T9 | 4629 | 50 | 0 | 0 |
T12 | 3575 | 0 | 0 | 0 |
T13 | 393400 | 393216 | 0 | 0 |
T14 | 1518 | 0 | 0 | 0 |
T18 | 1295 | 0 | 0 | 0 |
T19 | 27848 | 5900 | 0 | 0 |
T22 | 0 | 64850 | 0 | 0 |
T27 | 0 | 3374 | 0 | 0 |
T46 | 0 | 33550 | 0 | 0 |
T73 | 0 | 150 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 7 | 6 | 85.71 | |
CONT_ASSIGN | 42 | 1 | 0 | 0.00 |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 63 | 6 | 6 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
42 | 0 | 1 | |
52 | unreachable | ||
63 | 1 | 1 | |
64 | 1 | 1 | |
65 | 1 | 1 | |
66 | 1 | 1 | |
67 | 1 | 1 | |
==> MISSING_ELSE | |||
72 | 1 | 1 | |
MISSING_ELSE |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 3 | 3 | 100.00 | |
IF | 63 | 3 | 3 | 100.00 |
LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | 1 | Covered | T27,T23,T24 |
1 | 0 | Covered | T27,T73,T23 |
0 | - | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataBitsPerMaskCheck_A | 991 | 991 | 0 | 0 |
gen_wmask[0].MaskCheck_A | 362988880 | 6226416 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 991 | 991 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 362988880 | 6226416 | 0 | 0 |
T23 | 0 | 746496 | 0 | 0 |
T24 | 0 | 391680 | 0 | 0 |
T27 | 136405 | 25600 | 0 | 0 |
T28 | 1983 | 0 | 0 | 0 |
T35 | 0 | 600 | 0 | 0 |
T45 | 53839 | 0 | 0 | 0 |
T46 | 273027 | 0 | 0 | 0 |
T49 | 5174 | 0 | 0 | 0 |
T73 | 2954 | 0 | 0 | 0 |
T75 | 0 | 400 | 0 | 0 |
T76 | 0 | 50 | 0 | 0 |
T77 | 0 | 200 | 0 | 0 |
T130 | 1656 | 0 | 0 | 0 |
T131 | 2219 | 0 | 0 | 0 |
T140 | 39035 | 0 | 0 | 0 |
T141 | 998 | 0 | 0 | 0 |
T143 | 0 | 100 | 0 | 0 |
T144 | 0 | 606 | 0 | 0 |
T145 | 0 | 556 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 7 | 6 | 85.71 | |
CONT_ASSIGN | 42 | 1 | 0 | 0.00 |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 63 | 6 | 6 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
42 | 0 | 1 | |
52 | unreachable | ||
63 | 1 | 1 | |
64 | 1 | 1 | |
65 | 1 | 1 | |
66 | 1 | 1 | |
67 | 1 | 1 | |
==> MISSING_ELSE | |||
72 | 1 | 1 | |
MISSING_ELSE |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 3 | 3 | 100.00 | |
IF | 63 | 3 | 3 | 100.00 |
LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | 1 | Covered | T23,T24,T74 |
1 | 0 | Covered | T77,T146,T147 |
0 | - | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataBitsPerMaskCheck_A | 991 | 991 | 0 | 0 |
gen_wmask[0].MaskCheck_A | 362988880 | 5191812 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 991 | 991 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 362988880 | 5191812 | 0 | 0 |
T20 | 127637 | 0 | 0 | 0 |
T21 | 1381 | 0 | 0 | 0 |
T23 | 109364 | 720896 | 0 | 0 |
T24 | 117667 | 327680 | 0 | 0 |
T63 | 4202 | 0 | 0 | 0 |
T70 | 0 | 327680 | 0 | 0 |
T74 | 0 | 786432 | 0 | 0 |
T120 | 401549 | 0 | 0 | 0 |
T122 | 122056 | 0 | 0 | 0 |
T135 | 0 | 196608 | 0 | 0 |
T136 | 0 | 720896 | 0 | 0 |
T148 | 0 | 720896 | 0 | 0 |
T149 | 0 | 556 | 0 | 0 |
T150 | 0 | 458752 | 0 | 0 |
T151 | 0 | 589824 | 0 | 0 |
T152 | 1869 | 0 | 0 | 0 |
T153 | 112469 | 0 | 0 | 0 |
T154 | 131095 | 0 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 7 | 6 | 85.71 | |
CONT_ASSIGN | 42 | 1 | 0 | 0.00 |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 63 | 6 | 6 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
42 | 0 | 1 | |
52 | unreachable | ||
63 | 1 | 1 | |
64 | 1 | 1 | |
65 | 1 | 1 | |
66 | 1 | 1 | |
67 | 1 | 1 | |
==> MISSING_ELSE | |||
72 | 1 | 1 | |
MISSING_ELSE |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 3 | 3 | 100.00 | |
IF | 63 | 3 | 3 | 100.00 |
LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | 1 | Covered | T23,T24,T75 |
1 | 0 | Covered | T73,T75,T76 |
0 | - | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataBitsPerMaskCheck_A | 991 | 991 | 0 | 0 |
gen_wmask[0].MaskCheck_A | 362988880 | 5211112 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 991 | 991 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 362988880 | 5211112 | 0 | 0 |
T20 | 127637 | 0 | 0 | 0 |
T21 | 1381 | 0 | 0 | 0 |
T23 | 109364 | 720896 | 0 | 0 |
T24 | 117667 | 327680 | 0 | 0 |
T63 | 4202 | 0 | 0 | 0 |
T70 | 0 | 327680 | 0 | 0 |
T74 | 0 | 786432 | 0 | 0 |
T75 | 0 | 250 | 0 | 0 |
T77 | 0 | 650 | 0 | 0 |
T120 | 401549 | 0 | 0 | 0 |
T122 | 122056 | 0 | 0 | 0 |
T146 | 0 | 250 | 0 | 0 |
T147 | 0 | 200 | 0 | 0 |
T152 | 1869 | 0 | 0 | 0 |
T153 | 112469 | 0 | 0 | 0 |
T154 | 131095 | 0 | 0 | 0 |
T155 | 0 | 300 | 0 | 0 |
T156 | 0 | 556 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |