Module Definition
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Module Instance : tb.dut.u_intr_prog_lvl

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.67 100.00 66.67 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.67 100.00 66.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.22 97.14 92.20 98.44 100.00 98.33 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_intr_prog_empty

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.75 100.00 75.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.75 100.00 75.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.22 97.14 92.20 98.44 100.00 98.33 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_intr_rd_full

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.75 100.00 75.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.75 100.00 75.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.22 97.14 92.20 98.44 100.00 98.33 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_intr_rd_lvl

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.75 100.00 75.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.75 100.00 75.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.22 97.14 92.20 98.44 100.00 98.33 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_intr_op_done

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.75 100.00 75.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.75 100.00 75.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.22 97.14 92.20 98.44 100.00 98.33 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_intr_corr_err

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.75 100.00 75.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.75 100.00 75.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.22 97.14 92.20 98.44 100.00 98.33 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_intr_hw
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5411100.00
ALWAYS8033100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
47 1 1
49 1 1
52 1 1
54 1 1
80 1 1
81 1 1
83 1 1


Cond Coverage for Module : prim_intr_hw
TotalCoveredPercent
Conditions12975.00
Logical12975.00
Non-Logical00
Event00

 LINE       47
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T4
10Not Covered

 LINE       47
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       52
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T4
10CoveredT1,T2,T4

 LINE       83
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01CoveredT1,T7,T47
10CoveredT2,T3,T4
11CoveredT1,T7,T30

Branch Coverage for Module : prim_intr_hw
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 80 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 80 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : prim_intr_hw
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
IntrTKind_A 5946 5946 0 0


IntrTKind_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 5946 5946 0 0
T1 6 6 0 0
T2 6 6 0 0
T3 6 6 0 0
T4 6 6 0 0
T5 6 6 0 0
T9 6 6 0 0
T12 6 6 0 0
T13 6 6 0 0
T18 6 6 0 0
T19 6 6 0 0

Line Coverage for Instance : tb.dut.u_intr_prog_lvl
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5411100.00
ALWAYS8033100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
47 1 1
49 1 1
52 1 1
54 1 1
80 1 1
81 1 1
83 1 1


Cond Coverage for Instance : tb.dut.u_intr_prog_lvl
TotalCoveredPercent
Conditions12866.67
Logical12866.67
Non-Logical00
Event00

 LINE       47
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT120,T60,T121
10Not Covered

 LINE       47
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       52
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT120,T60,T121
10CoveredT120,T60,T121

 LINE       83
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01CoveredT1,T7,T47
10Not Covered
11CoveredT120,T60,T121

Branch Coverage for Instance : tb.dut.u_intr_prog_lvl
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 80 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 80 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_intr_prog_lvl
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
IntrTKind_A 991 991 0 0


IntrTKind_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 991 991 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0

Line Coverage for Instance : tb.dut.u_intr_prog_empty
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5411100.00
ALWAYS8033100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
47 1 1
49 1 1
52 1 1
54 1 1
80 1 1
81 1 1
83 1 1


Cond Coverage for Instance : tb.dut.u_intr_prog_empty
TotalCoveredPercent
Conditions12975.00
Logical12975.00
Non-Logical00
Event00

 LINE       47
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T4
10Not Covered

 LINE       47
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       52
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T4
10CoveredT1,T2,T4

 LINE       83
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01CoveredT1,T7,T47
10CoveredT2,T4,T13
11CoveredT1,T49,T73

Branch Coverage for Instance : tb.dut.u_intr_prog_empty
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 80 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 80 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_intr_prog_empty
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
IntrTKind_A 991 991 0 0


IntrTKind_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 991 991 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0

Line Coverage for Instance : tb.dut.u_intr_rd_full
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5411100.00
ALWAYS8033100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
47 1 1
49 1 1
52 1 1
54 1 1
80 1 1
81 1 1
83 1 1


Cond Coverage for Instance : tb.dut.u_intr_rd_full
TotalCoveredPercent
Conditions12975.00
Logical12975.00
Non-Logical00
Event00

 LINE       47
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T7,T30
10Not Covered

 LINE       47
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       52
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T7,T30
10CoveredT2,T7,T30

 LINE       83
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01CoveredT1,T7,T47
10CoveredT2,T23,T122
11CoveredT7,T30,T59

Branch Coverage for Instance : tb.dut.u_intr_rd_full
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 80 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 80 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_intr_rd_full
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
IntrTKind_A 991 991 0 0


IntrTKind_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 991 991 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0

Line Coverage for Instance : tb.dut.u_intr_rd_lvl
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5411100.00
ALWAYS8033100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
47 1 1
49 1 1
52 1 1
54 1 1
80 1 1
81 1 1
83 1 1


Cond Coverage for Instance : tb.dut.u_intr_rd_lvl
TotalCoveredPercent
Conditions12975.00
Logical12975.00
Non-Logical00
Event00

 LINE       47
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T7,T30
10Not Covered

 LINE       47
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       52
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T7,T30
10CoveredT2,T7,T30

 LINE       83
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01CoveredT1,T7,T47
10CoveredT2,T23,T122
11CoveredT7,T30,T20

Branch Coverage for Instance : tb.dut.u_intr_rd_lvl
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 80 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 80 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_intr_rd_lvl
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
IntrTKind_A 991 991 0 0


IntrTKind_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 991 991 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0

Line Coverage for Instance : tb.dut.u_intr_op_done
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5411100.00
ALWAYS8033100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
47 1 1
49 1 1
52 1 1
54 1 1
80 1 1
81 1 1
83 1 1


Cond Coverage for Instance : tb.dut.u_intr_op_done
TotalCoveredPercent
Conditions12975.00
Logical12975.00
Non-Logical00
Event00

 LINE       47
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       47
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       52
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       83
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01CoveredT1,T7,T47
10CoveredT2,T3,T4
11CoveredT1,T7,T47

Branch Coverage for Instance : tb.dut.u_intr_op_done
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 80 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 80 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_intr_op_done
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
IntrTKind_A 991 991 0 0


IntrTKind_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 991 991 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0

Line Coverage for Instance : tb.dut.u_intr_corr_err
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5411100.00
ALWAYS8033100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
47 1 1
49 1 1
52 1 1
54 1 1
80 1 1
81 1 1
83 1 1


Cond Coverage for Instance : tb.dut.u_intr_corr_err
TotalCoveredPercent
Conditions12975.00
Logical12975.00
Non-Logical00
Event00

 LINE       47
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T3,T19
10Not Covered

 LINE       47
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       52
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T3,T19
10CoveredT1,T3,T19

 LINE       83
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01CoveredT1,T7,T47
10CoveredT3,T19,T8
11CoveredT1,T73,T40

Branch Coverage for Instance : tb.dut.u_intr_corr_err
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 80 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 80 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_intr_corr_err
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
IntrTKind_A 991 991 0 0


IntrTKind_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 991 991 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%