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Module Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 fifo_h


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 fifo_h


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_dfifo[0].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_dfifo[0].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

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Module Instances:
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo
Line Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 365625677 32041553 0 0
DepthKnown_A 365625677 364690923 0 0
RvalidKnown_A 365625677 364690923 0 0
WreadyKnown_A 365625677 364690923 0 0
gen_passthru_fifo.paramCheckPass 1204 1204 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 365625677 32041553 0 0
T1 3195 657 0 0
T2 107248 152950 0 0
T3 2343 539 0 0
T4 260719 129817 0 0
T5 48237 27060 0 0
T9 4629 391 0 0
T12 3575 505 0 0
T13 393400 1512 0 0
T18 1295 20 0 0
T19 27848 12898 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 365625677 364690923 0 0
T1 3195 3046 0 0
T2 107248 107243 0 0
T3 2343 2289 0 0
T4 260719 260646 0 0
T5 48237 48153 0 0
T9 4629 4128 0 0
T12 3575 2970 0 0
T13 393400 393388 0 0
T18 1295 1226 0 0
T19 27848 27793 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 365625677 364690923 0 0
T1 3195 3046 0 0
T2 107248 107243 0 0
T3 2343 2289 0 0
T4 260719 260646 0 0
T5 48237 48153 0 0
T9 4629 4128 0 0
T12 3575 2970 0 0
T13 393400 393388 0 0
T18 1295 1226 0 0
T19 27848 27793 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 365625677 364690923 0 0
T1 3195 3046 0 0
T2 107248 107243 0 0
T3 2343 2289 0 0
T4 260719 260646 0 0
T5 48237 48153 0 0
T9 4629 4128 0 0
T12 3575 2970 0 0
T13 393400 393388 0 0
T18 1295 1226 0 0
T19 27848 27793 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 1204 1204 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 365625677 38486589 0 0
DepthKnown_A 365625677 364690923 0 0
RvalidKnown_A 365625677 364690923 0 0
WreadyKnown_A 365625677 364690923 0 0
gen_passthru_fifo.paramCheckPass 1204 1204 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 365625677 38486589 0 0
T1 3195 657 0 0
T2 107248 152950 0 0
T3 2343 539 0 0
T4 260719 129817 0 0
T5 48237 18489 0 0
T9 4629 387 0 0
T12 3575 505 0 0
T13 393400 1512 0 0
T18 1295 20 0 0
T19 27848 12898 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 365625677 364690923 0 0
T1 3195 3046 0 0
T2 107248 107243 0 0
T3 2343 2289 0 0
T4 260719 260646 0 0
T5 48237 48153 0 0
T9 4629 4128 0 0
T12 3575 2970 0 0
T13 393400 393388 0 0
T18 1295 1226 0 0
T19 27848 27793 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 365625677 364690923 0 0
T1 3195 3046 0 0
T2 107248 107243 0 0
T3 2343 2289 0 0
T4 260719 260646 0 0
T5 48237 48153 0 0
T9 4629 4128 0 0
T12 3575 2970 0 0
T13 393400 393388 0 0
T18 1295 1226 0 0
T19 27848 27793 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 365625677 364690923 0 0
T1 3195 3046 0 0
T2 107248 107243 0 0
T3 2343 2289 0 0
T4 260719 260646 0 0
T5 48237 48153 0 0
T9 4629 4128 0 0
T12 3575 2970 0 0
T13 393400 393388 0 0
T18 1295 1226 0 0
T19 27848 27793 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 1204 1204 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 365625677 5100148 0 0
DepthKnown_A 365625677 364690923 0 0
RvalidKnown_A 365625677 364690923 0 0
WreadyKnown_A 365625677 364690923 0 0
gen_passthru_fifo.paramCheckPass 1204 1204 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 365625677 5100148 0 0
T1 3195 4 0 0
T2 107248 10175 0 0
T3 2343 0 0 0
T4 260719 8451 0 0
T5 48237 0 0 0
T6 0 6618 0 0
T9 4629 31 0 0
T12 3575 0 0 0
T13 393400 0 0 0
T18 1295 0 0 0
T19 27848 762 0 0
T22 0 7440 0 0
T27 0 7497 0 0
T33 0 1936 0 0
T48 0 1640 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 365625677 364690923 0 0
T1 3195 3046 0 0
T2 107248 107243 0 0
T3 2343 2289 0 0
T4 260719 260646 0 0
T5 48237 48153 0 0
T9 4629 4128 0 0
T12 3575 2970 0 0
T13 393400 393388 0 0
T18 1295 1226 0 0
T19 27848 27793 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 365625677 364690923 0 0
T1 3195 3046 0 0
T2 107248 107243 0 0
T3 2343 2289 0 0
T4 260719 260646 0 0
T5 48237 48153 0 0
T9 4629 4128 0 0
T12 3575 2970 0 0
T13 393400 393388 0 0
T18 1295 1226 0 0
T19 27848 27793 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 365625677 364690923 0 0
T1 3195 3046 0 0
T2 107248 107243 0 0
T3 2343 2289 0 0
T4 260719 260646 0 0
T5 48237 48153 0 0
T9 4629 4128 0 0
T12 3575 2970 0 0
T13 393400 393388 0 0
T18 1295 1226 0 0
T19 27848 27793 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 1204 1204 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 365625677 3289927 0 0
DepthKnown_A 365625677 364690923 0 0
RvalidKnown_A 365625677 364690923 0 0
WreadyKnown_A 365625677 364690923 0 0
gen_passthru_fifo.paramCheckPass 1204 1204 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 365625677 3289927 0 0
T1 3195 4 0 0
T2 107248 10175 0 0
T3 2343 0 0 0
T4 260719 8451 0 0
T5 48237 0 0 0
T6 0 6618 0 0
T9 4629 27 0 0
T12 3575 0 0 0
T13 393400 0 0 0
T18 1295 0 0 0
T19 27848 762 0 0
T22 0 7440 0 0
T27 0 7497 0 0
T33 0 8647 0 0
T48 0 1640 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 365625677 364690923 0 0
T1 3195 3046 0 0
T2 107248 107243 0 0
T3 2343 2289 0 0
T4 260719 260646 0 0
T5 48237 48153 0 0
T9 4629 4128 0 0
T12 3575 2970 0 0
T13 393400 393388 0 0
T18 1295 1226 0 0
T19 27848 27793 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 365625677 364690923 0 0
T1 3195 3046 0 0
T2 107248 107243 0 0
T3 2343 2289 0 0
T4 260719 260646 0 0
T5 48237 48153 0 0
T9 4629 4128 0 0
T12 3575 2970 0 0
T13 393400 393388 0 0
T18 1295 1226 0 0
T19 27848 27793 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 365625677 364690923 0 0
T1 3195 3046 0 0
T2 107248 107243 0 0
T3 2343 2289 0 0
T4 260719 260646 0 0
T5 48237 48153 0 0
T9 4629 4128 0 0
T12 3575 2970 0 0
T13 393400 393388 0 0
T18 1295 1226 0 0
T19 27848 27793 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 1204 1204 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0

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