Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	338377	1		T1	2401		T2	4125		T3	1
all_values[1]	338377	1		T1	2401		T2	4125		T3	1
all_values[2]	338377	1		T1	2401		T2	4125		T3	1
all_values[3]	338377	1		T1	2401		T2	4125		T3	1
all_values[4]	338377	1		T1	2401		T2	4125		T3	1
all_values[5]	338377	1		T1	2401		T2	4125		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	10361	1		T1	6		T3	6		T14	6
auto[1]	2019901	1		T1	14400		T2	24750		T6	13656

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1648622	1		T1	11962		T2	19595		T3	6
auto[1]	381640	1		T1	2444		T2	5155		T4	4

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	1291	1		T1	1		T3	1		T14	1
all_values[0]	auto[0]	auto[1]	432	1		T4	1		T15	1		T25	1
all_values[0]	auto[1]	auto[0]	272777	1		T1	2400		T2	1		T6	2276
all_values[0]	auto[1]	auto[1]	63877	1		T2	4124		T109	4324		T78	2215
all_values[1]	auto[0]	auto[0]	1671	1		T1	1		T3	1		T14	1
all_values[1]	auto[0]	auto[1]	50	1		T348	1		T349	2		T350	1
all_values[1]	auto[1]	auto[0]	278260	1		T1	2400		T2	4125		T6	2276
all_values[1]	auto[1]	auto[1]	58396	1		T78	3617		T79	4933		T80	3644
all_values[2]	auto[0]	auto[0]	1594	1		T1	1		T3	1		T14	1
all_values[2]	auto[0]	auto[1]	126	1		T4	1		T15	1		T81	1
all_values[2]	auto[1]	auto[0]	329109	1		T1	2375		T2	4125		T6	1493
all_values[2]	auto[1]	auto[1]	7548	1		T1	25		T6	783		T7	842
all_values[3]	auto[0]	auto[0]	1580	1		T1	1		T3	1		T14	1
all_values[3]	auto[0]	auto[1]	162	1		T4	1		T15	1		T81	1
all_values[3]	auto[1]	auto[0]	185118	1		T1	1167		T2	4125		T6	1084
all_values[3]	auto[1]	auto[1]	151517	1		T1	1233		T6	1192		T7	1061
all_values[4]	auto[0]	auto[0]	1181	1		T1	1		T3	1		T14	1
all_values[4]	auto[0]	auto[1]	542	1		T4	1		T15	1		T25	1
all_values[4]	auto[1]	auto[0]	237886	1		T1	1214		T2	3094		T6	1140
all_values[4]	auto[1]	auto[1]	98768	1		T1	1186		T2	1031		T6	1136
all_values[5]	auto[0]	auto[0]	1568	1		T1	1		T3	1		T14	1
all_values[5]	auto[0]	auto[1]	164	1		T48	1		T39	1		T40	1
all_values[5]	auto[1]	auto[0]	336587	1		T1	2400		T2	4125		T6	2276
all_values[5]	auto[1]	auto[1]	58	1		T240	1		T241	2		T242	2