| | | | | | | |
tb.dut.FifoDepthCheck_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.FlashAddrKnown_A
| 0 | 0 | 423189654 | 298797156 | 0 | 0 |
|
tb.dut.FlashAddrKnown_AKnownEnable
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.FlashKnownO_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.FlashProgKnown_A
| 0 | 0 | 423189654 | 184235401 | 0 | 0 |
|
tb.dut.FlashProgKnown_AKnownEnable
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.FpvSecCmAddrCntAlertCheck_A
| 0 | 0 | 423189654 | 50 | 0 | 0 |
|
tb.dut.FpvSecCmArbFsmCheck_A
| 0 | 0 | 423189654 | 50 | 0 | 0 |
|
tb.dut.FpvSecCmLcCtrlFsmCheck_A
| 0 | 0 | 423189654 | 50 | 0 | 0 |
|
tb.dut.FpvSecCmLcCtrlRmaFsmCheck_A
| 0 | 0 | 423189654 | 50 | 0 | 0 |
|
tb.dut.FpvSecCmPageCntAlertCheck_A
| 0 | 0 | 423189654 | 50 | 0 | 0 |
|
tb.dut.FpvSecCmProgCnt_A
| 0 | 0 | 423189654 | 50 | 0 | 0 |
|
tb.dut.FpvSecCmRdCnt_A
| 0 | 0 | 423189654 | 50 | 0 | 0 |
|
tb.dut.FpvSecCmRdFifoRptrCheck_A
| 0 | 0 | 423189654 | 50 | 0 | 0 |
|
tb.dut.FpvSecCmRdFifoWptrCheck_A
| 0 | 0 | 423189654 | 50 | 0 | 0 |
|
tb.dut.FpvSecCmRegWeOnehotCheck_A
| 0 | 0 | 423189654 | 50 | 0 | 0 |
|
tb.dut.FpvSecCmSeedCntAlertCheck_A
| 0 | 0 | 423189654 | 50 | 0 | 0 |
|
tb.dut.FpvSecCmTlLcGateFsm_A
| 0 | 0 | 423189654 | 50 | 0 | 0 |
|
tb.dut.FpvSecCmTlProgLcGateFsm_A
| 0 | 0 | 423189654 | 50 | 0 | 0 |
|
tb.dut.FpvSecCmWipeIdx_A
| 0 | 0 | 423189654 | 50 | 0 | 0 |
|
tb.dut.FpvSecCmWordCntAlertCheck_A
| 0 | 0 | 423189654 | 50 | 0 | 0 |
|
tb.dut.IntrErrO_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.IntrOpDoneKnownO_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.IntrProgEmptyKnownO_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.IntrProgLvlKnownO_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.IntrProgRdFullKnownO_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.IntrRdLvlKnownO_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.MemRspPayLoad_A
| 0 | 0 | 423189654 | 6162834 | 0 | 0 |
|
tb.dut.MemRspPayLoad_AKnownEnable
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.MemTlAReadyKnownO_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.MemTlDValidKnownO_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.PrimRspPayLoad_AKnownEnable
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.PrimTlAReadyKnownO_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.PrimTlDValidKnownO_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.RspPayLoad_A
| 0 | 0 | 423002885 | 38212475 | 0 | 0 |
|
tb.dut.RspPayLoad_AKnownEnable
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.TdoEnIsOne_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.TdoKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.TlAReadyKnownO_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.TlDValidKnownO_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.TlulOOBAddrErr_A
| 0 | 0 | 425753398 | 3450 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.addr_rd_A
| 0 | 0 | 425753398 | 2045 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_0_rd_A
| 0 | 0 | 425753398 | 4004 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_1_rd_A
| 0 | 0 | 425753398 | 4127 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_2_rd_A
| 0 | 0 | 425753398 | 3415 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_3_rd_A
| 0 | 0 | 425753398 | 4431 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_4_rd_A
| 0 | 0 | 425753398 | 3775 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_5_rd_A
| 0 | 0 | 425753398 | 3631 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_6_rd_A
| 0 | 0 | 425753398 | 3971 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_7_rd_A
| 0 | 0 | 425753398 | 3593 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_8_rd_A
| 0 | 0 | 425753398 | 3990 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_9_rd_A
| 0 | 0 | 425753398 | 4048 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_0_rd_A
| 0 | 0 | 425753398 | 1295 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_1_rd_A
| 0 | 0 | 425753398 | 1268 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_2_rd_A
| 0 | 0 | 425753398 | 1614 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_3_rd_A
| 0 | 0 | 425753398 | 2043 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_4_rd_A
| 0 | 0 | 425753398 | 2117 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_5_rd_A
| 0 | 0 | 425753398 | 2099 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_6_rd_A
| 0 | 0 | 425753398 | 1595 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_7_rd_A
| 0 | 0 | 425753398 | 1817 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_8_rd_A
| 0 | 0 | 425753398 | 2071 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_9_rd_A
| 0 | 0 | 425753398 | 1627 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.bank0_info1_page_cfg_rd_A
| 0 | 0 | 425753398 | 4452 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.bank0_info1_regwen_rd_A
| 0 | 0 | 425753398 | 1521 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_page_cfg_0_rd_A
| 0 | 0 | 425753398 | 3510 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_page_cfg_1_rd_A
| 0 | 0 | 425753398 | 3860 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_regwen_0_rd_A
| 0 | 0 | 425753398 | 1273 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_regwen_1_rd_A
| 0 | 0 | 425753398 | 1932 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_0_rd_A
| 0 | 0 | 425753398 | 4153 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_1_rd_A
| 0 | 0 | 425753398 | 3713 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_2_rd_A
| 0 | 0 | 425753398 | 3927 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_3_rd_A
| 0 | 0 | 425753398 | 4344 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_4_rd_A
| 0 | 0 | 425753398 | 3945 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_5_rd_A
| 0 | 0 | 425753398 | 3923 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_6_rd_A
| 0 | 0 | 425753398 | 3673 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_7_rd_A
| 0 | 0 | 425753398 | 4171 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_8_rd_A
| 0 | 0 | 425753398 | 4271 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_9_rd_A
| 0 | 0 | 425753398 | 3319 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_0_rd_A
| 0 | 0 | 425753398 | 1535 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_1_rd_A
| 0 | 0 | 425753398 | 1826 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_2_rd_A
| 0 | 0 | 425753398 | 1311 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_3_rd_A
| 0 | 0 | 425753398 | 1825 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_4_rd_A
| 0 | 0 | 425753398 | 2037 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_5_rd_A
| 0 | 0 | 425753398 | 1123 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_6_rd_A
| 0 | 0 | 425753398 | 2109 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_7_rd_A
| 0 | 0 | 425753398 | 1994 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_8_rd_A
| 0 | 0 | 425753398 | 1788 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_9_rd_A
| 0 | 0 | 425753398 | 2066 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.bank1_info1_page_cfg_rd_A
| 0 | 0 | 425753398 | 3928 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.bank1_info1_regwen_rd_A
| 0 | 0 | 425753398 | 2097 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_page_cfg_0_rd_A
| 0 | 0 | 425753398 | 4035 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_page_cfg_1_rd_A
| 0 | 0 | 425753398 | 4101 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_regwen_0_rd_A
| 0 | 0 | 425753398 | 1906 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_regwen_1_rd_A
| 0 | 0 | 425753398 | 1413 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.bank_cfg_regwen_rd_A
| 0 | 0 | 425753398 | 1919 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.default_region_rd_A
| 0 | 0 | 425753398 | 3770 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.exec_rd_A
| 0 | 0 | 425753398 | 2052 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.fifo_lvl_rd_A
| 0 | 0 | 425753398 | 2320 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.fifo_rst_rd_A
| 0 | 0 | 425753398 | 1612 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.hw_info_cfg_override_rd_A
| 0 | 0 | 425753398 | 1738 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.intr_enable_rd_A
| 0 | 0 | 425753398 | 2874 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.mp_region_0_rd_A
| 0 | 0 | 425753398 | 1921 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.mp_region_1_rd_A
| 0 | 0 | 425753398 | 2659 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.mp_region_2_rd_A
| 0 | 0 | 425753398 | 2005 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.mp_region_3_rd_A
| 0 | 0 | 425753398 | 1734 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.mp_region_4_rd_A
| 0 | 0 | 425753398 | 2146 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.mp_region_5_rd_A
| 0 | 0 | 425753398 | 2006 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.mp_region_6_rd_A
| 0 | 0 | 425753398 | 2093 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.mp_region_7_rd_A
| 0 | 0 | 425753398 | 2061 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_0_rd_A
| 0 | 0 | 425753398 | 3898 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_1_rd_A
| 0 | 0 | 425753398 | 3346 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_2_rd_A
| 0 | 0 | 425753398 | 4328 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_3_rd_A
| 0 | 0 | 425753398 | 3946 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_4_rd_A
| 0 | 0 | 425753398 | 4101 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_5_rd_A
| 0 | 0 | 425753398 | 3496 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_6_rd_A
| 0 | 0 | 425753398 | 3924 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_7_rd_A
| 0 | 0 | 425753398 | 3819 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.phy_alert_cfg_rd_A
| 0 | 0 | 425753398 | 1091 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_0_rd_A
| 0 | 0 | 425753398 | 1997 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_1_rd_A
| 0 | 0 | 425753398 | 2082 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_2_rd_A
| 0 | 0 | 425753398 | 1317 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_3_rd_A
| 0 | 0 | 425753398 | 1663 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_4_rd_A
| 0 | 0 | 425753398 | 1270 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_5_rd_A
| 0 | 0 | 425753398 | 2094 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_6_rd_A
| 0 | 0 | 425753398 | 2012 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_7_rd_A
| 0 | 0 | 425753398 | 2125 | 0 | 0 |
|
tb.dut.flash_ctrl_core_csr_assert.scratch_rd_A
| 0 | 0 | 425753398 | 1829 | 0 | 0 |
|
tb.dut.gen_phy_assertions[0].FpvSecCmPhyFsmCheck_A
| 0 | 0 | 423189654 | 50 | 0 | 0 |
|
tb.dut.gen_phy_assertions[0].FpvSecCmPhyProgFsmCheck_A
| 0 | 0 | 423189654 | 50 | 0 | 0 |
|
tb.dut.gen_phy_assertions[1].FpvSecCmPhyFsmCheck_A
| 0 | 0 | 423189654 | 50 | 0 | 0 |
|
tb.dut.gen_phy_assertions[1].FpvSecCmPhyProgFsmCheck_A
| 0 | 0 | 423189654 | 50 | 0 | 0 |
|
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyHostCnt_A
| 0 | 0 | 423189654 | 50 | 0 | 0 |
|
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdDataFifoRPtr_A
| 0 | 0 | 423189654 | 50 | 0 | 0 |
|
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdDataFifoWPtr_A
| 0 | 0 | 423189654 | 50 | 0 | 0 |
|
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdRspFifoRPtr_A
| 0 | 0 | 423189654 | 50 | 0 | 0 |
|
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdRspFifoWPtr_A
| 0 | 0 | 423189654 | 50 | 0 | 0 |
|
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRspFifoRPtr_A
| 0 | 0 | 423189654 | 50 | 0 | 0 |
|
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRspFifoWPtr_A
| 0 | 0 | 423189654 | 50 | 0 | 0 |
|
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyHostCnt_A
| 0 | 0 | 423189654 | 50 | 0 | 0 |
|
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdDataFifoRPtr_A
| 0 | 0 | 423189654 | 50 | 0 | 0 |
|
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdDataFifoWPtr_A
| 0 | 0 | 423189654 | 50 | 0 | 0 |
|
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdRspFifoRPtr_A
| 0 | 0 | 423189654 | 50 | 0 | 0 |
|
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdRspFifoWPtr_A
| 0 | 0 | 423189654 | 50 | 0 | 0 |
|
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRspFifoRPtr_A
| 0 | 0 | 423189654 | 50 | 0 | 0 |
|
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRspFifoWPtr_A
| 0 | 0 | 423189654 | 50 | 0 | 0 |
|
tb.dut.gen_reg_we_assert_generic.FpvSecCmPrimRegWeOnehotCheck_A
| 0 | 0 | 423189654 | 26 | 0 | 0 |
|
tb.dut.tlul_assert_device.aKnown_A
| 0 | 0 | 425753375 | 36292630 | 0 | 0 |
|
tb.dut.tlul_assert_device.aKnown_AKnownEnable
| 0 | 0 | 425753375 | 424847601 | 0 | 0 |
|
tb.dut.tlul_assert_device.aReadyKnown_A
| 0 | 0 | 425753375 | 424847601 | 0 | 0 |
|
tb.dut.tlul_assert_device.dKnown_A
| 0 | 0 | 425753375 | 39038805 | 0 | 0 |
|
tb.dut.tlul_assert_device.dKnown_AKnownEnable
| 0 | 0 | 425753375 | 424847601 | 0 | 0 |
|
tb.dut.tlul_assert_device.dReadyKnown_A
| 0 | 0 | 425753375 | 424847601 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[102].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[103].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[104].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[105].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[106].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[107].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[108].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[109].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[10].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[110].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[111].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[112].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[113].noOutstandingReqsAtEndOfSim_A
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tb.dut.tlul_assert_device.gen_assert_final[250].noOutstandingReqsAtEndOfSim_A
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tb.dut.tlul_assert_device.gen_assert_final[251].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[252].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[253].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[254].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[255].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[25].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[26].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[27].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[28].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[29].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[2].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[30].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[31].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[32].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[33].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[34].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[35].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[36].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[37].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[38].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[39].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[3].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[40].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[41].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[42].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[43].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[44].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[45].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[46].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[47].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[48].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[49].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[4].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[50].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[51].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[52].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[53].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[54].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[55].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[56].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[57].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[58].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[59].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[5].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[60].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[61].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[62].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[63].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[64].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[65].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[66].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[67].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[68].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[69].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[6].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[70].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[71].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[72].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[73].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[74].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[75].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[76].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[77].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[78].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[79].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[7].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[80].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[81].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[82].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[83].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[84].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[85].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[86].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[87].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[88].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[89].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[8].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[90].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[91].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[92].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[93].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[94].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[95].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[96].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[97].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[98].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[99].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[9].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.aDataKnown_M
| 0 | 0 | 425754081 | 9969788 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.addrSizeAlignedErr_A
| 0 | 0 | 425753375 | 5591 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.contigMask_M
| 0 | 0 | 425754081 | 31070253 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.dDataKnown_A
| 0 | 0 | 425567312 | 32103922 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.legalAOpcodeErr_A
| 0 | 0 | 425753375 | 4603 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.legalAParam_M
| 0 | 0 | 425754081 | 36292637 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.legalDParam_A
| 0 | 0 | 425754081 | 39038815 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.pendingReqPerSrc_M
| 0 | 0 | 425754081 | 36292637 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.respMustHaveReq_A
| 0 | 0 | 425754081 | 39038815 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.respOpcode_A
| 0 | 0 | 425754081 | 39038815 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.respSzEqReqSz_A
| 0 | 0 | 425754081 | 39038815 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.sizeGTEMaskErr_A
| 0 | 0 | 425753375 | 4235 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.sizeMatchesMaskErr_A
| 0 | 0 | 425753375 | 4686 | 0 | 0 |
|
tb.dut.tlul_assert_device.p_dbw.TlDbw_A
| 0 | 0 | 1274 | 1274 | 0 | 0 |
|
tb.dut.u_ctrl_arb.u_state_regs.AssertConnected_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_ctrl_arb.u_state_regs_A
| 0 | 0 | 423189677 | 422369935 | 0 | 0 |
|
tb.dut.u_disable_buf.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_disable_buf.OutputsKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_disable_buf.gen_no_flops.OutputDelay_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.ArbCntMax_A
| 0 | 0 | 423189654 | 2139443 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.CtrlPrio_A
| 0 | 0 | 423189654 | 2139443 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.HostTransIdleChk_A
| 0 | 0 | 423189654 | 23259109 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.NoRemainder_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.OneHotReqs_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.Pow2Multiple_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.RdTxnCheck_A
| 0 | 0 | 423002885 | 422183143 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.OneDonePerTxn_A
| 0 | 0 | 423189654 | 1215954 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.PostPackRule_A
| 0 | 0 | 423189654 | 16894 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.PrePackRule_A
| 0 | 0 | 423189654 | 8210 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.WidthCheck_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.u_state_regs.AssertConnected_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.u_state_regs_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.OutputsKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_no_flops.OutputDelay_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.CheckHotOne_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.CheckNGreaterZero_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.GntImpliesReady_A
| 0 | 0 | 423189654 | 120868503 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.GntImpliesValid_A
| 0 | 0 | 423189654 | 120868503 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.GrantKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.IdxKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.IndexIsCorrect_A
| 0 | 0 | 423189654 | 120868503 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.NoReadyValidNoGrant_A
| 0 | 0 | 423189654 | 46451417 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.Priority_A
| 0 | 0 | 423189654 | 126931369 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.ReadyAndValidImplyGrant_A
| 0 | 0 | 423189654 | 120868503 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.ReqAndReadyImplyGrant_A
| 0 | 0 | 423189654 | 120868503 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.ReqImpliesValid_A
| 0 | 0 | 423189654 | 126931369 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.ValidKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.CheckHotOne_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.CheckNGreaterZero_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.GntImpliesReady_A
| 0 | 0 | 423189654 | 120650659 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.GntImpliesValid_A
| 0 | 0 | 423189654 | 120650659 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.GrantKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.IdxKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.IndexIsCorrect_A
| 0 | 0 | 423189654 | 120650659 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.NoReadyValidNoGrant_A
| 0 | 0 | 423189654 | 46451419 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.Priority_A
| 0 | 0 | 423189654 | 126713523 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.ReadyAndValidImplyGrant_A
| 0 | 0 | 423189654 | 120650659 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.ReqAndReadyImplyGrant_A
| 0 | 0 | 423189654 | 120650659 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.ReqImpliesValid_A
| 0 | 0 | 423189654 | 126713523 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.ValidKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.BufferMatchEcc_A
| 0 | 0 | 423189654 | 831174 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.ExclusiveOps_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.ExclusiveProgHazard_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.ExclusiveState_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.ForwardCheck_A
| 0 | 0 | 423189654 | 2078133 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.IdleCheck_A
| 0 | 0 | 423189654 | 53358807 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.MaxBufs_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.OneHotAlloc_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.OneHotMatch_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.OneHotRspMatch_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.OneHotUpdate_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf.AllocCheck_A
| 0 | 0 | 423189654 | 724164 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf.UpdateCheck_A
| 0 | 0 | 423189654 | 724164 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf.AllocCheck_A
| 0 | 0 | 423189654 | 723748 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf.UpdateCheck_A
| 0 | 0 | 423189654 | 723746 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf.AllocCheck_A
| 0 | 0 | 423189654 | 723779 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf.UpdateCheck_A
| 0 | 0 | 423189654 | 723778 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf.AllocCheck_A
| 0 | 0 | 423189654 | 723356 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf.UpdateCheck_A
| 0 | 0 | 423189654 | 723356 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage.DataKnown_A
| 0 | 0 | 423189654 | 13150779 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage.DepthKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage.RvalidKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage.WreadyKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage.gen_normal_fifo.depthShallNotExceedParamDepth
| 0 | 0 | 423189654 | 13150779 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep.BufferDecrUnderRun_A
| 0 | 0 | 423189654 | 3726218 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep.BufferDepRsp_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep.BufferIncrOverFlow_A
| 0 | 0 | 423189654 | 3726223 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep.DepBufferRspOrder_A
| 0 | 0 | 423189656 | 8844041 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage.DataKnown_A
| 0 | 0 | 423002885 | 13942076 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage.DepthKnown_A
| 0 | 0 | 423002885 | 422183143 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage.RvalidKnown_A
| 0 | 0 | 423002885 | 422183143 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage.WreadyKnown_A
| 0 | 0 | 423002885 | 422183143 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage.gen_normal_fifo.depthShallNotExceedParamDepth
| 0 | 0 | 423002885 | 13942076 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo.DataKnown_A
| 0 | 0 | 423002885 | 53352616 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo.DepthKnown_A
| 0 | 0 | 423002885 | 422183143 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo.RvalidKnown_A
| 0 | 0 | 423002885 | 422183143 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo.WreadyKnown_A
| 0 | 0 | 423002885 | 422183143 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo.gen_normal_fifo.depthShallNotExceedParamDepth
| 0 | 0 | 423002885 | 53352616 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.CheckHotOne_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.CheckNGreaterZero_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.GntImpliesReady_A
| 0 | 0 | 423189654 | 2856591 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.GntImpliesValid_A
| 0 | 0 | 423189654 | 2856591 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.GrantKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.IdxKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.IndexIsCorrect_A
| 0 | 0 | 423189654 | 2856591 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.NoReadyValidNoGrant_A
| 0 | 0 | 423189654 | 304986728 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.ReadyAndValidImplyGrant_A
| 0 | 0 | 423189654 | 2856591 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.ReqAndReadyImplyGrant_A
| 0 | 0 | 423189654 | 2856591 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.ReqImpliesValid_A
| 0 | 0 | 423189654 | 112179969 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.RoundRobin_A
| 0 | 0 | 423189654 | 32297 | 0 | 1053 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.ValidKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_scramble.gen_gf_mult.u_mult.IntegerLoops_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_scramble.gen_gf_mult.u_mult.StagePow2_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_state_regs.AssertConnected_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_state_regs_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo.DataKnown_A
| 0 | 0 | 423002885 | 2934376 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo.DepthKnown_A
| 0 | 0 | 423002885 | 422183143 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo.RvalidKnown_A
| 0 | 0 | 423002885 | 422183143 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo.WreadyKnown_A
| 0 | 0 | 423002885 | 422183143 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo.gen_normal_fifo.depthShallNotExceedParamDepth
| 0 | 0 | 423002885 | 2934376 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.ArbCntMax_A
| 0 | 0 | 423189654 | 2327977 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.CtrlPrio_A
| 0 | 0 | 423189654 | 2327977 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.HostTransIdleChk_A
| 0 | 0 | 423189654 | 23384183 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.NoRemainder_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.OneHotReqs_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.Pow2Multiple_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.RdTxnCheck_A
| 0 | 0 | 423002885 | 422183143 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.OneDonePerTxn_A
| 0 | 0 | 423189654 | 1178809 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.PostPackRule_A
| 0 | 0 | 423189654 | 13003 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.PrePackRule_A
| 0 | 0 | 423189654 | 6578 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.WidthCheck_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.u_state_regs.AssertConnected_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.u_state_regs_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.OutputsKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_no_flops.OutputDelay_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.CheckHotOne_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.CheckNGreaterZero_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.GntImpliesReady_A
| 0 | 0 | 423189654 | 100730303 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.GntImpliesValid_A
| 0 | 0 | 423189654 | 100730303 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.GrantKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.IdxKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.IndexIsCorrect_A
| 0 | 0 | 423189654 | 100730303 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.NoReadyValidNoGrant_A
| 0 | 0 | 423189654 | 43633744 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.Priority_A
| 0 | 0 | 423189654 | 106995725 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.ReadyAndValidImplyGrant_A
| 0 | 0 | 423189654 | 100730303 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.ReqAndReadyImplyGrant_A
| 0 | 0 | 423189654 | 100730303 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.ReqImpliesValid_A
| 0 | 0 | 423189654 | 106995725 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.ValidKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.CheckHotOne_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.CheckNGreaterZero_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.GntImpliesReady_A
| 0 | 0 | 423189654 | 100730303 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.GntImpliesValid_A
| 0 | 0 | 423189654 | 100730303 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.GrantKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.IdxKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.IndexIsCorrect_A
| 0 | 0 | 423189654 | 100730303 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.NoReadyValidNoGrant_A
| 0 | 0 | 423189654 | 43633744 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.Priority_A
| 0 | 0 | 423189654 | 106995725 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.ReadyAndValidImplyGrant_A
| 0 | 0 | 423189654 | 100730303 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.ReqAndReadyImplyGrant_A
| 0 | 0 | 423189654 | 100730303 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.ReqImpliesValid_A
| 0 | 0 | 423189654 | 106995725 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.ValidKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.BufferMatchEcc_A
| 0 | 0 | 423189654 | 648599 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.ExclusiveOps_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.ExclusiveProgHazard_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.ExclusiveState_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.ForwardCheck_A
| 0 | 0 | 423189654 | 1763687 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.IdleCheck_A
| 0 | 0 | 423189654 | 50782007 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.MaxBufs_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.OneHotAlloc_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.OneHotMatch_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.OneHotRspMatch_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.OneHotUpdate_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf.AllocCheck_A
| 0 | 0 | 423189654 | 679773 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf.UpdateCheck_A
| 0 | 0 | 423189654 | 679772 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf.AllocCheck_A
| 0 | 0 | 423189654 | 679650 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf.UpdateCheck_A
| 0 | 0 | 423189654 | 679649 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf.AllocCheck_A
| 0 | 0 | 423189654 | 679614 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf.UpdateCheck_A
| 0 | 0 | 423189654 | 679613 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf.AllocCheck_A
| 0 | 0 | 423189654 | 679006 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf.UpdateCheck_A
| 0 | 0 | 423189654 | 679003 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage.DataKnown_A
| 0 | 0 | 423189654 | 11635357 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage.DepthKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage.RvalidKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage.WreadyKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage.gen_normal_fifo.depthShallNotExceedParamDepth
| 0 | 0 | 423189654 | 11635357 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep.BufferDecrUnderRun_A
| 0 | 0 | 423189654 | 3366636 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep.BufferDepRsp_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep.BufferIncrOverFlow_A
| 0 | 0 | 423189654 | 3366643 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep.DepBufferRspOrder_A
| 0 | 0 | 423189658 | 7879834 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage.DataKnown_A
| 0 | 0 | 423002885 | 12690309 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage.DepthKnown_A
| 0 | 0 | 423002885 | 422183143 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage.RvalidKnown_A
| 0 | 0 | 423002885 | 422183143 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage.WreadyKnown_A
| 0 | 0 | 423002885 | 422183143 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage.gen_normal_fifo.depthShallNotExceedParamDepth
| 0 | 0 | 423002885 | 12690309 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo.DataKnown_A
| 0 | 0 | 423002885 | 50777007 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo.DepthKnown_A
| 0 | 0 | 423002885 | 422183143 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo.RvalidKnown_A
| 0 | 0 | 423002885 | 422183143 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo.WreadyKnown_A
| 0 | 0 | 423002885 | 422183143 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo.gen_normal_fifo.depthShallNotExceedParamDepth
| 0 | 0 | 423002885 | 50777007 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.CheckHotOne_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.CheckNGreaterZero_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.GntImpliesReady_A
| 0 | 0 | 423189654 | 2712737 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.GntImpliesValid_A
| 0 | 0 | 423189654 | 2712737 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.GrantKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.IdxKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.IndexIsCorrect_A
| 0 | 0 | 423189654 | 2712737 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.NoReadyValidNoGrant_A
| 0 | 0 | 423189654 | 307772940 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.ReadyAndValidImplyGrant_A
| 0 | 0 | 423189654 | 2712737 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.ReqAndReadyImplyGrant_A
| 0 | 0 | 423189654 | 2712737 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.ReqImpliesValid_A
| 0 | 0 | 423189654 | 110047689 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.RoundRobin_A
| 0 | 0 | 423189654 | 20915 | 0 | 1053 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.ValidKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_scramble.gen_gf_mult.u_mult.IntegerLoops_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_scramble.gen_gf_mult.u_mult.StagePow2_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_state_regs.AssertConnected_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_state_regs_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo.DataKnown_A
| 0 | 0 | 423002885 | 3159795 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo.DepthKnown_A
| 0 | 0 | 423002885 | 422183143 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo.RvalidKnown_A
| 0 | 0 | 423002885 | 422183143 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo.WreadyKnown_A
| 0 | 0 | 423002885 | 422183143 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo.gen_normal_fifo.depthShallNotExceedParamDepth
| 0 | 0 | 423002885 | 3159795 | 0 | 0 |
|
tb.dut.u_eflash.u_bank_sequence_fifo.DataKnown_A
| 0 | 0 | 423189654 | 35009719 | 0 | 0 |
|
tb.dut.u_eflash.u_bank_sequence_fifo.DepthKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_eflash.u_bank_sequence_fifo.RvalidKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_eflash.u_bank_sequence_fifo.WreadyKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_eflash.u_bank_sequence_fifo.gen_normal_fifo.depthShallNotExceedParamDepth
| 0 | 0 | 423189654 | 35009719 | 0 | 0 |
|
tb.dut.u_eflash.u_disable_buf.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_eflash.u_disable_buf.OutputsKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_eflash.u_disable_buf.gen_no_flops.OutputDelay_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic.DataBitsPerMaskCheck_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheck_A
| 0 | 0 | 423189654 | 22730376 | 0 | 0 |
|
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic.DataBitsPerMaskCheck_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheck_A
| 0 | 0 | 423189654 | 5859260 | 0 | 0 |
|
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic.DataBitsPerMaskCheck_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheck_A
| 0 | 0 | 423189654 | 6088959 | 0 | 0 |
|
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo.DataKnown_A
| 0 | 0 | 423189654 | 106194619 | 0 | 0 |
|
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo.DepthKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo.RvalidKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo.WreadyKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo.gen_normal_fifo.depthShallNotExceedParamDepth
| 0 | 0 | 423189654 | 106194619 | 0 | 0 |
|
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic.DataBitsPerMaskCheck_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheck_A
| 0 | 0 | 423189654 | 67752630 | 0 | 0 |
|
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic.DataBitsPerMaskCheck_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheck_A
| 0 | 0 | 423189654 | 4672714 | 0 | 0 |
|
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic.DataBitsPerMaskCheck_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheck_A
| 0 | 0 | 423189654 | 3499614 | 0 | 0 |
|
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic.DataBitsPerMaskCheck_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheck_A
| 0 | 0 | 423189654 | 3532494 | 0 | 0 |
|
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo.DataKnown_A
| 0 | 0 | 423189654 | 87331374 | 0 | 0 |
|
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo.DepthKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo.RvalidKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo.WreadyKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo.gen_normal_fifo.depthShallNotExceedParamDepth
| 0 | 0 | 423189654 | 87331374 | 0 | 0 |
|
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic.DataBitsPerMaskCheck_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheck_A
| 0 | 0 | 423189654 | 66879271 | 0 | 0 |
|
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.en2addrHit
| 0 | 0 | 425753375 | 54912 | 0 | 0 |
|
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.reAfterRv
| 0 | 0 | 425753375 | 54912 | 0 | 0 |
|
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.rePulse
| 0 | 0 | 425753375 | 38238 | 0 | 0 |
|
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_chk.PayLoadWidthCheck
| 0 | 0 | 1274 | 1274 | 0 | 0 |
|
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.AllowedLatency_A
| 0 | 0 | 1274 | 1274 | 0 | 0 |
|
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.MatchedWidthAssert
| 0 | 0 | 1274 | 1274 | 0 | 0 |
|
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.u_err.dataWidthOnly32_A
| 0 | 0 | 1274 | 1274 | 0 | 0 |
|
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A
| 0 | 0 | 1274 | 1274 | 0 | 0 |
|
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck
| 0 | 0 | 1274 | 1274 | 0 | 0 |
|
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_rsp_intg_gen.DataWidthCheck_A
| 0 | 0 | 1274 | 1274 | 0 | 0 |
|
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_rsp_intg_gen.PayLoadWidthCheck
| 0 | 0 | 1274 | 1274 | 0 | 0 |
|
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.wePulse
| 0 | 0 | 425753375 | 16674 | 0 | 0 |
|
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.OutputsKnown_A
| 0 | 0 | 416486214 | 415666472 | 0 | 0 |
|
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_flops.OutputDelay_A
| 0 | 0 | 416486214 | 415634231 | 0 | 2769 |
|
tb.dut.u_flash_hw_if.DisableChk_A
| 0 | 0 | 411116219 | 4919124 | 0 | 44 |
|
tb.dut.u_flash_hw_if.ProgRdVerify_A
| 0 | 0 | 409228670 | 2043536 | 0 | 0 |
|
tb.dut.u_flash_hw_if.u_addr_sync_reqack.SyncReqAckAckNeedsReq
| 0 | 0 | 423189677 | 9005 | 0 | 0 |
|
tb.dut.u_flash_hw_if.u_addr_sync_reqack.SyncReqAckHoldReq
| 0 | 0 | 423096640 | 8674 | 0 | 0 |
|
tb.dut.u_flash_hw_if.u_data_sync_reqack.SyncReqAckAckNeedsReq
| 0 | 0 | 423189677 | 8969 | 0 | 0 |
|
tb.dut.u_flash_hw_if.u_data_sync_reqack.SyncReqAckHoldReq
| 0 | 0 | 406376979 | 8669 | 0 | 0 |
|
tb.dut.u_flash_hw_if.u_rma_state_regs.AssertConnected_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_flash_hw_if.u_rma_state_regs_A
| 0 | 0 | 423189677 | 422369935 | 0 | 0 |
|
tb.dut.u_flash_hw_if.u_state_regs.AssertConnected_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_flash_hw_if.u_state_regs_A
| 0 | 0 | 423189677 | 422369935 | 0 | 0 |
|
tb.dut.u_flash_hw_if.u_sync_rma_req.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_flash_hw_if.u_sync_rma_req.OutputsKnown_A
| 0 | 0 | 416486237 | 415666495 | 0 | 0 |
|
tb.dut.u_flash_hw_if.u_sync_rma_req.gen_flops.OutputDelay_A
| 0 | 0 | 416486237 | 415634239 | 0 | 2769 |
|
tb.dut.u_flash_mp.BankEraseData_A
| 0 | 0 | 423189677 | 7341528 | 0 | 0 |
|
tb.dut.u_flash_mp.BankEraseInfo_A
| 0 | 0 | 423189677 | 9306680 | 0 | 0 |
|
tb.dut.u_flash_mp.DataReqToInfo_A
| 0 | 0 | 423189677 | 265643712 | 0 | 0 |
|
tb.dut.u_flash_mp.InReqOutReq_A
| 0 | 0 | 423189677 | 298908806 | 0 | 0 |
|
tb.dut.u_flash_mp.InfoReqToData_A
| 0 | 0 | 423189677 | 33265094 | 0 | 0 |
|
tb.dut.u_flash_mp.NoReqWhenErr_A
| 0 | 0 | 418350944 | 111590 | 0 | 0 |
|
tb.dut.u_flash_mp.bkEraseEnOnehot_A
| 0 | 0 | 423189677 | 16648208 | 0 | 0 |
|
tb.dut.u_flash_mp.hwInfoRuleOnehot_A
| 0 | 0 | 423189677 | 154814635 | 0 | 0 |
|
tb.dut.u_flash_mp.invalidReqOnehot_A
| 0 | 0 | 423189677 | 298797176 | 0 | 0 |
|
tb.dut.u_flash_mp.requestTypesOnehot_A
| 0 | 0 | 423189677 | 298797176 | 0 | 0 |
|
tb.dut.u_intr_corr_err.IntrTKind_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_intr_op_done.IntrTKind_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_intr_prog_empty.IntrTKind_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_intr_prog_lvl.IntrTKind_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_intr_rd_full.IntrTKind_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_intr_rd_lvl.IntrTKind_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_lc_escalation_en_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_lc_escalation_en_sync.OutputsKnown_A
| 0 | 0 | 416463700 | 415643958 | 0 | 0 |
|
tb.dut.u_lc_escalation_en_sync.gen_flops.OutputDelay_A
| 0 | 0 | 416463700 | 415611846 | 0 | 2625 |
|
tb.dut.u_lc_seed_hw_rd_en_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_lc_seed_hw_rd_en_sync.OutputsKnown_A
| 0 | 0 | 416486237 | 415666495 | 0 | 0 |
|
tb.dut.u_lc_seed_hw_rd_en_sync.gen_flops.OutputDelay_A
| 0 | 0 | 416486237 | 415634239 | 0 | 2769 |
|
tb.dut.u_prog_fifo.DataKnown_A
| 0 | 0 | 423189654 | 189889109 | 0 | 0 |
|
tb.dut.u_prog_fifo.DepthKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_prog_fifo.RvalidKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_prog_fifo.WreadyKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_prog_fifo.gen_normal_fifo.depthShallNotExceedParamDepth
| 0 | 0 | 423189654 | 189889109 | 0 | 0 |
|
tb.dut.u_prog_tl_gate.u_err_en_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_prog_tl_gate.u_err_en_sync.OutputsKnown_A
| 0 | 0 | 416486214 | 415666472 | 0 | 0 |
|
tb.dut.u_prog_tl_gate.u_err_en_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 416486214 | 415666472 | 0 | 0 |
|
tb.dut.u_prog_tl_gate.u_state_regs.AssertConnected_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_prog_tl_gate.u_state_regs_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_prog_tl_gate.u_tlul_err_resp.u_intg_gen.DataWidthCheck_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_prog_tl_gate.u_tlul_err_resp.u_intg_gen.PayLoadWidthCheck
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_reg_core.en2addrHit
| 0 | 0 | 425753398 | 24091504 | 0 | 0 |
|
tb.dut.u_reg_core.reAfterRv
| 0 | 0 | 425753398 | 24091487 | 0 | 0 |
|
tb.dut.u_reg_core.rePulse
| 0 | 0 | 425753398 | 21825856 | 0 | 0 |
|
tb.dut.u_reg_core.u_chk.PayLoadWidthCheck
| 0 | 0 | 1274 | 1274 | 0 | 0 |
|
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_0.CheckSwAccessIsLegal_A
| 0 | 0 | 1274 | 1274 | 0 | 0 |
|
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_0.MubiIsNotYetSupported_A
| 0 | 0 | 425753398 | 424847624 | 0 | 0 |
|
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_1.CheckSwAccessIsLegal_A
| 0 | 0 | 1274 | 1274 | 0 | 0 |
|
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_1.MubiIsNotYetSupported_A
| 0 | 0 | 425753398 | 424847624 | 0 | 0 |
|
tb.dut.u_reg_core.u_reg_if.AllowedLatency_A
| 0 | 0 | 1274 | 1274 | 0 | 0 |
|
tb.dut.u_reg_core.u_reg_if.MatchedWidthAssert
| 0 | 0 | 1274 | 1274 | 0 | 0 |
|
tb.dut.u_reg_core.u_reg_if.u_err.dataWidthOnly32_A
| 0 | 0 | 1274 | 1274 | 0 | 0 |
|
tb.dut.u_reg_core.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A
| 0 | 0 | 1274 | 1274 | 0 | 0 |
|
tb.dut.u_reg_core.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck
| 0 | 0 | 1274 | 1274 | 0 | 0 |
|
tb.dut.u_reg_core.u_rsp_intg_gen.DataWidthCheck_A
| 0 | 0 | 1274 | 1274 | 0 | 0 |
|
tb.dut.u_reg_core.u_rsp_intg_gen.PayLoadWidthCheck
| 0 | 0 | 1274 | 1274 | 0 | 0 |
|
tb.dut.u_reg_core.u_socket.NotOverflowed_A
| 0 | 0 | 425753375 | 424847601 | 0 | 0 |
|
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.DataKnown_A
| 0 | 0 | 425753375 | 36292630 | 0 | 0 |
|
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.DepthKnown_A
| 0 | 0 | 425753375 | 424847601 | 0 | 0 |
|
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.RvalidKnown_A
| 0 | 0 | 425753375 | 424847601 | 0 | 0 |
|
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.WreadyKnown_A
| 0 | 0 | 425753375 | 424847601 | 0 | 0 |
|
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.gen_passthru_fifo.paramCheckPass
| 0 | 0 | 1274 | 1274 | 0 | 0 |
|
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.DataKnown_A
| 0 | 0 | 425753375 | 39038805 | 0 | 0 |
|
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.DepthKnown_A
| 0 | 0 | 425753375 | 424847601 | 0 | 0 |
|
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.RvalidKnown_A
| 0 | 0 | 425753375 | 424847601 | 0 | 0 |
|
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.WreadyKnown_A
| 0 | 0 | 425753375 | 424847601 | 0 | 0 |
|
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.gen_passthru_fifo.paramCheckPass
| 0 | 0 | 1274 | 1274 | 0 | 0 |
|
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.DataKnown_A
| 0 | 0 | 425753375 | 7599776 | 0 | 0 |
|
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.DepthKnown_A
| 0 | 0 | 425753375 | 424847601 | 0 | 0 |
|
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.RvalidKnown_A
| 0 | 0 | 425753375 | 424847601 | 0 | 0 |
|
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.WreadyKnown_A
| 0 | 0 | 425753375 | 424847601 | 0 | 0 |
|
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass
| 0 | 0 | 1274 | 1274 | 0 | 0 |
|
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.DataKnown_A
| 0 | 0 | 425753375 | 3230684 | 0 | 0 |
|
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.DepthKnown_A
| 0 | 0 | 425753375 | 424847601 | 0 | 0 |
|
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.RvalidKnown_A
| 0 | 0 | 425753375 | 424847601 | 0 | 0 |
|
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.WreadyKnown_A
| 0 | 0 | 425753375 | 424847601 | 0 | 0 |
|
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass
| 0 | 0 | 1274 | 1274 | 0 | 0 |
|
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.DataKnown_A
| 0 | 0 | 425753375 | 4108423 | 0 | 0 |
|
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.DepthKnown_A
| 0 | 0 | 425753375 | 424847601 | 0 | 0 |
|
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.RvalidKnown_A
| 0 | 0 | 425753375 | 424847601 | 0 | 0 |
|
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.WreadyKnown_A
| 0 | 0 | 425753375 | 424847601 | 0 | 0 |
|
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass
| 0 | 0 | 1274 | 1274 | 0 | 0 |
|
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.DataKnown_A
| 0 | 0 | 425753375 | 4565978 | 0 | 0 |
|
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.DepthKnown_A
| 0 | 0 | 425753375 | 424847601 | 0 | 0 |
|
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.RvalidKnown_A
| 0 | 0 | 425753375 | 424847601 | 0 | 0 |
|
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.WreadyKnown_A
| 0 | 0 | 425753375 | 424847601 | 0 | 0 |
|
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass
| 0 | 0 | 1274 | 1274 | 0 | 0 |
|
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo.DataKnown_A
| 0 | 0 | 425753375 | 24519392 | 0 | 0 |
|
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo.DepthKnown_A
| 0 | 0 | 425753375 | 424847601 | 0 | 0 |
|
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo.RvalidKnown_A
| 0 | 0 | 425753375 | 424847601 | 0 | 0 |
|
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo.WreadyKnown_A
| 0 | 0 | 425753375 | 424847601 | 0 | 0 |
|
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass
| 0 | 0 | 1274 | 1274 | 0 | 0 |
|
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo.DataKnown_A
| 0 | 0 | 425753375 | 31242143 | 0 | 0 |
|
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo.DepthKnown_A
| 0 | 0 | 425753375 | 424847601 | 0 | 0 |
|
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo.RvalidKnown_A
| 0 | 0 | 425753375 | 424847601 | 0 | 0 |
|
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo.WreadyKnown_A
| 0 | 0 | 425753375 | 424847601 | 0 | 0 |
|
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass
| 0 | 0 | 1274 | 1274 | 0 | 0 |
|
tb.dut.u_reg_core.u_socket.gen_err_resp.err_resp.u_intg_gen.DataWidthCheck_A
| 0 | 0 | 1274 | 1274 | 0 | 0 |
|
tb.dut.u_reg_core.u_socket.gen_err_resp.err_resp.u_intg_gen.PayLoadWidthCheck
| 0 | 0 | 1274 | 1274 | 0 | 0 |
|
tb.dut.u_reg_core.u_socket.maxN
| 0 | 0 | 1274 | 1274 | 0 | 0 |
|
tb.dut.u_reg_core.wePulse
| 0 | 0 | 425753398 | 2265631 | 0 | 0 |
|
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.InfoNoBiggerThanData_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.u_creator_mubi.OutputsKnown_A
| 0 | 0 | 423189677 | 422369935 | 0 | 0 |
|
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.u_owner_mubi.OutputsKnown_A
| 0 | 0 | 423189677 | 422369935 | 0 | 0 |
|
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.InfoNoBiggerThanData_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.u_creator_mubi.OutputsKnown_A
| 0 | 0 | 423189677 | 422369935 | 0 | 0 |
|
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.u_owner_mubi.OutputsKnown_A
| 0 | 0 | 423189677 | 422369935 | 0 | 0 |
|
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.InfoNoBiggerThanData_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.u_creator_mubi.OutputsKnown_A
| 0 | 0 | 423189677 | 422369935 | 0 | 0 |
|
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.u_owner_mubi.OutputsKnown_A
| 0 | 0 | 423189677 | 422369935 | 0 | 0 |
|
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.InfoNoBiggerThanData_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.u_creator_mubi.OutputsKnown_A
| 0 | 0 | 423189677 | 422369935 | 0 | 0 |
|
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.u_owner_mubi.OutputsKnown_A
| 0 | 0 | 423189677 | 422369935 | 0 | 0 |
|
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.InfoNoBiggerThanData_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.u_creator_mubi.OutputsKnown_A
| 0 | 0 | 423189677 | 422369935 | 0 | 0 |
|
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.u_owner_mubi.OutputsKnown_A
| 0 | 0 | 423189677 | 422369935 | 0 | 0 |
|
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.InfoNoBiggerThanData_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.u_creator_mubi.OutputsKnown_A
| 0 | 0 | 423189677 | 422369935 | 0 | 0 |
|
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.u_owner_mubi.OutputsKnown_A
| 0 | 0 | 423189677 | 422369935 | 0 | 0 |
|
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.OutputsKnown_A
| 0 | 0 | 416486237 | 415666495 | 0 | 0 |
|
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.gen_flops.OutputDelay_A
| 0 | 0 | 416486237 | 415634239 | 0 | 2769 |
|
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.OutputsKnown_A
| 0 | 0 | 416486237 | 415666495 | 0 | 0 |
|
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.gen_flops.OutputDelay_A
| 0 | 0 | 416486237 | 415634239 | 0 | 2769 |
|
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.OutputsKnown_A
| 0 | 0 | 416486237 | 415666495 | 0 | 0 |
|
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_flops.OutputDelay_A
| 0 | 0 | 416486237 | 415634239 | 0 | 2769 |
|
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.OutputsKnown_A
| 0 | 0 | 416486237 | 415666495 | 0 | 0 |
|
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.gen_flops.OutputDelay_A
| 0 | 0 | 416486237 | 415634239 | 0 | 2769 |
|
tb.dut.u_sw_rd_fifo.DataKnown_A
| 0 | 0 | 423189654 | 51916979 | 0 | 0 |
|
tb.dut.u_sw_rd_fifo.DepthKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_sw_rd_fifo.RvalidKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_sw_rd_fifo.WreadyKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_sw_rd_fifo.gen_normal_fifo.depthShallNotExceedParamDepth
| 0 | 0 | 423189654 | 51916979 | 0 | 0 |
|
tb.dut.u_tl_adapter_eflash.AddrOutKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_tl_adapter_eflash.DataIntgOptions_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_tl_adapter_eflash.ReqOutKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_tl_adapter_eflash.SramDwHasByteGranularity_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_tl_adapter_eflash.SramDwIsMultipleOfTlulWidth_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_tl_adapter_eflash.TlOutKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_tl_adapter_eflash.TlOutPayloadKnown_A
| 0 | 0 | 423189654 | 6162698 | 0 | 0 |
|
tb.dut.u_tl_adapter_eflash.TlOutPayloadKnown_AKnownEnable
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_tl_adapter_eflash.WdataOutKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_tl_adapter_eflash.WeOutKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_tl_adapter_eflash.WmaskOutKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_tl_adapter_eflash.adapterNoReadOrWrite
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_tl_adapter_eflash.gen_cmd_intg_check.u_cmd_intg_chk.PayLoadWidthCheck
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_tl_adapter_eflash.rvalidHighReqFifoEmpty
| 0 | 0 | 423189654 | 4461843 | 0 | 0 |
|
tb.dut.u_tl_adapter_eflash.rvalidHighWhenRspFifoFull
| 0 | 0 | 423189654 | 4461843 | 0 | 0 |
|
tb.dut.u_tl_adapter_eflash.u_err.dataWidthOnly32_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_tl_adapter_eflash.u_reqfifo.DataKnown_A
| 0 | 0 | 423189654 | 36710426 | 0 | 0 |
|
tb.dut.u_tl_adapter_eflash.u_reqfifo.DepthKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_tl_adapter_eflash.u_reqfifo.RvalidKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_tl_adapter_eflash.u_reqfifo.WreadyKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_tl_adapter_eflash.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth
| 0 | 0 | 423189654 | 36710426 | 0 | 0 |
|
tb.dut.u_tl_adapter_eflash.u_rsp_gen.DataWidthCheck_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_tl_adapter_eflash.u_rsp_gen.PayLoadWidthCheck
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_tl_adapter_eflash.u_rspfifo.DataKnown_A
| 0 | 0 | 423189654 | 6156726 | 0 | 0 |
|
tb.dut.u_tl_adapter_eflash.u_rspfifo.DepthKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_tl_adapter_eflash.u_rspfifo.RvalidKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_tl_adapter_eflash.u_rspfifo.WreadyKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_tl_adapter_eflash.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth
| 0 | 0 | 423189654 | 6156726 | 0 | 0 |
|
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.DataKnown_A
| 0 | 0 | 423189654 | 35009719 | 0 | 0 |
|
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.DepthKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.RvalidKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.WreadyKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth
| 0 | 0 | 423189654 | 35009719 | 0 | 0 |
|
tb.dut.u_tl_gate.u_err_en_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_tl_gate.u_err_en_sync.OutputsKnown_A
| 0 | 0 | 416486214 | 415666472 | 0 | 0 |
|
tb.dut.u_tl_gate.u_err_en_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 416486214 | 415666472 | 0 | 0 |
|
tb.dut.u_tl_gate.u_state_regs.AssertConnected_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_tl_gate.u_state_regs_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_tl_gate.u_tlul_err_resp.u_intg_gen.DataWidthCheck_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_tl_gate.u_tlul_err_resp.u_intg_gen.PayLoadWidthCheck
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_to_prog_fifo.AddrOutKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_to_prog_fifo.DataIntgOptions_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_to_prog_fifo.ReqOutKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_to_prog_fifo.SramDwHasByteGranularity_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_to_prog_fifo.SramDwIsMultipleOfTlulWidth_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_to_prog_fifo.TlOutKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_to_prog_fifo.TlOutPayloadKnown_A
| 0 | 0 | 423189654 | 3203360 | 0 | 0 |
|
tb.dut.u_to_prog_fifo.TlOutPayloadKnown_AKnownEnable
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_to_prog_fifo.WdataOutKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_to_prog_fifo.WeOutKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_to_prog_fifo.WmaskOutKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_to_prog_fifo.adapterNoReadOrWrite
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_to_prog_fifo.u_err.dataWidthOnly32_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_to_prog_fifo.u_reqfifo.DataKnown_A
| 0 | 0 | 423189654 | 3203360 | 0 | 0 |
|
tb.dut.u_to_prog_fifo.u_reqfifo.DepthKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_to_prog_fifo.u_reqfifo.RvalidKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_to_prog_fifo.u_reqfifo.WreadyKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_to_prog_fifo.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth
| 0 | 0 | 423189654 | 3203360 | 0 | 0 |
|
tb.dut.u_to_prog_fifo.u_rsp_gen.DataWidthCheck_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_to_prog_fifo.u_rsp_gen.PayLoadWidthCheck
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_to_prog_fifo.u_rspfifo.DepthKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_to_prog_fifo.u_rspfifo.RvalidKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_to_prog_fifo.u_rspfifo.WreadyKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_to_prog_fifo.u_sramreqfifo.DepthKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_to_prog_fifo.u_sramreqfifo.RvalidKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_to_prog_fifo.u_sramreqfifo.WreadyKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_to_rd_fifo.AddrOutKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_to_rd_fifo.DataIntgOptions_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_to_rd_fifo.ReqOutKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_to_rd_fifo.SramDwHasByteGranularity_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_to_rd_fifo.SramDwIsMultipleOfTlulWidth_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_to_rd_fifo.TlOutKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_to_rd_fifo.TlOutPayloadKnown_A
| 0 | 0 | 423189654 | 4562270 | 0 | 0 |
|
tb.dut.u_to_rd_fifo.TlOutPayloadKnown_AKnownEnable
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_to_rd_fifo.WdataOutKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_to_rd_fifo.WeOutKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_to_rd_fifo.WmaskOutKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_to_rd_fifo.adapterNoReadOrWrite
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_to_rd_fifo.rvalidHighReqFifoEmpty
| 0 | 0 | 423189654 | 3155630 | 0 | 0 |
|
tb.dut.u_to_rd_fifo.rvalidHighWhenRspFifoFull
| 0 | 0 | 422583589 | 3149254 | 0 | 0 |
|
tb.dut.u_to_rd_fifo.u_err.dataWidthOnly32_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_to_rd_fifo.u_reqfifo.DataKnown_A
| 0 | 0 | 423189654 | 4562270 | 0 | 0 |
|
tb.dut.u_to_rd_fifo.u_reqfifo.DepthKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_to_rd_fifo.u_reqfifo.RvalidKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_to_rd_fifo.u_reqfifo.WreadyKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_to_rd_fifo.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth
| 0 | 0 | 423189654 | 4562270 | 0 | 0 |
|
tb.dut.u_to_rd_fifo.u_rsp_gen.DataWidthCheck_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_to_rd_fifo.u_rsp_gen.PayLoadWidthCheck
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_to_rd_fifo.u_rspfifo.DataKnown_A
| 0 | 0 | 423002885 | 4554321 | 0 | 0 |
|
tb.dut.u_to_rd_fifo.u_rspfifo.DepthKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_to_rd_fifo.u_rspfifo.RvalidKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_to_rd_fifo.u_rspfifo.WreadyKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_to_rd_fifo.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth
| 0 | 0 | 423189654 | 4568120 | 0 | 0 |
|
tb.dut.u_to_rd_fifo.u_sramreqfifo.DataKnown_A
| 0 | 0 | 423189654 | 3155630 | 0 | 0 |
|
tb.dut.u_to_rd_fifo.u_sramreqfifo.DepthKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_to_rd_fifo.u_sramreqfifo.RvalidKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_to_rd_fifo.u_sramreqfifo.WreadyKnown_A
| 0 | 0 | 423189654 | 422369912 | 0 | 0 |
|
tb.dut.u_to_rd_fifo.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth
| 0 | 0 | 423189654 | 3155630 | 0 | 0 |
|