Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
199 |
1 |
|
T4 |
12 |
|
T17 |
2 |
|
T218 |
1 |
| others[1] |
262 |
1 |
|
T4 |
8 |
|
T39 |
1 |
|
T17 |
1 |
| others[2] |
230 |
1 |
|
T4 |
6 |
|
T17 |
2 |
|
T67 |
1 |
| others[3] |
396 |
1 |
|
T4 |
17 |
|
T40 |
1 |
|
T17 |
1 |
| false |
113 |
1 |
|
T4 |
2 |
|
T382 |
1 |
|
T59 |
4 |
| true |
12681 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8190 |
1 |
|
T3 |
1 |
|
T4 |
14 |
|
T25 |
1 |
| others[1] |
1203 |
1 |
|
T4 |
20 |
|
T61 |
1 |
|
T22 |
2 |
| others[2] |
1259 |
1 |
|
T4 |
22 |
|
T16 |
1 |
|
T25 |
1 |
| others[3] |
2103 |
1 |
|
T2 |
1 |
|
T4 |
33 |
|
T108 |
1 |
| false |
686 |
1 |
|
T4 |
12 |
|
T21 |
1 |
|
T22 |
1 |
| true |
440 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8291 |
1 |
|
T4 |
20 |
|
T108 |
1 |
|
T44 |
140 |
| others[1] |
1258 |
1 |
|
T4 |
14 |
|
T20 |
1 |
|
T32 |
2 |
| others[2] |
1215 |
1 |
|
T3 |
1 |
|
T4 |
27 |
|
T7 |
1 |
| others[3] |
2039 |
1 |
|
T2 |
1 |
|
T4 |
24 |
|
T90 |
1 |
| false |
660 |
1 |
|
T4 |
16 |
|
T25 |
1 |
|
T20 |
1 |
| true |
418 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
111 |
1 |
|
T4 |
6 |
|
T17 |
3 |
|
T218 |
1 |
| others[1] |
112 |
1 |
|
T4 |
3 |
|
T25 |
1 |
|
T17 |
1 |
| others[2] |
108 |
1 |
|
T4 |
2 |
|
T17 |
1 |
|
T316 |
1 |
| others[3] |
178 |
1 |
|
T4 |
4 |
|
T25 |
1 |
|
T17 |
2 |
| false |
48 |
1 |
|
T4 |
6 |
|
T17 |
1 |
|
T261 |
1 |
| true |
13324 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
240 |
1 |
|
T4 |
8 |
|
T17 |
1 |
|
T261 |
1 |
| others[1] |
248 |
1 |
|
T4 |
13 |
|
T45 |
1 |
|
T48 |
1 |
| others[2] |
239 |
1 |
|
T4 |
10 |
|
T25 |
1 |
|
T73 |
1 |
| others[3] |
396 |
1 |
|
T1 |
1 |
|
T4 |
14 |
|
T7 |
1 |
| false |
124 |
1 |
|
T4 |
7 |
|
T59 |
3 |
|
T70 |
4 |
| true |
12634 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
49 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8104 |
1 |
|
T1 |
1 |
|
T4 |
17 |
|
T16 |
1 |
| others[1] |
1074 |
1 |
|
T4 |
25 |
|
T25 |
1 |
|
T20 |
2 |
| others[2] |
1028 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
19 |
| others[3] |
1701 |
1 |
|
T4 |
28 |
|
T11 |
1 |
|
T20 |
2 |
| false |
545 |
1 |
|
T4 |
12 |
|
T108 |
1 |
|
T90 |
1 |
| true |
1429 |
1 |
|
T7 |
1 |
|
T89 |
1 |
|
T164 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
220 |
1 |
|
T4 |
12 |
|
T17 |
1 |
|
T224 |
1 |
| others[1] |
216 |
1 |
|
T4 |
2 |
|
T17 |
2 |
|
T218 |
1 |
| others[2] |
258 |
1 |
|
T4 |
11 |
|
T17 |
1 |
|
T287 |
1 |
| others[3] |
369 |
1 |
|
T4 |
19 |
|
T7 |
1 |
|
T73 |
1 |
| false |
125 |
1 |
|
T4 |
5 |
|
T39 |
1 |
|
T382 |
1 |
| true |
12693 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
207 |
1 |
|
T4 |
15 |
|
T25 |
1 |
|
T17 |
1 |
| others[1] |
250 |
1 |
|
T4 |
20 |
|
T17 |
1 |
|
T316 |
1 |
| others[2] |
227 |
1 |
|
T4 |
8 |
|
T59 |
7 |
|
T70 |
10 |
| others[3] |
349 |
1 |
|
T4 |
15 |
|
T17 |
1 |
|
T218 |
1 |
| false |
139 |
1 |
|
T4 |
5 |
|
T382 |
1 |
|
T109 |
1 |
| true |
12709 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8260 |
1 |
|
T4 |
17 |
|
T16 |
1 |
|
T44 |
140 |
| others[1] |
1251 |
1 |
|
T4 |
26 |
|
T20 |
1 |
|
T32 |
1 |
| others[2] |
1208 |
1 |
|
T3 |
1 |
|
T4 |
17 |
|
T20 |
1 |
| others[3] |
2080 |
1 |
|
T2 |
1 |
|
T4 |
31 |
|
T25 |
1 |
| false |
628 |
1 |
|
T4 |
10 |
|
T25 |
1 |
|
T108 |
1 |
| true |
454 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1276 |
1 |
|
T3 |
1 |
|
T4 |
22 |
|
T20 |
1 |
| others[1] |
1221 |
1 |
|
T2 |
1 |
|
T4 |
15 |
|
T16 |
1 |
| others[2] |
1239 |
1 |
|
T4 |
21 |
|
T6 |
1 |
|
T20 |
1 |
| others[3] |
2086 |
1 |
|
T4 |
30 |
|
T20 |
4 |
|
T21 |
1 |
| false |
631 |
1 |
|
T4 |
13 |
|
T21 |
1 |
|
T45 |
1 |
| true |
420 |
1 |
|
T1 |
1 |
|
T7 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
98 |
1 |
|
T4 |
3 |
|
T17 |
2 |
|
T59 |
5 |
| others[1] |
106 |
1 |
|
T4 |
6 |
|
T25 |
1 |
|
T39 |
1 |
| others[2] |
110 |
1 |
|
T4 |
3 |
|
T25 |
1 |
|
T17 |
1 |
| others[3] |
207 |
1 |
|
T4 |
10 |
|
T17 |
5 |
|
T218 |
1 |
| false |
56 |
1 |
|
T4 |
4 |
|
T59 |
4 |
|
T70 |
2 |
| true |
6296 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
225 |
1 |
|
T4 |
9 |
|
T40 |
1 |
|
T17 |
1 |
| others[1] |
222 |
1 |
|
T4 |
12 |
|
T7 |
1 |
|
T49 |
1 |
| others[2] |
221 |
1 |
|
T4 |
8 |
|
T218 |
1 |
|
T83 |
1 |
| others[3] |
384 |
1 |
|
T4 |
26 |
|
T25 |
1 |
|
T17 |
1 |
| false |
123 |
1 |
|
T4 |
3 |
|
T17 |
2 |
|
T261 |
1 |
| true |
5698 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1099 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
26 |
| others[1] |
1007 |
1 |
|
T4 |
18 |
|
T25 |
1 |
|
T108 |
1 |
| others[2] |
1079 |
1 |
|
T4 |
20 |
|
T25 |
1 |
|
T20 |
1 |
| others[3] |
1740 |
1 |
|
T4 |
28 |
|
T16 |
1 |
|
T20 |
2 |
| false |
552 |
1 |
|
T4 |
9 |
|
T7 |
1 |
|
T20 |
2 |
| true |
1396 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T49 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
231 |
1 |
|
T4 |
7 |
|
T25 |
1 |
|
T67 |
3 |
| others[1] |
222 |
1 |
|
T1 |
1 |
|
T4 |
8 |
|
T41 |
1 |
| others[2] |
241 |
1 |
|
T4 |
11 |
|
T17 |
1 |
|
T67 |
1 |
| others[3] |
404 |
1 |
|
T4 |
11 |
|
T40 |
1 |
|
T17 |
3 |
| false |
116 |
1 |
|
T4 |
4 |
|
T74 |
1 |
|
T59 |
4 |
| true |
5659 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
60 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
197 |
1 |
|
T4 |
11 |
|
T25 |
1 |
|
T214 |
1 |
| others[1] |
216 |
1 |
|
T4 |
4 |
|
T218 |
2 |
|
T382 |
1 |
| others[2] |
232 |
1 |
|
T4 |
4 |
|
T17 |
2 |
|
T198 |
1 |
| others[3] |
370 |
1 |
|
T4 |
16 |
|
T25 |
1 |
|
T17 |
2 |
| false |
126 |
1 |
|
T4 |
3 |
|
T48 |
1 |
|
T59 |
4 |
| true |
5732 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1243 |
1 |
|
T4 |
17 |
|
T21 |
1 |
|
T32 |
2 |
| others[1] |
1231 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
16 |
| others[2] |
1292 |
1 |
|
T4 |
24 |
|
T25 |
1 |
|
T108 |
1 |
| others[3] |
2005 |
1 |
|
T4 |
31 |
|
T20 |
2 |
|
T21 |
3 |
| false |
645 |
1 |
|
T4 |
13 |
|
T25 |
1 |
|
T20 |
1 |
| true |
457 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1292 |
1 |
|
T3 |
1 |
|
T4 |
14 |
|
T25 |
1 |
| others[1] |
1252 |
1 |
|
T4 |
11 |
|
T21 |
1 |
|
T22 |
4 |
| others[2] |
1192 |
1 |
|
T4 |
25 |
|
T108 |
1 |
|
T21 |
2 |
| others[3] |
2082 |
1 |
|
T4 |
35 |
|
T7 |
1 |
|
T16 |
1 |
| false |
629 |
1 |
|
T2 |
1 |
|
T4 |
16 |
|
T20 |
1 |
| true |
426 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
117 |
1 |
|
T4 |
3 |
|
T48 |
1 |
|
T17 |
2 |
| others[1] |
99 |
1 |
|
T4 |
2 |
|
T17 |
1 |
|
T379 |
1 |
| others[2] |
116 |
1 |
|
T4 |
3 |
|
T17 |
1 |
|
T218 |
1 |
| others[3] |
177 |
1 |
|
T4 |
7 |
|
T25 |
2 |
|
T17 |
4 |
| false |
67 |
1 |
|
T4 |
1 |
|
T59 |
4 |
|
T70 |
3 |
| true |
6297 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
235 |
1 |
|
T4 |
6 |
|
T289 |
1 |
|
T385 |
1 |
| others[1] |
236 |
1 |
|
T4 |
10 |
|
T45 |
1 |
|
T41 |
1 |
| others[2] |
231 |
1 |
|
T4 |
5 |
|
T17 |
2 |
|
T224 |
1 |
| others[3] |
403 |
1 |
|
T4 |
19 |
|
T47 |
1 |
|
T48 |
1 |
| false |
116 |
1 |
|
T4 |
6 |
|
T17 |
1 |
|
T59 |
3 |
| true |
5652 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1025 |
1 |
|
T4 |
23 |
|
T11 |
1 |
|
T20 |
1 |
| others[1] |
1088 |
1 |
|
T3 |
1 |
|
T4 |
17 |
|
T16 |
1 |
| others[2] |
1050 |
1 |
|
T2 |
1 |
|
T4 |
19 |
|
T25 |
1 |
| others[3] |
1771 |
1 |
|
T4 |
30 |
|
T25 |
1 |
|
T20 |
3 |
| false |
556 |
1 |
|
T4 |
12 |
|
T21 |
1 |
|
T164 |
1 |
| true |
1383 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
226 |
1 |
|
T4 |
9 |
|
T7 |
1 |
|
T25 |
1 |
| others[1] |
224 |
1 |
|
T4 |
15 |
|
T218 |
1 |
|
T120 |
1 |
| others[2] |
237 |
1 |
|
T4 |
11 |
|
T17 |
1 |
|
T198 |
1 |
| others[3] |
374 |
1 |
|
T1 |
1 |
|
T4 |
16 |
|
T49 |
1 |
| false |
138 |
1 |
|
T4 |
6 |
|
T17 |
1 |
|
T19 |
1 |
| true |
5674 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
44 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
210 |
1 |
|
T4 |
12 |
|
T48 |
1 |
|
T17 |
1 |
| others[1] |
226 |
1 |
|
T4 |
11 |
|
T17 |
1 |
|
T198 |
1 |
| others[2] |
226 |
1 |
|
T4 |
9 |
|
T261 |
1 |
|
T83 |
1 |
| others[3] |
383 |
1 |
|
T4 |
21 |
|
T17 |
1 |
|
T289 |
1 |
| false |
104 |
1 |
|
T4 |
6 |
|
T17 |
1 |
|
T87 |
1 |
| true |
5724 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1285 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
21 |
| others[1] |
1211 |
1 |
|
T4 |
22 |
|
T20 |
2 |
|
T21 |
1 |
| others[2] |
1268 |
1 |
|
T4 |
14 |
|
T108 |
1 |
|
T21 |
2 |
| others[3] |
1993 |
1 |
|
T4 |
33 |
|
T16 |
1 |
|
T25 |
1 |
| false |
666 |
1 |
|
T4 |
11 |
|
T20 |
1 |
|
T32 |
1 |
| true |
450 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1255 |
1 |
|
T4 |
22 |
|
T16 |
1 |
|
T25 |
1 |
| others[1] |
1285 |
1 |
|
T4 |
19 |
|
T20 |
1 |
|
T45 |
1 |
| others[2] |
1216 |
1 |
|
T4 |
21 |
|
T32 |
3 |
|
T61 |
1 |
| others[3] |
2049 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
29 |
| false |
640 |
1 |
|
T4 |
10 |
|
T21 |
1 |
|
T22 |
1 |
| true |
428 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
105 |
1 |
|
T4 |
8 |
|
T17 |
5 |
|
T67 |
1 |
| others[1] |
105 |
1 |
|
T4 |
1 |
|
T39 |
1 |
|
T261 |
1 |
| others[2] |
90 |
1 |
|
T4 |
4 |
|
T218 |
1 |
|
T379 |
1 |
| others[3] |
171 |
1 |
|
T4 |
4 |
|
T17 |
2 |
|
T261 |
1 |
| false |
67 |
1 |
|
T4 |
1 |
|
T25 |
2 |
|
T17 |
1 |
| true |
6335 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
250 |
1 |
|
T1 |
1 |
|
T4 |
12 |
|
T48 |
1 |
| others[1] |
232 |
1 |
|
T4 |
7 |
|
T17 |
1 |
|
T381 |
1 |
| others[2] |
259 |
1 |
|
T4 |
5 |
|
T17 |
1 |
|
T198 |
1 |
| others[3] |
403 |
1 |
|
T4 |
18 |
|
T49 |
1 |
|
T17 |
2 |
| false |
134 |
1 |
|
T4 |
6 |
|
T47 |
1 |
|
T109 |
1 |
| true |
5595 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
53 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1088 |
1 |
|
T4 |
21 |
|
T20 |
2 |
|
T32 |
4 |
| others[1] |
1033 |
1 |
|
T3 |
1 |
|
T4 |
17 |
|
T20 |
1 |
| others[2] |
1038 |
1 |
|
T4 |
18 |
|
T6 |
1 |
|
T16 |
1 |
| others[3] |
1754 |
1 |
|
T2 |
1 |
|
T4 |
33 |
|
T7 |
1 |
| false |
566 |
1 |
|
T4 |
12 |
|
T25 |
1 |
|
T20 |
1 |
| true |
1394 |
1 |
|
T1 |
1 |
|
T11 |
1 |
|
T89 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
239 |
1 |
|
T4 |
5 |
|
T6 |
1 |
|
T49 |
1 |
| others[1] |
209 |
1 |
|
T4 |
12 |
|
T48 |
1 |
|
T74 |
1 |
| others[2] |
263 |
1 |
|
T4 |
16 |
|
T7 |
1 |
|
T17 |
1 |
| others[3] |
399 |
1 |
|
T1 |
1 |
|
T4 |
19 |
|
T39 |
1 |
| false |
99 |
1 |
|
T4 |
5 |
|
T379 |
1 |
|
T380 |
1 |
| true |
5664 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
44 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
232 |
1 |
|
T4 |
11 |
|
T17 |
1 |
|
T59 |
5 |
| others[1] |
216 |
1 |
|
T4 |
16 |
|
T39 |
1 |
|
T261 |
1 |
| others[2] |
214 |
1 |
|
T4 |
7 |
|
T17 |
1 |
|
T218 |
1 |
| others[3] |
381 |
1 |
|
T4 |
15 |
|
T25 |
2 |
|
T17 |
1 |
| false |
122 |
1 |
|
T4 |
5 |
|
T198 |
1 |
|
T289 |
1 |
| true |
5708 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1261 |
1 |
|
T3 |
1 |
|
T4 |
19 |
|
T20 |
1 |
| others[1] |
1240 |
1 |
|
T2 |
1 |
|
T4 |
22 |
|
T25 |
1 |
| others[2] |
1273 |
1 |
|
T4 |
16 |
|
T6 |
1 |
|
T25 |
1 |
| others[3] |
2026 |
1 |
|
T4 |
33 |
|
T20 |
1 |
|
T45 |
1 |
| false |
629 |
1 |
|
T4 |
11 |
|
T16 |
1 |
|
T108 |
1 |
| true |
444 |
1 |
|
T1 |
1 |
|
T7 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1221 |
1 |
|
T4 |
17 |
|
T16 |
1 |
|
T20 |
1 |
| others[1] |
1198 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
23 |
| others[2] |
1279 |
1 |
|
T4 |
18 |
|
T25 |
1 |
|
T21 |
2 |
| others[3] |
2118 |
1 |
|
T4 |
37 |
|
T25 |
1 |
|
T20 |
4 |
| false |
631 |
1 |
|
T4 |
6 |
|
T20 |
1 |
|
T21 |
1 |
| true |
426 |
1 |
|
T1 |
1 |
|
T7 |
1 |
|
T11 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |