Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
111 |
1 |
|
T4 |
6 |
|
T17 |
1 |
|
T314 |
1 |
| others[1] |
108 |
1 |
|
T4 |
3 |
|
T17 |
3 |
|
T218 |
1 |
| others[2] |
113 |
1 |
|
T4 |
4 |
|
T17 |
2 |
|
T261 |
2 |
| others[3] |
196 |
1 |
|
T4 |
5 |
|
T25 |
1 |
|
T17 |
2 |
| false |
57 |
1 |
|
T25 |
1 |
|
T380 |
1 |
|
T59 |
7 |
| true |
6288 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
269 |
1 |
|
T4 |
8 |
|
T45 |
1 |
|
T17 |
2 |
| others[1] |
219 |
1 |
|
T4 |
9 |
|
T7 |
1 |
|
T17 |
1 |
| others[2] |
238 |
1 |
|
T4 |
11 |
|
T39 |
1 |
|
T17 |
1 |
| others[3] |
400 |
1 |
|
T4 |
18 |
|
T25 |
1 |
|
T40 |
1 |
| false |
115 |
1 |
|
T4 |
6 |
|
T346 |
1 |
|
T59 |
2 |
| true |
5632 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1049 |
1 |
|
T4 |
21 |
|
T7 |
1 |
|
T25 |
1 |
| others[1] |
1091 |
1 |
|
T4 |
17 |
|
T16 |
1 |
|
T11 |
1 |
| others[2] |
1102 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
13 |
| others[3] |
1687 |
1 |
|
T1 |
1 |
|
T4 |
34 |
|
T20 |
3 |
| false |
598 |
1 |
|
T4 |
16 |
|
T108 |
1 |
|
T20 |
1 |
| true |
1346 |
1 |
|
T6 |
1 |
|
T89 |
1 |
|
T45 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
205 |
1 |
|
T4 |
12 |
|
T218 |
1 |
|
T59 |
11 |
| others[1] |
235 |
1 |
|
T4 |
9 |
|
T6 |
1 |
|
T39 |
1 |
| others[2] |
253 |
1 |
|
T4 |
10 |
|
T48 |
1 |
|
T17 |
1 |
| others[3] |
398 |
1 |
|
T1 |
1 |
|
T4 |
17 |
|
T25 |
1 |
| false |
102 |
1 |
|
T4 |
5 |
|
T19 |
1 |
|
T289 |
2 |
| true |
5680 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
48 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
240 |
1 |
|
T4 |
7 |
|
T17 |
1 |
|
T109 |
1 |
| others[1] |
210 |
1 |
|
T4 |
7 |
|
T289 |
1 |
|
T379 |
1 |
| others[2] |
236 |
1 |
|
T4 |
9 |
|
T17 |
1 |
|
T67 |
1 |
| others[3] |
372 |
1 |
|
T4 |
20 |
|
T25 |
1 |
|
T48 |
1 |
| false |
107 |
1 |
|
T4 |
6 |
|
T39 |
1 |
|
T218 |
1 |
| true |
5708 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1277 |
1 |
|
T2 |
1 |
|
T4 |
23 |
|
T20 |
1 |
| others[1] |
1245 |
1 |
|
T4 |
20 |
|
T21 |
1 |
|
T32 |
2 |
| others[2] |
1195 |
1 |
|
T4 |
16 |
|
T25 |
1 |
|
T108 |
1 |
| others[3] |
2043 |
1 |
|
T3 |
1 |
|
T4 |
34 |
|
T16 |
1 |
| false |
664 |
1 |
|
T4 |
8 |
|
T25 |
1 |
|
T90 |
1 |
| true |
449 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1273 |
1 |
|
T4 |
17 |
|
T20 |
1 |
|
T21 |
1 |
| others[1] |
1198 |
1 |
|
T4 |
19 |
|
T20 |
2 |
|
T21 |
1 |
| others[2] |
1226 |
1 |
|
T2 |
1 |
|
T4 |
20 |
|
T20 |
1 |
| others[3] |
2086 |
1 |
|
T3 |
1 |
|
T4 |
30 |
|
T7 |
1 |
| false |
674 |
1 |
|
T4 |
15 |
|
T20 |
1 |
|
T21 |
1 |
| true |
416 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
118 |
1 |
|
T4 |
4 |
|
T25 |
1 |
|
T17 |
3 |
| others[1] |
104 |
1 |
|
T4 |
4 |
|
T261 |
2 |
|
T316 |
1 |
| others[2] |
116 |
1 |
|
T4 |
6 |
|
T17 |
1 |
|
T218 |
2 |
| others[3] |
164 |
1 |
|
T4 |
3 |
|
T25 |
1 |
|
T48 |
1 |
| false |
48 |
1 |
|
T4 |
2 |
|
T59 |
3 |
|
T103 |
1 |
| true |
6323 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
238 |
1 |
|
T4 |
10 |
|
T45 |
1 |
|
T287 |
1 |
| others[1] |
247 |
1 |
|
T4 |
10 |
|
T47 |
1 |
|
T39 |
1 |
| others[2] |
242 |
1 |
|
T4 |
5 |
|
T25 |
1 |
|
T17 |
1 |
| others[3] |
394 |
1 |
|
T4 |
19 |
|
T17 |
2 |
|
T218 |
2 |
| false |
114 |
1 |
|
T4 |
4 |
|
T25 |
1 |
|
T41 |
1 |
| true |
5638 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1019 |
1 |
|
T4 |
19 |
|
T16 |
1 |
|
T25 |
1 |
| others[1] |
1057 |
1 |
|
T4 |
16 |
|
T20 |
3 |
|
T21 |
1 |
| others[2] |
1042 |
1 |
|
T1 |
1 |
|
T4 |
27 |
|
T20 |
2 |
| others[3] |
1822 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
31 |
| false |
503 |
1 |
|
T4 |
8 |
|
T108 |
1 |
|
T61 |
1 |
| true |
1430 |
1 |
|
T7 |
1 |
|
T11 |
1 |
|
T89 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
237 |
1 |
|
T1 |
1 |
|
T4 |
8 |
|
T17 |
1 |
| others[1] |
224 |
1 |
|
T4 |
7 |
|
T17 |
2 |
|
T287 |
1 |
| others[2] |
243 |
1 |
|
T4 |
6 |
|
T49 |
1 |
|
T17 |
1 |
| others[3] |
409 |
1 |
|
T4 |
17 |
|
T48 |
1 |
|
T40 |
1 |
| false |
117 |
1 |
|
T4 |
7 |
|
T73 |
1 |
|
T67 |
1 |
| true |
5643 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
56 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
192 |
1 |
|
T4 |
9 |
|
T17 |
1 |
|
T67 |
2 |
| others[1] |
219 |
1 |
|
T4 |
9 |
|
T48 |
1 |
|
T218 |
1 |
| others[2] |
233 |
1 |
|
T4 |
7 |
|
T83 |
1 |
|
T214 |
1 |
| others[3] |
381 |
1 |
|
T4 |
18 |
|
T17 |
2 |
|
T109 |
1 |
| false |
108 |
1 |
|
T4 |
5 |
|
T17 |
1 |
|
T19 |
1 |
| true |
5740 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1248 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
21 |
| others[1] |
1236 |
1 |
|
T4 |
15 |
|
T7 |
1 |
|
T20 |
2 |
| others[2] |
1272 |
1 |
|
T4 |
19 |
|
T25 |
1 |
|
T108 |
1 |
| others[3] |
2013 |
1 |
|
T4 |
34 |
|
T16 |
1 |
|
T25 |
1 |
| false |
663 |
1 |
|
T4 |
12 |
|
T20 |
2 |
|
T21 |
1 |
| true |
441 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1228 |
1 |
|
T3 |
1 |
|
T4 |
14 |
|
T16 |
1 |
| others[1] |
1189 |
1 |
|
T2 |
1 |
|
T4 |
14 |
|
T25 |
1 |
| others[2] |
1231 |
1 |
|
T4 |
16 |
|
T108 |
1 |
|
T20 |
1 |
| others[3] |
2163 |
1 |
|
T4 |
46 |
|
T20 |
3 |
|
T21 |
3 |
| false |
633 |
1 |
|
T4 |
11 |
|
T20 |
2 |
|
T22 |
1 |
| true |
429 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
103 |
1 |
|
T4 |
3 |
|
T261 |
2 |
|
T59 |
2 |
| others[1] |
103 |
1 |
|
T4 |
9 |
|
T17 |
2 |
|
T218 |
1 |
| others[2] |
92 |
1 |
|
T4 |
2 |
|
T25 |
1 |
|
T39 |
1 |
| others[3] |
202 |
1 |
|
T4 |
5 |
|
T25 |
1 |
|
T17 |
4 |
| false |
62 |
1 |
|
T4 |
2 |
|
T17 |
1 |
|
T218 |
1 |
| true |
6311 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
231 |
1 |
|
T4 |
12 |
|
T6 |
1 |
|
T45 |
1 |
| others[1] |
222 |
1 |
|
T4 |
7 |
|
T287 |
1 |
|
T67 |
1 |
| others[2] |
250 |
1 |
|
T1 |
1 |
|
T4 |
11 |
|
T47 |
1 |
| others[3] |
369 |
1 |
|
T4 |
20 |
|
T7 |
1 |
|
T25 |
1 |
| false |
108 |
1 |
|
T4 |
4 |
|
T343 |
1 |
|
T379 |
1 |
| true |
5693 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
47 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1032 |
1 |
|
T2 |
1 |
|
T4 |
26 |
|
T25 |
1 |
| others[1] |
1068 |
1 |
|
T4 |
19 |
|
T25 |
1 |
|
T20 |
2 |
| others[2] |
1074 |
1 |
|
T3 |
1 |
|
T4 |
23 |
|
T20 |
1 |
| others[3] |
1781 |
1 |
|
T4 |
24 |
|
T7 |
1 |
|
T20 |
2 |
| false |
531 |
1 |
|
T4 |
9 |
|
T16 |
1 |
|
T108 |
1 |
| true |
1387 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
245 |
1 |
|
T4 |
8 |
|
T17 |
1 |
|
T198 |
1 |
| others[1] |
242 |
1 |
|
T4 |
11 |
|
T41 |
1 |
|
T19 |
1 |
| others[2] |
225 |
1 |
|
T4 |
6 |
|
T73 |
1 |
|
T74 |
1 |
| others[3] |
395 |
1 |
|
T4 |
20 |
|
T7 |
1 |
|
T49 |
1 |
| false |
110 |
1 |
|
T4 |
3 |
|
T261 |
1 |
|
T214 |
1 |
| true |
5656 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
249 |
1 |
|
T4 |
8 |
|
T25 |
1 |
|
T48 |
1 |
| others[1] |
219 |
1 |
|
T4 |
11 |
|
T17 |
1 |
|
T382 |
1 |
| others[2] |
215 |
1 |
|
T4 |
10 |
|
T17 |
2 |
|
T83 |
1 |
| others[3] |
358 |
1 |
|
T4 |
14 |
|
T25 |
1 |
|
T17 |
1 |
| false |
104 |
1 |
|
T4 |
4 |
|
T19 |
1 |
|
T59 |
5 |
| true |
5728 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1258 |
1 |
|
T4 |
18 |
|
T20 |
1 |
|
T32 |
5 |
| others[1] |
1221 |
1 |
|
T4 |
23 |
|
T21 |
1 |
|
T90 |
1 |
| others[2] |
1228 |
1 |
|
T2 |
1 |
|
T4 |
17 |
|
T25 |
1 |
| others[3] |
2065 |
1 |
|
T4 |
34 |
|
T16 |
1 |
|
T25 |
1 |
| false |
654 |
1 |
|
T3 |
1 |
|
T4 |
9 |
|
T108 |
1 |
| true |
447 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1251 |
1 |
|
T4 |
25 |
|
T16 |
1 |
|
T25 |
1 |
| others[1] |
1208 |
1 |
|
T4 |
18 |
|
T6 |
1 |
|
T25 |
1 |
| others[2] |
1227 |
1 |
|
T4 |
19 |
|
T90 |
1 |
|
T47 |
1 |
| others[3] |
2093 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
34 |
| false |
674 |
1 |
|
T4 |
5 |
|
T20 |
1 |
|
T21 |
1 |
| true |
420 |
1 |
|
T1 |
1 |
|
T7 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
90 |
1 |
|
T4 |
1 |
|
T380 |
1 |
|
T59 |
3 |
| others[1] |
117 |
1 |
|
T4 |
4 |
|
T25 |
1 |
|
T17 |
2 |
| others[2] |
106 |
1 |
|
T4 |
7 |
|
T25 |
1 |
|
T17 |
2 |
| others[3] |
169 |
1 |
|
T4 |
7 |
|
T17 |
4 |
|
T218 |
2 |
| false |
51 |
1 |
|
T4 |
1 |
|
T103 |
2 |
|
T386 |
2 |
| true |
6340 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
248 |
1 |
|
T4 |
7 |
|
T25 |
1 |
|
T17 |
2 |
| others[1] |
231 |
1 |
|
T4 |
10 |
|
T17 |
2 |
|
T218 |
1 |
| others[2] |
207 |
1 |
|
T4 |
5 |
|
T47 |
1 |
|
T73 |
1 |
| others[3] |
396 |
1 |
|
T4 |
17 |
|
T6 |
1 |
|
T48 |
1 |
| false |
104 |
1 |
|
T4 |
4 |
|
T17 |
1 |
|
T74 |
1 |
| true |
5687 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1052 |
1 |
|
T4 |
13 |
|
T20 |
1 |
|
T21 |
1 |
| others[1] |
996 |
1 |
|
T2 |
1 |
|
T4 |
25 |
|
T16 |
1 |
| others[2] |
1102 |
1 |
|
T4 |
24 |
|
T11 |
1 |
|
T20 |
1 |
| others[3] |
1770 |
1 |
|
T4 |
31 |
|
T20 |
4 |
|
T21 |
2 |
| false |
524 |
1 |
|
T3 |
1 |
|
T4 |
8 |
|
T108 |
1 |
| true |
1429 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
201 |
1 |
|
T4 |
12 |
|
T17 |
1 |
|
T343 |
1 |
| others[1] |
225 |
1 |
|
T4 |
9 |
|
T74 |
1 |
|
T198 |
1 |
| others[2] |
226 |
1 |
|
T4 |
12 |
|
T73 |
1 |
|
T41 |
1 |
| others[3] |
391 |
1 |
|
T4 |
14 |
|
T17 |
2 |
|
T224 |
1 |
| false |
129 |
1 |
|
T4 |
4 |
|
T17 |
1 |
|
T314 |
1 |
| true |
5701 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
206 |
1 |
|
T4 |
15 |
|
T17 |
2 |
|
T198 |
1 |
| others[1] |
237 |
1 |
|
T4 |
13 |
|
T25 |
1 |
|
T67 |
1 |
| others[2] |
256 |
1 |
|
T4 |
13 |
|
T83 |
1 |
|
T59 |
10 |
| others[3] |
364 |
1 |
|
T4 |
15 |
|
T25 |
1 |
|
T48 |
1 |
| false |
104 |
1 |
|
T4 |
3 |
|
T17 |
1 |
|
T218 |
1 |
| true |
5706 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1238 |
1 |
|
T4 |
25 |
|
T16 |
1 |
|
T20 |
2 |
| others[1] |
1268 |
1 |
|
T4 |
21 |
|
T108 |
1 |
|
T20 |
1 |
| others[2] |
1285 |
1 |
|
T2 |
1 |
|
T4 |
18 |
|
T25 |
1 |
| others[3] |
2031 |
1 |
|
T4 |
31 |
|
T25 |
1 |
|
T20 |
2 |
| false |
618 |
1 |
|
T3 |
1 |
|
T4 |
6 |
|
T20 |
1 |
| true |
433 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1282 |
1 |
|
T2 |
1 |
|
T4 |
24 |
|
T21 |
1 |
| others[1] |
1247 |
1 |
|
T3 |
1 |
|
T4 |
13 |
|
T7 |
1 |
| others[2] |
1275 |
1 |
|
T4 |
29 |
|
T25 |
2 |
|
T108 |
1 |
| others[3] |
1996 |
1 |
|
T4 |
31 |
|
T16 |
1 |
|
T20 |
2 |
| false |
642 |
1 |
|
T4 |
4 |
|
T21 |
1 |
|
T22 |
2 |
| true |
431 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
116 |
1 |
|
T4 |
6 |
|
T25 |
2 |
|
T17 |
2 |
| others[1] |
107 |
1 |
|
T4 |
4 |
|
T17 |
1 |
|
T59 |
2 |
| others[2] |
114 |
1 |
|
T4 |
4 |
|
T17 |
4 |
|
T379 |
1 |
| others[3] |
175 |
1 |
|
T4 |
5 |
|
T261 |
1 |
|
T382 |
1 |
| false |
54 |
1 |
|
T4 |
3 |
|
T17 |
1 |
|
T218 |
1 |
| true |
6307 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
239 |
1 |
|
T4 |
7 |
|
T6 |
1 |
|
T17 |
1 |
| others[1] |
239 |
1 |
|
T4 |
10 |
|
T45 |
1 |
|
T48 |
1 |
| others[2] |
242 |
1 |
|
T4 |
7 |
|
T17 |
1 |
|
T218 |
1 |
| others[3] |
401 |
1 |
|
T4 |
15 |
|
T17 |
2 |
|
T208 |
1 |
| false |
117 |
1 |
|
T4 |
6 |
|
T7 |
1 |
|
T82 |
1 |
| true |
5635 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1052 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
22 |
| others[1] |
1092 |
1 |
|
T4 |
21 |
|
T20 |
1 |
|
T21 |
3 |
| others[2] |
1011 |
1 |
|
T4 |
20 |
|
T20 |
2 |
|
T32 |
1 |
| others[3] |
1777 |
1 |
|
T1 |
1 |
|
T4 |
30 |
|
T16 |
1 |
| false |
549 |
1 |
|
T4 |
8 |
|
T89 |
1 |
|
T22 |
1 |
| true |
1392 |
1 |
|
T6 |
1 |
|
T7 |
1 |
|
T11 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |