Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
231 |
1 |
|
T4 |
5 |
|
T17 |
1 |
|
T218 |
1 |
| others[1] |
231 |
1 |
|
T4 |
10 |
|
T218 |
1 |
|
T289 |
1 |
| others[2] |
227 |
1 |
|
T4 |
10 |
|
T49 |
1 |
|
T73 |
1 |
| others[3] |
404 |
1 |
|
T4 |
21 |
|
T39 |
1 |
|
T17 |
2 |
| false |
121 |
1 |
|
T4 |
5 |
|
T381 |
1 |
|
T59 |
4 |
| true |
5659 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
181 |
1 |
|
T4 |
9 |
|
T83 |
1 |
|
T59 |
8 |
| others[1] |
207 |
1 |
|
T4 |
11 |
|
T198 |
1 |
|
T382 |
1 |
| others[2] |
211 |
1 |
|
T4 |
10 |
|
T314 |
1 |
|
T59 |
12 |
| others[3] |
398 |
1 |
|
T4 |
13 |
|
T40 |
1 |
|
T17 |
3 |
| false |
102 |
1 |
|
T4 |
4 |
|
T25 |
1 |
|
T379 |
1 |
| true |
5774 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1227 |
1 |
|
T4 |
16 |
|
T25 |
1 |
|
T21 |
1 |
| others[1] |
1268 |
1 |
|
T4 |
25 |
|
T20 |
4 |
|
T32 |
2 |
| others[2] |
1250 |
1 |
|
T3 |
1 |
|
T4 |
21 |
|
T7 |
1 |
| others[3] |
2071 |
1 |
|
T2 |
1 |
|
T4 |
26 |
|
T25 |
1 |
| false |
605 |
1 |
|
T4 |
13 |
|
T16 |
1 |
|
T108 |
1 |
| true |
452 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1171 |
1 |
|
T4 |
25 |
|
T25 |
1 |
|
T20 |
2 |
| others[1] |
1274 |
1 |
|
T2 |
1 |
|
T4 |
23 |
|
T25 |
1 |
| others[2] |
1314 |
1 |
|
T4 |
18 |
|
T16 |
1 |
|
T20 |
1 |
| others[3] |
2056 |
1 |
|
T3 |
1 |
|
T4 |
28 |
|
T7 |
1 |
| false |
631 |
1 |
|
T4 |
7 |
|
T108 |
1 |
|
T21 |
1 |
| true |
427 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
125 |
1 |
|
T4 |
10 |
|
T25 |
1 |
|
T261 |
1 |
| others[1] |
91 |
1 |
|
T4 |
1 |
|
T17 |
4 |
|
T261 |
1 |
| others[2] |
120 |
1 |
|
T4 |
7 |
|
T17 |
1 |
|
T218 |
1 |
| others[3] |
159 |
1 |
|
T4 |
5 |
|
T25 |
1 |
|
T17 |
2 |
| false |
46 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T59 |
2 |
| true |
6332 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
250 |
1 |
|
T4 |
11 |
|
T17 |
2 |
|
T83 |
1 |
| others[1] |
212 |
1 |
|
T4 |
4 |
|
T73 |
1 |
|
T40 |
1 |
| others[2] |
229 |
1 |
|
T4 |
12 |
|
T6 |
1 |
|
T25 |
1 |
| others[3] |
410 |
1 |
|
T4 |
13 |
|
T7 |
1 |
|
T45 |
1 |
| false |
121 |
1 |
|
T4 |
6 |
|
T25 |
1 |
|
T289 |
1 |
| true |
5651 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1069 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
20 |
| others[1] |
1033 |
1 |
|
T1 |
1 |
|
T4 |
20 |
|
T108 |
1 |
| others[2] |
1071 |
1 |
|
T4 |
20 |
|
T25 |
1 |
|
T20 |
1 |
| others[3] |
1762 |
1 |
|
T4 |
31 |
|
T6 |
1 |
|
T16 |
1 |
| false |
531 |
1 |
|
T4 |
10 |
|
T25 |
1 |
|
T20 |
1 |
| true |
1407 |
1 |
|
T7 |
1 |
|
T11 |
1 |
|
T89 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
254 |
1 |
|
T4 |
8 |
|
T17 |
1 |
|
T346 |
3 |
| others[1] |
230 |
1 |
|
T4 |
10 |
|
T287 |
1 |
|
T101 |
1 |
| others[2] |
236 |
1 |
|
T4 |
12 |
|
T6 |
1 |
|
T74 |
1 |
| others[3] |
393 |
1 |
|
T1 |
1 |
|
T4 |
12 |
|
T73 |
1 |
| false |
124 |
1 |
|
T4 |
2 |
|
T17 |
2 |
|
T346 |
2 |
| true |
5636 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
57 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
232 |
1 |
|
T4 |
11 |
|
T48 |
1 |
|
T198 |
1 |
| others[1] |
219 |
1 |
|
T4 |
14 |
|
T25 |
2 |
|
T17 |
1 |
| others[2] |
233 |
1 |
|
T4 |
13 |
|
T40 |
1 |
|
T67 |
1 |
| others[3] |
353 |
1 |
|
T4 |
14 |
|
T17 |
1 |
|
T19 |
1 |
| false |
119 |
1 |
|
T4 |
3 |
|
T17 |
1 |
|
T218 |
1 |
| true |
5717 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1265 |
1 |
|
T4 |
18 |
|
T7 |
1 |
|
T25 |
1 |
| others[1] |
1213 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
22 |
| others[2] |
1291 |
1 |
|
T4 |
23 |
|
T21 |
1 |
|
T32 |
2 |
| others[3] |
2043 |
1 |
|
T4 |
28 |
|
T16 |
1 |
|
T108 |
1 |
| false |
628 |
1 |
|
T4 |
10 |
|
T22 |
1 |
|
T17 |
1 |
| true |
433 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1226 |
1 |
|
T2 |
1 |
|
T4 |
26 |
|
T25 |
1 |
| others[1] |
1223 |
1 |
|
T4 |
18 |
|
T16 |
1 |
|
T20 |
2 |
| others[2] |
1209 |
1 |
|
T4 |
15 |
|
T25 |
1 |
|
T20 |
3 |
| others[3] |
2176 |
1 |
|
T3 |
1 |
|
T4 |
34 |
|
T20 |
2 |
| false |
608 |
1 |
|
T4 |
8 |
|
T22 |
4 |
|
T57 |
1 |
| true |
431 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
106 |
1 |
|
T4 |
4 |
|
T17 |
2 |
|
T218 |
1 |
| others[1] |
89 |
1 |
|
T4 |
5 |
|
T17 |
1 |
|
T59 |
2 |
| others[2] |
110 |
1 |
|
T4 |
4 |
|
T25 |
2 |
|
T17 |
1 |
| others[3] |
173 |
1 |
|
T4 |
7 |
|
T17 |
3 |
|
T218 |
1 |
| false |
65 |
1 |
|
T4 |
3 |
|
T17 |
1 |
|
T59 |
7 |
| true |
6330 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
230 |
1 |
|
T4 |
10 |
|
T198 |
1 |
|
T346 |
3 |
| others[1] |
237 |
1 |
|
T4 |
10 |
|
T25 |
1 |
|
T47 |
1 |
| others[2] |
238 |
1 |
|
T4 |
14 |
|
T6 |
1 |
|
T7 |
1 |
| others[3] |
379 |
1 |
|
T4 |
15 |
|
T39 |
1 |
|
T17 |
1 |
| false |
140 |
1 |
|
T4 |
6 |
|
T25 |
1 |
|
T17 |
1 |
| true |
5649 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1092 |
1 |
|
T4 |
22 |
|
T20 |
1 |
|
T32 |
4 |
| others[1] |
1041 |
1 |
|
T1 |
1 |
|
T4 |
19 |
|
T16 |
1 |
| others[2] |
989 |
1 |
|
T4 |
22 |
|
T6 |
1 |
|
T20 |
3 |
| others[3] |
1808 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
27 |
| false |
587 |
1 |
|
T4 |
11 |
|
T108 |
1 |
|
T21 |
1 |
| true |
1356 |
1 |
|
T7 |
1 |
|
T11 |
1 |
|
T89 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
232 |
1 |
|
T4 |
11 |
|
T25 |
1 |
|
T198 |
1 |
| others[1] |
207 |
1 |
|
T4 |
6 |
|
T101 |
1 |
|
T289 |
1 |
| others[2] |
253 |
1 |
|
T4 |
12 |
|
T7 |
1 |
|
T73 |
1 |
| others[3] |
399 |
1 |
|
T4 |
10 |
|
T6 |
1 |
|
T40 |
1 |
| false |
111 |
1 |
|
T4 |
5 |
|
T261 |
1 |
|
T343 |
1 |
| true |
5671 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
205 |
1 |
|
T4 |
6 |
|
T261 |
1 |
|
T316 |
1 |
| others[1] |
218 |
1 |
|
T4 |
6 |
|
T17 |
1 |
|
T218 |
1 |
| others[2] |
219 |
1 |
|
T4 |
9 |
|
T198 |
1 |
|
T289 |
1 |
| others[3] |
382 |
1 |
|
T4 |
25 |
|
T25 |
1 |
|
T17 |
2 |
| false |
114 |
1 |
|
T4 |
3 |
|
T59 |
7 |
|
T70 |
6 |
| true |
5735 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1241 |
1 |
|
T4 |
19 |
|
T25 |
1 |
|
T32 |
4 |
| others[1] |
1277 |
1 |
|
T3 |
1 |
|
T4 |
17 |
|
T20 |
2 |
| others[2] |
1267 |
1 |
|
T4 |
22 |
|
T6 |
1 |
|
T16 |
1 |
| others[3] |
2032 |
1 |
|
T2 |
1 |
|
T4 |
33 |
|
T20 |
4 |
| false |
619 |
1 |
|
T4 |
10 |
|
T108 |
1 |
|
T32 |
1 |
| true |
437 |
1 |
|
T1 |
1 |
|
T7 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1244 |
1 |
|
T4 |
20 |
|
T108 |
1 |
|
T20 |
1 |
| others[1] |
1239 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
19 |
| others[2] |
1261 |
1 |
|
T4 |
22 |
|
T20 |
3 |
|
T32 |
4 |
| others[3] |
2018 |
1 |
|
T4 |
26 |
|
T16 |
1 |
|
T20 |
2 |
| false |
681 |
1 |
|
T4 |
14 |
|
T25 |
2 |
|
T21 |
1 |
| true |
430 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
103 |
1 |
|
T4 |
2 |
|
T218 |
1 |
|
T261 |
1 |
| others[1] |
107 |
1 |
|
T4 |
4 |
|
T17 |
1 |
|
T218 |
1 |
| others[2] |
92 |
1 |
|
T4 |
3 |
|
T25 |
1 |
|
T39 |
1 |
| others[3] |
185 |
1 |
|
T4 |
4 |
|
T25 |
1 |
|
T17 |
3 |
| false |
52 |
1 |
|
T4 |
2 |
|
T17 |
1 |
|
T316 |
1 |
| true |
6334 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
238 |
1 |
|
T4 |
8 |
|
T73 |
1 |
|
T17 |
1 |
| others[1] |
239 |
1 |
|
T4 |
10 |
|
T17 |
2 |
|
T82 |
1 |
| others[2] |
232 |
1 |
|
T4 |
13 |
|
T316 |
1 |
|
T381 |
1 |
| others[3] |
408 |
1 |
|
T4 |
18 |
|
T6 |
1 |
|
T45 |
1 |
| false |
131 |
1 |
|
T4 |
3 |
|
T17 |
1 |
|
T41 |
1 |
| true |
5625 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1084 |
1 |
|
T4 |
14 |
|
T108 |
1 |
|
T11 |
1 |
| others[1] |
1054 |
1 |
|
T4 |
18 |
|
T25 |
1 |
|
T20 |
2 |
| others[2] |
1054 |
1 |
|
T4 |
27 |
|
T6 |
1 |
|
T7 |
1 |
| others[3] |
1753 |
1 |
|
T3 |
1 |
|
T4 |
29 |
|
T20 |
1 |
| false |
538 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
13 |
| true |
1390 |
1 |
|
T89 |
1 |
|
T45 |
1 |
|
T48 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
240 |
1 |
|
T4 |
15 |
|
T39 |
1 |
|
T17 |
2 |
| others[1] |
222 |
1 |
|
T4 |
6 |
|
T17 |
2 |
|
T101 |
1 |
| others[2] |
219 |
1 |
|
T4 |
10 |
|
T41 |
1 |
|
T261 |
1 |
| others[3] |
379 |
1 |
|
T4 |
14 |
|
T25 |
1 |
|
T48 |
1 |
| false |
105 |
1 |
|
T4 |
8 |
|
T224 |
1 |
|
T59 |
5 |
| true |
5708 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
216 |
1 |
|
T4 |
3 |
|
T17 |
1 |
|
T289 |
1 |
| others[1] |
216 |
1 |
|
T4 |
6 |
|
T39 |
1 |
|
T17 |
1 |
| others[2] |
239 |
1 |
|
T4 |
14 |
|
T218 |
1 |
|
T198 |
1 |
| others[3] |
414 |
1 |
|
T4 |
22 |
|
T40 |
1 |
|
T17 |
4 |
| false |
113 |
1 |
|
T4 |
2 |
|
T25 |
1 |
|
T59 |
7 |
| true |
5675 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1252 |
1 |
|
T4 |
24 |
|
T20 |
1 |
|
T21 |
1 |
| others[1] |
1311 |
1 |
|
T4 |
20 |
|
T25 |
1 |
|
T20 |
2 |
| others[2] |
1219 |
1 |
|
T2 |
1 |
|
T4 |
24 |
|
T16 |
1 |
| others[3] |
2009 |
1 |
|
T4 |
28 |
|
T108 |
1 |
|
T20 |
4 |
| false |
645 |
1 |
|
T3 |
1 |
|
T4 |
5 |
|
T32 |
1 |
| true |
437 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1306 |
1 |
|
T4 |
22 |
|
T20 |
2 |
|
T21 |
1 |
| others[1] |
1279 |
1 |
|
T4 |
20 |
|
T21 |
1 |
|
T32 |
1 |
| others[2] |
1225 |
1 |
|
T2 |
1 |
|
T4 |
23 |
|
T16 |
1 |
| others[3] |
2016 |
1 |
|
T3 |
1 |
|
T4 |
27 |
|
T7 |
1 |
| false |
622 |
1 |
|
T4 |
9 |
|
T25 |
1 |
|
T108 |
1 |
| true |
425 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
96 |
1 |
|
T4 |
4 |
|
T17 |
2 |
|
T316 |
1 |
| others[1] |
112 |
1 |
|
T4 |
4 |
|
T25 |
1 |
|
T17 |
2 |
| others[2] |
112 |
1 |
|
T4 |
5 |
|
T25 |
1 |
|
T17 |
1 |
| others[3] |
177 |
1 |
|
T4 |
9 |
|
T17 |
3 |
|
T289 |
2 |
| false |
57 |
1 |
|
T4 |
2 |
|
T261 |
1 |
|
T59 |
1 |
| true |
6319 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
256 |
1 |
|
T4 |
9 |
|
T49 |
1 |
|
T218 |
1 |
| others[1] |
227 |
1 |
|
T1 |
1 |
|
T4 |
7 |
|
T17 |
1 |
| others[2] |
231 |
1 |
|
T4 |
10 |
|
T17 |
2 |
|
T198 |
1 |
| others[3] |
398 |
1 |
|
T4 |
19 |
|
T7 |
1 |
|
T17 |
4 |
| false |
134 |
1 |
|
T4 |
7 |
|
T40 |
1 |
|
T218 |
1 |
| true |
5627 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
49 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1097 |
1 |
|
T4 |
22 |
|
T11 |
1 |
|
T21 |
2 |
| others[1] |
1068 |
1 |
|
T4 |
16 |
|
T25 |
1 |
|
T108 |
1 |
| others[2] |
1068 |
1 |
|
T2 |
1 |
|
T4 |
15 |
|
T7 |
1 |
| others[3] |
1743 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
34 |
| false |
523 |
1 |
|
T4 |
14 |
|
T20 |
1 |
|
T90 |
1 |
| true |
1374 |
1 |
|
T6 |
1 |
|
T47 |
1 |
|
T65 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
231 |
1 |
|
T4 |
12 |
|
T17 |
1 |
|
T261 |
1 |
| others[1] |
254 |
1 |
|
T4 |
20 |
|
T7 |
1 |
|
T17 |
1 |
| others[2] |
225 |
1 |
|
T4 |
7 |
|
T39 |
1 |
|
T224 |
1 |
| others[3] |
386 |
1 |
|
T4 |
17 |
|
T25 |
1 |
|
T41 |
1 |
| false |
106 |
1 |
|
T4 |
4 |
|
T73 |
1 |
|
T218 |
1 |
| true |
5671 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
209 |
1 |
|
T4 |
18 |
|
T289 |
1 |
|
T59 |
7 |
| others[1] |
227 |
1 |
|
T4 |
11 |
|
T218 |
1 |
|
T261 |
1 |
| others[2] |
212 |
1 |
|
T4 |
16 |
|
T39 |
1 |
|
T40 |
1 |
| others[3] |
376 |
1 |
|
T4 |
11 |
|
T17 |
2 |
|
T289 |
1 |
| false |
107 |
1 |
|
T4 |
4 |
|
T25 |
1 |
|
T67 |
1 |
| true |
5742 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1252 |
1 |
|
T4 |
21 |
|
T20 |
2 |
|
T32 |
3 |
| others[1] |
1186 |
1 |
|
T4 |
24 |
|
T25 |
1 |
|
T108 |
1 |
| others[2] |
1220 |
1 |
|
T4 |
22 |
|
T20 |
3 |
|
T90 |
1 |
| others[3] |
2108 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
27 |
| false |
655 |
1 |
|
T4 |
7 |
|
T32 |
3 |
|
T223 |
1 |
| true |
452 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T7 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |