Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.dis.val
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.dis.val
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.ecc_dis
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.ecc_dis
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.scramble_dis
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.scramble_dis
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1229 |
1 |
|
T3 |
1 |
|
T4 |
19 |
|
T20 |
2 |
| others[1] |
1222 |
1 |
|
T2 |
1 |
|
T4 |
20 |
|
T108 |
1 |
| others[2] |
1292 |
1 |
|
T4 |
16 |
|
T16 |
1 |
|
T25 |
1 |
| others[3] |
2053 |
1 |
|
T4 |
39 |
|
T20 |
3 |
|
T21 |
1 |
| false |
654 |
1 |
|
T4 |
7 |
|
T25 |
1 |
|
T20 |
1 |
| true |
423 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
114 |
1 |
|
T4 |
2 |
|
T25 |
1 |
|
T17 |
3 |
| others[1] |
115 |
1 |
|
T4 |
3 |
|
T48 |
1 |
|
T17 |
1 |
| others[2] |
80 |
1 |
|
T4 |
1 |
|
T17 |
3 |
|
T261 |
1 |
| others[3] |
178 |
1 |
|
T4 |
4 |
|
T25 |
1 |
|
T17 |
1 |
| false |
54 |
1 |
|
T4 |
3 |
|
T67 |
1 |
|
T59 |
3 |
| true |
6332 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
230 |
1 |
|
T4 |
4 |
|
T25 |
1 |
|
T224 |
1 |
| others[1] |
224 |
1 |
|
T4 |
12 |
|
T7 |
1 |
|
T45 |
1 |
| others[2] |
232 |
1 |
|
T4 |
10 |
|
T47 |
1 |
|
T39 |
1 |
| others[3] |
419 |
1 |
|
T4 |
18 |
|
T48 |
1 |
|
T17 |
3 |
| false |
152 |
1 |
|
T4 |
6 |
|
T381 |
1 |
|
T67 |
1 |
| true |
5616 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1061 |
1 |
|
T4 |
22 |
|
T16 |
1 |
|
T108 |
1 |
| others[1] |
1078 |
1 |
|
T1 |
1 |
|
T4 |
21 |
|
T20 |
4 |
| others[2] |
1065 |
1 |
|
T3 |
1 |
|
T4 |
22 |
|
T21 |
2 |
| others[3] |
1771 |
1 |
|
T2 |
1 |
|
T4 |
23 |
|
T6 |
1 |
| false |
568 |
1 |
|
T4 |
13 |
|
T20 |
1 |
|
T32 |
1 |
| true |
1330 |
1 |
|
T7 |
1 |
|
T11 |
1 |
|
T45 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
225 |
1 |
|
T4 |
14 |
|
T49 |
1 |
|
T17 |
1 |
| others[1] |
243 |
1 |
|
T4 |
10 |
|
T261 |
1 |
|
T109 |
1 |
| others[2] |
209 |
1 |
|
T4 |
14 |
|
T7 |
1 |
|
T48 |
1 |
| others[3] |
386 |
1 |
|
T4 |
15 |
|
T25 |
1 |
|
T17 |
2 |
| false |
113 |
1 |
|
T4 |
1 |
|
T290 |
1 |
|
T387 |
1 |
| true |
5697 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
206 |
1 |
|
T4 |
11 |
|
T17 |
1 |
|
T87 |
1 |
| others[1] |
235 |
1 |
|
T4 |
10 |
|
T40 |
1 |
|
T17 |
1 |
| others[2] |
235 |
1 |
|
T4 |
6 |
|
T19 |
1 |
|
T261 |
1 |
| others[3] |
387 |
1 |
|
T4 |
18 |
|
T25 |
2 |
|
T48 |
1 |
| false |
95 |
1 |
|
T4 |
6 |
|
T218 |
1 |
|
T314 |
1 |
| true |
5715 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1238 |
1 |
|
T2 |
1 |
|
T4 |
24 |
|
T20 |
2 |
| others[1] |
1253 |
1 |
|
T3 |
1 |
|
T4 |
19 |
|
T108 |
1 |
| others[2] |
1203 |
1 |
|
T4 |
16 |
|
T25 |
1 |
|
T20 |
1 |
| others[3] |
2051 |
1 |
|
T4 |
34 |
|
T16 |
1 |
|
T25 |
1 |
| false |
678 |
1 |
|
T4 |
8 |
|
T21 |
1 |
|
T32 |
3 |
| true |
450 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1247 |
1 |
|
T2 |
1 |
|
T4 |
19 |
|
T21 |
1 |
| others[1] |
1265 |
1 |
|
T4 |
20 |
|
T25 |
1 |
|
T20 |
2 |
| others[2] |
1281 |
1 |
|
T3 |
1 |
|
T4 |
23 |
|
T20 |
3 |
| others[3] |
2019 |
1 |
|
T4 |
31 |
|
T16 |
1 |
|
T108 |
1 |
| false |
639 |
1 |
|
T4 |
8 |
|
T25 |
1 |
|
T21 |
1 |
| true |
422 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
109 |
1 |
|
T4 |
2 |
|
T17 |
3 |
|
T218 |
1 |
| others[1] |
97 |
1 |
|
T4 |
5 |
|
T17 |
1 |
|
T59 |
2 |
| others[2] |
87 |
1 |
|
T4 |
2 |
|
T25 |
1 |
|
T17 |
1 |
| others[3] |
180 |
1 |
|
T4 |
5 |
|
T17 |
3 |
|
T218 |
1 |
| false |
52 |
1 |
|
T4 |
1 |
|
T25 |
1 |
|
T261 |
1 |
| true |
6348 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
241 |
1 |
|
T4 |
7 |
|
T40 |
1 |
|
T17 |
1 |
| others[1] |
249 |
1 |
|
T4 |
11 |
|
T17 |
1 |
|
T74 |
1 |
| others[2] |
245 |
1 |
|
T4 |
18 |
|
T6 |
1 |
|
T198 |
1 |
| others[3] |
393 |
1 |
|
T4 |
12 |
|
T7 |
1 |
|
T25 |
1 |
| false |
119 |
1 |
|
T4 |
4 |
|
T48 |
1 |
|
T17 |
1 |
| true |
5626 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1084 |
1 |
|
T1 |
1 |
|
T4 |
18 |
|
T25 |
1 |
| others[1] |
1063 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
20 |
| others[2] |
1020 |
1 |
|
T4 |
19 |
|
T16 |
1 |
|
T65 |
1 |
| others[3] |
1796 |
1 |
|
T4 |
36 |
|
T7 |
1 |
|
T20 |
3 |
| false |
534 |
1 |
|
T4 |
8 |
|
T25 |
1 |
|
T22 |
2 |
| true |
1376 |
1 |
|
T6 |
1 |
|
T89 |
1 |
|
T48 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
230 |
1 |
|
T4 |
11 |
|
T17 |
1 |
|
T261 |
1 |
| others[1] |
229 |
1 |
|
T4 |
12 |
|
T39 |
1 |
|
T289 |
1 |
| others[2] |
235 |
1 |
|
T4 |
10 |
|
T17 |
1 |
|
T218 |
1 |
| others[3] |
378 |
1 |
|
T4 |
23 |
|
T48 |
1 |
|
T73 |
1 |
| false |
110 |
1 |
|
T4 |
6 |
|
T59 |
5 |
|
T70 |
1 |
| true |
5691 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
228 |
1 |
|
T4 |
12 |
|
T39 |
1 |
|
T261 |
1 |
| others[1] |
207 |
1 |
|
T4 |
7 |
|
T25 |
1 |
|
T40 |
1 |
| others[2] |
208 |
1 |
|
T4 |
12 |
|
T17 |
1 |
|
T59 |
6 |
| others[3] |
360 |
1 |
|
T4 |
13 |
|
T17 |
1 |
|
T289 |
1 |
| false |
108 |
1 |
|
T4 |
4 |
|
T17 |
1 |
|
T382 |
1 |
| true |
5762 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1240 |
1 |
|
T3 |
1 |
|
T4 |
21 |
|
T25 |
1 |
| others[1] |
1284 |
1 |
|
T4 |
17 |
|
T21 |
1 |
|
T32 |
1 |
| others[2] |
1209 |
1 |
|
T2 |
1 |
|
T4 |
15 |
|
T25 |
1 |
| others[3] |
2063 |
1 |
|
T4 |
35 |
|
T16 |
1 |
|
T21 |
2 |
| false |
631 |
1 |
|
T4 |
13 |
|
T108 |
1 |
|
T20 |
3 |
| true |
446 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1230 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
18 |
| others[1] |
1266 |
1 |
|
T4 |
26 |
|
T25 |
1 |
|
T108 |
1 |
| others[2] |
1245 |
1 |
|
T4 |
12 |
|
T89 |
1 |
|
T32 |
3 |
| others[3] |
2054 |
1 |
|
T4 |
32 |
|
T20 |
1 |
|
T90 |
1 |
| false |
659 |
1 |
|
T4 |
13 |
|
T20 |
1 |
|
T32 |
1 |
| true |
419 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
121 |
1 |
|
T4 |
7 |
|
T48 |
1 |
|
T17 |
2 |
| others[1] |
104 |
1 |
|
T4 |
4 |
|
T17 |
1 |
|
T218 |
1 |
| others[2] |
106 |
1 |
|
T4 |
2 |
|
T17 |
2 |
|
T19 |
1 |
| others[3] |
169 |
1 |
|
T4 |
6 |
|
T25 |
1 |
|
T17 |
2 |
| false |
63 |
1 |
|
T4 |
5 |
|
T25 |
1 |
|
T17 |
1 |
| true |
6310 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
213 |
1 |
|
T4 |
13 |
|
T6 |
1 |
|
T17 |
1 |
| others[1] |
247 |
1 |
|
T4 |
14 |
|
T25 |
1 |
|
T45 |
1 |
| others[2] |
219 |
1 |
|
T4 |
4 |
|
T7 |
1 |
|
T287 |
1 |
| others[3] |
412 |
1 |
|
T4 |
10 |
|
T17 |
4 |
|
T82 |
1 |
| false |
113 |
1 |
|
T4 |
5 |
|
T198 |
1 |
|
T316 |
1 |
| true |
5669 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1002 |
1 |
|
T4 |
10 |
|
T20 |
2 |
|
T21 |
1 |
| others[1] |
1079 |
1 |
|
T4 |
17 |
|
T21 |
1 |
|
T32 |
3 |
| others[2] |
1062 |
1 |
|
T2 |
1 |
|
T4 |
20 |
|
T6 |
1 |
| others[3] |
1746 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
37 |
| false |
581 |
1 |
|
T4 |
17 |
|
T32 |
1 |
|
T22 |
2 |
| true |
1403 |
1 |
|
T7 |
1 |
|
T11 |
1 |
|
T89 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
225 |
1 |
|
T4 |
6 |
|
T40 |
1 |
|
T314 |
1 |
| others[1] |
246 |
1 |
|
T4 |
10 |
|
T17 |
1 |
|
T287 |
1 |
| others[2] |
230 |
1 |
|
T4 |
11 |
|
T17 |
1 |
|
T198 |
1 |
| others[3] |
362 |
1 |
|
T4 |
7 |
|
T25 |
2 |
|
T48 |
1 |
| false |
117 |
1 |
|
T4 |
8 |
|
T49 |
1 |
|
T41 |
1 |
| true |
5693 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
218 |
1 |
|
T4 |
12 |
|
T19 |
1 |
|
T316 |
1 |
| others[1] |
232 |
1 |
|
T4 |
5 |
|
T17 |
1 |
|
T261 |
1 |
| others[2] |
232 |
1 |
|
T4 |
12 |
|
T17 |
1 |
|
T289 |
1 |
| others[3] |
357 |
1 |
|
T4 |
22 |
|
T48 |
1 |
|
T40 |
1 |
| false |
121 |
1 |
|
T4 |
6 |
|
T17 |
1 |
|
T218 |
1 |
| true |
5713 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1253 |
1 |
|
T3 |
1 |
|
T4 |
23 |
|
T7 |
1 |
| others[1] |
1295 |
1 |
|
T4 |
20 |
|
T20 |
1 |
|
T21 |
1 |
| others[2] |
1220 |
1 |
|
T4 |
15 |
|
T16 |
1 |
|
T21 |
1 |
| others[3] |
1985 |
1 |
|
T2 |
1 |
|
T4 |
33 |
|
T25 |
1 |
| false |
670 |
1 |
|
T4 |
10 |
|
T25 |
1 |
|
T20 |
3 |
| true |
450 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1249 |
1 |
|
T4 |
20 |
|
T20 |
3 |
|
T21 |
1 |
| others[1] |
1225 |
1 |
|
T4 |
17 |
|
T20 |
2 |
|
T32 |
2 |
| others[2] |
1227 |
1 |
|
T3 |
1 |
|
T4 |
18 |
|
T16 |
1 |
| others[3] |
2129 |
1 |
|
T2 |
1 |
|
T4 |
33 |
|
T25 |
1 |
| false |
617 |
1 |
|
T4 |
13 |
|
T25 |
1 |
|
T20 |
1 |
| true |
426 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
111 |
1 |
|
T4 |
4 |
|
T17 |
2 |
|
T382 |
1 |
| others[1] |
99 |
1 |
|
T4 |
7 |
|
T17 |
1 |
|
T218 |
1 |
| others[2] |
110 |
1 |
|
T4 |
1 |
|
T25 |
2 |
|
T17 |
1 |
| others[3] |
170 |
1 |
|
T4 |
8 |
|
T17 |
3 |
|
T214 |
1 |
| false |
51 |
1 |
|
T4 |
3 |
|
T17 |
1 |
|
T59 |
2 |
| true |
6332 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
237 |
1 |
|
T4 |
7 |
|
T7 |
1 |
|
T25 |
1 |
| others[1] |
225 |
1 |
|
T4 |
15 |
|
T25 |
1 |
|
T74 |
1 |
| others[2] |
222 |
1 |
|
T4 |
10 |
|
T17 |
1 |
|
T224 |
1 |
| others[3] |
405 |
1 |
|
T4 |
16 |
|
T49 |
1 |
|
T73 |
1 |
| false |
129 |
1 |
|
T4 |
7 |
|
T67 |
1 |
|
T388 |
1 |
| true |
5655 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1061 |
1 |
|
T4 |
21 |
|
T108 |
1 |
|
T20 |
2 |
| others[1] |
1004 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
18 |
| others[2] |
1046 |
1 |
|
T4 |
25 |
|
T16 |
1 |
|
T11 |
1 |
| others[3] |
1766 |
1 |
|
T4 |
32 |
|
T25 |
2 |
|
T20 |
2 |
| false |
582 |
1 |
|
T2 |
1 |
|
T4 |
5 |
|
T90 |
1 |
| true |
1414 |
1 |
|
T6 |
1 |
|
T7 |
1 |
|
T45 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
258 |
1 |
|
T4 |
15 |
|
T17 |
1 |
|
T287 |
1 |
| others[1] |
243 |
1 |
|
T4 |
9 |
|
T6 |
1 |
|
T17 |
1 |
| others[2] |
219 |
1 |
|
T4 |
11 |
|
T17 |
1 |
|
T316 |
1 |
| others[3] |
363 |
1 |
|
T4 |
13 |
|
T74 |
1 |
|
T83 |
1 |
| false |
117 |
1 |
|
T4 |
7 |
|
T224 |
1 |
|
T101 |
1 |
| true |
5673 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
216 |
1 |
|
T4 |
10 |
|
T218 |
1 |
|
T261 |
1 |
| others[1] |
225 |
1 |
|
T4 |
7 |
|
T59 |
9 |
|
T70 |
14 |
| others[2] |
228 |
1 |
|
T4 |
12 |
|
T39 |
1 |
|
T214 |
1 |
| others[3] |
398 |
1 |
|
T4 |
18 |
|
T17 |
3 |
|
T218 |
1 |
| false |
115 |
1 |
|
T4 |
2 |
|
T17 |
1 |
|
T67 |
1 |
| true |
5691 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1276 |
1 |
|
T4 |
26 |
|
T32 |
1 |
|
T22 |
2 |
| others[1] |
1206 |
1 |
|
T4 |
17 |
|
T20 |
1 |
|
T21 |
1 |
| others[2] |
1219 |
1 |
|
T2 |
1 |
|
T4 |
21 |
|
T20 |
2 |
| others[3] |
2084 |
1 |
|
T4 |
26 |
|
T16 |
1 |
|
T20 |
3 |
| false |
631 |
1 |
|
T3 |
1 |
|
T4 |
11 |
|
T25 |
2 |
| true |
457 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9 |
1 |
|
T166 |
1 |
|
T389 |
1 |
|
T157 |
1 |
| others[1] |
7 |
1 |
|
T97 |
1 |
|
T390 |
1 |
|
T147 |
1 |
| others[2] |
5 |
1 |
|
T153 |
1 |
|
T169 |
1 |
|
T170 |
1 |
| others[3] |
13 |
1 |
|
T391 |
1 |
|
T175 |
1 |
|
T392 |
1 |
| false |
2 |
1 |
|
T243 |
1 |
|
T393 |
1 |
|
- |
- |
| true |
46 |
1 |
|
T141 |
1 |
|
T111 |
1 |
|
T145 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2 |
1 |
|
T394 |
1 |
|
T395 |
1 |
|
- |
- |
| others[1] |
3 |
1 |
|
T371 |
1 |
|
T396 |
1 |
|
T397 |
1 |
| others[2] |
2 |
1 |
|
T253 |
1 |
|
T398 |
1 |
|
- |
- |
| others[3] |
4 |
1 |
|
T15 |
1 |
|
T399 |
1 |
|
T400 |
1 |
| false |
10 |
1 |
|
T401 |
1 |
|
T402 |
1 |
|
T403 |
1 |
| true |
26 |
1 |
|
T181 |
1 |
|
T179 |
1 |
|
T404 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
3 |
1 |
|
T405 |
1 |
|
T406 |
1 |
|
T407 |
1 |
| others[1] |
1 |
1 |
|
T408 |
1 |
|
- |
- |
|
- |
- |
| others[2] |
1 |
1 |
|
T409 |
1 |
|
- |
- |
|
- |
- |
| others[3] |
3 |
1 |
|
T402 |
1 |
|
T410 |
1 |
|
T411 |
1 |
| false |
14 |
1 |
|
T253 |
1 |
|
T179 |
1 |
|
T394 |
1 |
| true |
25 |
1 |
|
T15 |
1 |
|
T181 |
1 |
|
T371 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |