Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10115 |
1 |
|
T2 |
1 |
|
T4 |
13 |
|
T108 |
1 |
| others[1] |
769 |
1 |
|
T3 |
1 |
|
T4 |
19 |
|
T32 |
1 |
| others[2] |
821 |
1 |
|
T4 |
20 |
|
T20 |
1 |
|
T21 |
1 |
| others[3] |
1324 |
1 |
|
T4 |
35 |
|
T16 |
1 |
|
T25 |
1 |
| false |
436 |
1 |
|
T4 |
14 |
|
T20 |
2 |
|
T32 |
1 |
| true |
535 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2380 |
1 |
|
T3 |
1 |
|
T4 |
15 |
|
T25 |
1 |
| others[1] |
2420 |
1 |
|
T2 |
1 |
|
T4 |
11 |
|
T16 |
1 |
| others[2] |
2338 |
1 |
|
T4 |
16 |
|
T25 |
1 |
|
T44 |
28 |
| others[3] |
3939 |
1 |
|
T4 |
15 |
|
T44 |
42 |
|
T20 |
3 |
| false |
1292 |
1 |
|
T4 |
5 |
|
T44 |
16 |
|
T46 |
5 |
| true |
1631 |
1 |
|
T1 |
1 |
|
T4 |
39 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9591 |
1 |
|
T1 |
1 |
|
T4 |
10 |
|
T6 |
1 |
| others[1] |
262 |
1 |
|
T4 |
11 |
|
T21 |
1 |
|
T17 |
1 |
| others[2] |
262 |
1 |
|
T4 |
8 |
|
T25 |
1 |
|
T33 |
1 |
| others[3] |
496 |
1 |
|
T4 |
16 |
|
T7 |
1 |
|
T16 |
1 |
| false |
135 |
1 |
|
T4 |
6 |
|
T25 |
1 |
|
T17 |
1 |
| true |
3254 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
50 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9838 |
1 |
|
T4 |
12 |
|
T25 |
2 |
|
T44 |
140 |
| others[1] |
460 |
1 |
|
T4 |
13 |
|
T20 |
1 |
|
T65 |
1 |
| others[2] |
464 |
1 |
|
T4 |
16 |
|
T20 |
1 |
|
T32 |
1 |
| others[3] |
752 |
1 |
|
T4 |
15 |
|
T6 |
1 |
|
T108 |
1 |
| false |
250 |
1 |
|
T4 |
2 |
|
T21 |
1 |
|
T17 |
1 |
| true |
2236 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9578 |
1 |
|
T4 |
16 |
|
T25 |
1 |
|
T44 |
140 |
| others[1] |
234 |
1 |
|
T4 |
6 |
|
T383 |
1 |
|
T281 |
1 |
| others[2] |
273 |
1 |
|
T4 |
7 |
|
T6 |
1 |
|
T73 |
1 |
| others[3] |
447 |
1 |
|
T4 |
10 |
|
T33 |
1 |
|
T17 |
2 |
| false |
134 |
1 |
|
T4 |
8 |
|
T17 |
2 |
|
T59 |
5 |
| true |
3334 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9568 |
1 |
|
T4 |
13 |
|
T44 |
140 |
|
T21 |
1 |
| others[1] |
258 |
1 |
|
T4 |
10 |
|
T17 |
1 |
|
T19 |
1 |
| others[2] |
260 |
1 |
|
T4 |
7 |
|
T16 |
1 |
|
T21 |
2 |
| others[3] |
406 |
1 |
|
T4 |
20 |
|
T21 |
1 |
|
T39 |
1 |
| false |
145 |
1 |
|
T4 |
5 |
|
T200 |
1 |
|
T314 |
1 |
| true |
3363 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10140 |
1 |
|
T4 |
26 |
|
T16 |
1 |
|
T25 |
1 |
| others[1] |
784 |
1 |
|
T4 |
17 |
|
T6 |
1 |
|
T108 |
1 |
| others[2] |
783 |
1 |
|
T4 |
18 |
|
T20 |
1 |
|
T32 |
1 |
| others[3] |
1358 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
26 |
| false |
417 |
1 |
|
T4 |
14 |
|
T20 |
1 |
|
T90 |
1 |
| true |
518 |
1 |
|
T1 |
1 |
|
T7 |
1 |
|
T25 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10082 |
1 |
|
T4 |
17 |
|
T44 |
140 |
|
T46 |
67 |
| others[1] |
845 |
1 |
|
T2 |
1 |
|
T4 |
14 |
|
T20 |
3 |
| others[2] |
757 |
1 |
|
T4 |
19 |
|
T25 |
1 |
|
T20 |
1 |
| others[3] |
1318 |
1 |
|
T3 |
1 |
|
T4 |
38 |
|
T16 |
1 |
| false |
433 |
1 |
|
T4 |
13 |
|
T108 |
1 |
|
T47 |
1 |
| true |
532 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2452 |
1 |
|
T2 |
1 |
|
T4 |
10 |
|
T25 |
2 |
| others[1] |
2395 |
1 |
|
T4 |
10 |
|
T44 |
32 |
|
T20 |
3 |
| others[2] |
2461 |
1 |
|
T4 |
10 |
|
T44 |
34 |
|
T20 |
1 |
| others[3] |
3932 |
1 |
|
T4 |
12 |
|
T16 |
1 |
|
T44 |
30 |
| false |
1198 |
1 |
|
T3 |
1 |
|
T4 |
5 |
|
T44 |
17 |
| true |
1529 |
1 |
|
T1 |
1 |
|
T4 |
54 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9598 |
1 |
|
T4 |
12 |
|
T44 |
140 |
|
T46 |
67 |
| others[1] |
275 |
1 |
|
T4 |
8 |
|
T7 |
1 |
|
T25 |
1 |
| others[2] |
269 |
1 |
|
T4 |
8 |
|
T21 |
2 |
|
T90 |
1 |
| others[3] |
458 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
16 |
| false |
148 |
1 |
|
T4 |
6 |
|
T67 |
1 |
|
T212 |
1 |
| true |
3219 |
1 |
|
T3 |
1 |
|
T4 |
51 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9813 |
1 |
|
T4 |
14 |
|
T44 |
140 |
|
T20 |
2 |
| others[1] |
469 |
1 |
|
T4 |
10 |
|
T21 |
2 |
|
T32 |
1 |
| others[2] |
491 |
1 |
|
T4 |
15 |
|
T16 |
1 |
|
T20 |
1 |
| others[3] |
764 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
15 |
| false |
243 |
1 |
|
T4 |
4 |
|
T25 |
1 |
|
T11 |
1 |
| true |
2187 |
1 |
|
T2 |
1 |
|
T4 |
43 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9586 |
1 |
|
T4 |
10 |
|
T44 |
140 |
|
T21 |
1 |
| others[1] |
300 |
1 |
|
T4 |
12 |
|
T48 |
1 |
|
T49 |
1 |
| others[2] |
244 |
1 |
|
T1 |
1 |
|
T4 |
9 |
|
T16 |
1 |
| others[3] |
481 |
1 |
|
T2 |
1 |
|
T4 |
16 |
|
T25 |
1 |
| false |
112 |
1 |
|
T4 |
3 |
|
T223 |
1 |
|
T19 |
1 |
| true |
3244 |
1 |
|
T3 |
1 |
|
T4 |
51 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9556 |
1 |
|
T4 |
5 |
|
T44 |
140 |
|
T46 |
67 |
| others[1] |
255 |
1 |
|
T4 |
7 |
|
T21 |
1 |
|
T19 |
1 |
| others[2] |
264 |
1 |
|
T4 |
7 |
|
T16 |
1 |
|
T21 |
1 |
| others[3] |
406 |
1 |
|
T4 |
17 |
|
T25 |
1 |
|
T108 |
1 |
| false |
133 |
1 |
|
T4 |
10 |
|
T40 |
1 |
|
T59 |
6 |
| true |
3353 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10112 |
1 |
|
T4 |
22 |
|
T6 |
1 |
|
T44 |
140 |
| others[1] |
829 |
1 |
|
T4 |
13 |
|
T25 |
1 |
|
T20 |
2 |
| others[2] |
807 |
1 |
|
T4 |
19 |
|
T108 |
1 |
|
T20 |
1 |
| others[3] |
1314 |
1 |
|
T3 |
1 |
|
T4 |
38 |
|
T16 |
1 |
| false |
413 |
1 |
|
T2 |
1 |
|
T4 |
9 |
|
T20 |
3 |
| true |
492 |
1 |
|
T1 |
1 |
|
T7 |
1 |
|
T25 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10107 |
1 |
|
T2 |
1 |
|
T4 |
24 |
|
T44 |
140 |
| others[1] |
736 |
1 |
|
T4 |
16 |
|
T25 |
1 |
|
T20 |
2 |
| others[2] |
804 |
1 |
|
T4 |
23 |
|
T20 |
1 |
|
T22 |
6 |
| others[3] |
1367 |
1 |
|
T4 |
29 |
|
T90 |
1 |
|
T32 |
5 |
| false |
417 |
1 |
|
T3 |
1 |
|
T4 |
9 |
|
T16 |
1 |
| true |
536 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2402 |
1 |
|
T4 |
7 |
|
T25 |
1 |
|
T44 |
31 |
| others[1] |
2313 |
1 |
|
T2 |
1 |
|
T4 |
10 |
|
T44 |
18 |
| others[2] |
2378 |
1 |
|
T4 |
14 |
|
T44 |
30 |
|
T20 |
2 |
| others[3] |
3981 |
1 |
|
T4 |
10 |
|
T16 |
1 |
|
T25 |
1 |
| false |
1335 |
1 |
|
T3 |
1 |
|
T4 |
5 |
|
T44 |
14 |
| true |
1558 |
1 |
|
T1 |
1 |
|
T4 |
55 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9603 |
1 |
|
T4 |
9 |
|
T44 |
140 |
|
T21 |
1 |
| others[1] |
267 |
1 |
|
T4 |
10 |
|
T108 |
1 |
|
T198 |
1 |
| others[2] |
277 |
1 |
|
T4 |
11 |
|
T48 |
1 |
|
T57 |
1 |
| others[3] |
447 |
1 |
|
T4 |
17 |
|
T21 |
1 |
|
T33 |
1 |
| false |
146 |
1 |
|
T4 |
6 |
|
T17 |
1 |
|
T223 |
1 |
| true |
3227 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9764 |
1 |
|
T4 |
9 |
|
T16 |
1 |
|
T44 |
140 |
| others[1] |
480 |
1 |
|
T4 |
8 |
|
T20 |
1 |
|
T89 |
1 |
| others[2] |
482 |
1 |
|
T4 |
11 |
|
T6 |
1 |
|
T20 |
1 |
| others[3] |
793 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
19 |
| false |
244 |
1 |
|
T4 |
5 |
|
T65 |
1 |
|
T383 |
1 |
| true |
2204 |
1 |
|
T2 |
1 |
|
T4 |
49 |
|
T108 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9593 |
1 |
|
T4 |
10 |
|
T44 |
140 |
|
T21 |
1 |
| others[1] |
284 |
1 |
|
T4 |
8 |
|
T73 |
1 |
|
T17 |
1 |
| others[2] |
263 |
1 |
|
T4 |
7 |
|
T25 |
1 |
|
T412 |
1 |
| others[3] |
480 |
1 |
|
T1 |
1 |
|
T4 |
20 |
|
T57 |
1 |
| false |
138 |
1 |
|
T4 |
8 |
|
T7 |
1 |
|
T21 |
1 |
| true |
3209 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
48 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9592 |
1 |
|
T4 |
7 |
|
T44 |
140 |
|
T46 |
67 |
| others[1] |
228 |
1 |
|
T4 |
8 |
|
T282 |
1 |
|
T261 |
1 |
| others[2] |
209 |
1 |
|
T4 |
9 |
|
T21 |
1 |
|
T281 |
1 |
| others[3] |
427 |
1 |
|
T2 |
1 |
|
T4 |
17 |
|
T90 |
1 |
| false |
129 |
1 |
|
T4 |
4 |
|
T25 |
1 |
|
T328 |
1 |
| true |
3382 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
56 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10128 |
1 |
|
T3 |
1 |
|
T4 |
16 |
|
T25 |
1 |
| others[1] |
786 |
1 |
|
T4 |
18 |
|
T90 |
1 |
|
T32 |
1 |
| others[2] |
814 |
1 |
|
T2 |
1 |
|
T4 |
21 |
|
T16 |
1 |
| others[3] |
1344 |
1 |
|
T4 |
38 |
|
T20 |
4 |
|
T32 |
2 |
| false |
374 |
1 |
|
T4 |
8 |
|
T108 |
1 |
|
T47 |
1 |
| true |
521 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10096 |
1 |
|
T4 |
16 |
|
T16 |
1 |
|
T44 |
140 |
| others[1] |
785 |
1 |
|
T2 |
1 |
|
T4 |
16 |
|
T20 |
3 |
| others[2] |
737 |
1 |
|
T4 |
21 |
|
T20 |
1 |
|
T21 |
1 |
| others[3] |
1392 |
1 |
|
T3 |
1 |
|
T4 |
35 |
|
T25 |
2 |
| false |
418 |
1 |
|
T4 |
13 |
|
T22 |
1 |
|
T66 |
1 |
| true |
539 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2331 |
1 |
|
T3 |
1 |
|
T4 |
9 |
|
T108 |
1 |
| others[1] |
2378 |
1 |
|
T4 |
13 |
|
T44 |
40 |
|
T21 |
1 |
| others[2] |
2419 |
1 |
|
T4 |
8 |
|
T16 |
1 |
|
T25 |
1 |
| others[3] |
4051 |
1 |
|
T4 |
14 |
|
T25 |
1 |
|
T44 |
39 |
| false |
1205 |
1 |
|
T2 |
1 |
|
T4 |
4 |
|
T44 |
14 |
| true |
1583 |
1 |
|
T1 |
1 |
|
T4 |
53 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9593 |
1 |
|
T4 |
9 |
|
T25 |
1 |
|
T44 |
140 |
| others[1] |
258 |
1 |
|
T4 |
8 |
|
T33 |
1 |
|
T218 |
1 |
| others[2] |
287 |
1 |
|
T4 |
13 |
|
T61 |
1 |
|
T57 |
1 |
| others[3] |
472 |
1 |
|
T4 |
18 |
|
T16 |
1 |
|
T45 |
1 |
| false |
144 |
1 |
|
T1 |
1 |
|
T4 |
8 |
|
T21 |
1 |
| true |
3213 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
45 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9756 |
1 |
|
T4 |
8 |
|
T7 |
1 |
|
T44 |
140 |
| others[1] |
498 |
1 |
|
T4 |
13 |
|
T20 |
1 |
|
T21 |
1 |
| others[2] |
469 |
1 |
|
T2 |
1 |
|
T4 |
12 |
|
T25 |
2 |
| others[3] |
799 |
1 |
|
T4 |
17 |
|
T11 |
1 |
|
T20 |
1 |
| false |
251 |
1 |
|
T4 |
6 |
|
T16 |
1 |
|
T47 |
1 |
| true |
2194 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
45 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9581 |
1 |
|
T4 |
8 |
|
T6 |
1 |
|
T25 |
1 |
| others[1] |
258 |
1 |
|
T4 |
12 |
|
T17 |
2 |
|
T74 |
1 |
| others[2] |
273 |
1 |
|
T4 |
10 |
|
T21 |
1 |
|
T61 |
1 |
| others[3] |
409 |
1 |
|
T2 |
1 |
|
T4 |
22 |
|
T16 |
1 |
| false |
151 |
1 |
|
T4 |
3 |
|
T21 |
2 |
|
T281 |
1 |
| true |
3295 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
46 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9560 |
1 |
|
T4 |
8 |
|
T44 |
140 |
|
T46 |
67 |
| others[1] |
274 |
1 |
|
T4 |
13 |
|
T21 |
2 |
|
T17 |
1 |
| others[2] |
243 |
1 |
|
T4 |
9 |
|
T57 |
1 |
|
T282 |
1 |
| others[3] |
407 |
1 |
|
T4 |
19 |
|
T16 |
1 |
|
T21 |
1 |
| false |
124 |
1 |
|
T4 |
8 |
|
T281 |
1 |
|
T40 |
1 |
| true |
3359 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10161 |
1 |
|
T4 |
26 |
|
T44 |
140 |
|
T20 |
1 |
| others[1] |
758 |
1 |
|
T2 |
1 |
|
T4 |
17 |
|
T25 |
1 |
| others[2] |
824 |
1 |
|
T4 |
21 |
|
T16 |
1 |
|
T20 |
2 |
| others[3] |
1328 |
1 |
|
T3 |
1 |
|
T4 |
24 |
|
T25 |
1 |
| false |
386 |
1 |
|
T4 |
13 |
|
T32 |
1 |
|
T22 |
1 |
| true |
510 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10141 |
1 |
|
T3 |
1 |
|
T4 |
26 |
|
T44 |
140 |
| others[1] |
773 |
1 |
|
T4 |
10 |
|
T20 |
3 |
|
T22 |
2 |
| others[2] |
845 |
1 |
|
T4 |
11 |
|
T16 |
1 |
|
T108 |
1 |
| others[3] |
1280 |
1 |
|
T2 |
1 |
|
T4 |
43 |
|
T25 |
1 |
| false |
408 |
1 |
|
T4 |
11 |
|
T90 |
1 |
|
T32 |
2 |
| true |
520 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2374 |
1 |
|
T2 |
1 |
|
T4 |
5 |
|
T25 |
1 |
| others[1] |
2309 |
1 |
|
T4 |
11 |
|
T25 |
1 |
|
T108 |
1 |
| others[2] |
2377 |
1 |
|
T4 |
8 |
|
T44 |
25 |
|
T21 |
1 |
| others[3] |
4006 |
1 |
|
T3 |
1 |
|
T4 |
19 |
|
T16 |
1 |
| false |
1314 |
1 |
|
T4 |
3 |
|
T44 |
20 |
|
T20 |
1 |
| true |
1587 |
1 |
|
T1 |
1 |
|
T4 |
55 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9593 |
1 |
|
T4 |
8 |
|
T16 |
1 |
|
T44 |
140 |
| others[1] |
276 |
1 |
|
T4 |
6 |
|
T21 |
1 |
|
T39 |
1 |
| others[2] |
269 |
1 |
|
T4 |
8 |
|
T108 |
1 |
|
T17 |
1 |
| others[3] |
476 |
1 |
|
T4 |
23 |
|
T7 |
1 |
|
T21 |
2 |
| false |
138 |
1 |
|
T4 |
6 |
|
T40 |
1 |
|
T17 |
2 |
| true |
3215 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |