Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9801 |
1 |
|
T4 |
8 |
|
T44 |
140 |
|
T11 |
1 |
| others[1] |
440 |
1 |
|
T2 |
1 |
|
T4 |
10 |
|
T20 |
1 |
| others[2] |
474 |
1 |
|
T4 |
11 |
|
T25 |
1 |
|
T21 |
1 |
| others[3] |
793 |
1 |
|
T3 |
1 |
|
T4 |
13 |
|
T16 |
1 |
| false |
267 |
1 |
|
T4 |
6 |
|
T21 |
1 |
|
T32 |
1 |
| true |
2192 |
1 |
|
T1 |
1 |
|
T4 |
53 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9585 |
1 |
|
T4 |
2 |
|
T44 |
140 |
|
T90 |
1 |
| others[1] |
271 |
1 |
|
T4 |
13 |
|
T21 |
1 |
|
T33 |
1 |
| others[2] |
262 |
1 |
|
T2 |
1 |
|
T4 |
11 |
|
T49 |
1 |
| others[3] |
440 |
1 |
|
T4 |
20 |
|
T16 |
1 |
|
T25 |
2 |
| false |
153 |
1 |
|
T4 |
7 |
|
T343 |
1 |
|
T59 |
5 |
| true |
3256 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
48 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9587 |
1 |
|
T4 |
12 |
|
T44 |
140 |
|
T46 |
67 |
| others[1] |
252 |
1 |
|
T4 |
11 |
|
T21 |
1 |
|
T90 |
1 |
| others[2] |
260 |
1 |
|
T2 |
1 |
|
T4 |
9 |
|
T21 |
2 |
| others[3] |
415 |
1 |
|
T4 |
15 |
|
T61 |
1 |
|
T85 |
1 |
| false |
150 |
1 |
|
T4 |
7 |
|
T17 |
2 |
|
T289 |
1 |
| true |
3303 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
47 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10087 |
1 |
|
T4 |
15 |
|
T108 |
1 |
|
T44 |
140 |
| others[1] |
839 |
1 |
|
T4 |
20 |
|
T20 |
2 |
|
T32 |
2 |
| others[2] |
817 |
1 |
|
T4 |
21 |
|
T20 |
1 |
|
T21 |
1 |
| others[3] |
1313 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
35 |
| false |
384 |
1 |
|
T4 |
10 |
|
T32 |
1 |
|
T22 |
3 |
| true |
527 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10118 |
1 |
|
T2 |
1 |
|
T4 |
22 |
|
T108 |
1 |
| others[1] |
838 |
1 |
|
T4 |
22 |
|
T20 |
1 |
|
T32 |
1 |
| others[2] |
780 |
1 |
|
T4 |
15 |
|
T16 |
1 |
|
T20 |
2 |
| others[3] |
1330 |
1 |
|
T3 |
1 |
|
T4 |
31 |
|
T25 |
1 |
| false |
379 |
1 |
|
T4 |
11 |
|
T22 |
2 |
|
T84 |
3 |
| true |
522 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2410 |
1 |
|
T4 |
8 |
|
T44 |
33 |
|
T21 |
1 |
| others[1] |
2431 |
1 |
|
T4 |
9 |
|
T16 |
1 |
|
T25 |
1 |
| others[2] |
2319 |
1 |
|
T4 |
10 |
|
T44 |
17 |
|
T20 |
4 |
| others[3] |
4010 |
1 |
|
T3 |
1 |
|
T4 |
15 |
|
T25 |
1 |
| false |
1253 |
1 |
|
T2 |
1 |
|
T4 |
10 |
|
T108 |
1 |
| true |
1544 |
1 |
|
T1 |
1 |
|
T4 |
49 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9618 |
1 |
|
T4 |
12 |
|
T44 |
140 |
|
T46 |
67 |
| others[1] |
271 |
1 |
|
T4 |
7 |
|
T16 |
1 |
|
T108 |
1 |
| others[2] |
261 |
1 |
|
T4 |
7 |
|
T61 |
1 |
|
T17 |
1 |
| others[3] |
462 |
1 |
|
T4 |
16 |
|
T21 |
1 |
|
T45 |
1 |
| false |
148 |
1 |
|
T2 |
1 |
|
T4 |
6 |
|
T57 |
1 |
| true |
3207 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
53 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9782 |
1 |
|
T4 |
12 |
|
T44 |
140 |
|
T46 |
67 |
| others[1] |
463 |
1 |
|
T4 |
5 |
|
T6 |
1 |
|
T25 |
1 |
| others[2] |
516 |
1 |
|
T4 |
10 |
|
T108 |
1 |
|
T11 |
1 |
| others[3] |
719 |
1 |
|
T4 |
21 |
|
T7 |
1 |
|
T25 |
1 |
| false |
248 |
1 |
|
T2 |
1 |
|
T4 |
5 |
|
T21 |
2 |
| true |
2239 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
48 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9562 |
1 |
|
T4 |
4 |
|
T6 |
1 |
|
T44 |
140 |
| others[1] |
253 |
1 |
|
T4 |
5 |
|
T17 |
1 |
|
T223 |
1 |
| others[2] |
281 |
1 |
|
T2 |
1 |
|
T4 |
12 |
|
T16 |
1 |
| others[3] |
446 |
1 |
|
T4 |
26 |
|
T7 |
1 |
|
T17 |
1 |
| false |
154 |
1 |
|
T4 |
6 |
|
T57 |
1 |
|
T412 |
1 |
| true |
3271 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
48 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9593 |
1 |
|
T4 |
9 |
|
T44 |
140 |
|
T21 |
1 |
| others[1] |
251 |
1 |
|
T4 |
4 |
|
T25 |
1 |
|
T21 |
1 |
| others[2] |
240 |
1 |
|
T4 |
13 |
|
T383 |
1 |
|
T17 |
1 |
| others[3] |
436 |
1 |
|
T2 |
1 |
|
T4 |
17 |
|
T90 |
1 |
| false |
132 |
1 |
|
T4 |
4 |
|
T17 |
1 |
|
T218 |
1 |
| true |
3315 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
54 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10072 |
1 |
|
T4 |
13 |
|
T108 |
1 |
|
T44 |
140 |
| others[1] |
819 |
1 |
|
T4 |
18 |
|
T16 |
1 |
|
T20 |
1 |
| others[2] |
763 |
1 |
|
T3 |
1 |
|
T4 |
23 |
|
T32 |
3 |
| others[3] |
1375 |
1 |
|
T2 |
1 |
|
T4 |
34 |
|
T25 |
1 |
| false |
429 |
1 |
|
T4 |
13 |
|
T22 |
2 |
|
T17 |
1 |
| true |
509 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10127 |
1 |
|
T4 |
23 |
|
T6 |
1 |
|
T16 |
1 |
| others[1] |
773 |
1 |
|
T3 |
1 |
|
T4 |
12 |
|
T20 |
3 |
| others[2] |
804 |
1 |
|
T4 |
19 |
|
T25 |
1 |
|
T20 |
2 |
| others[3] |
1299 |
1 |
|
T2 |
1 |
|
T4 |
37 |
|
T20 |
1 |
| false |
422 |
1 |
|
T4 |
10 |
|
T21 |
1 |
|
T32 |
3 |
| true |
542 |
1 |
|
T1 |
1 |
|
T7 |
1 |
|
T25 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2372 |
1 |
|
T4 |
11 |
|
T108 |
1 |
|
T44 |
22 |
| others[1] |
2373 |
1 |
|
T4 |
2 |
|
T16 |
1 |
|
T44 |
26 |
| others[2] |
2443 |
1 |
|
T3 |
1 |
|
T4 |
10 |
|
T25 |
1 |
| others[3] |
3978 |
1 |
|
T4 |
14 |
|
T25 |
1 |
|
T44 |
48 |
| false |
1217 |
1 |
|
T2 |
1 |
|
T4 |
5 |
|
T44 |
17 |
| true |
1584 |
1 |
|
T1 |
1 |
|
T4 |
59 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9614 |
1 |
|
T4 |
9 |
|
T44 |
140 |
|
T21 |
2 |
| others[1] |
279 |
1 |
|
T4 |
11 |
|
T7 |
1 |
|
T25 |
2 |
| others[2] |
269 |
1 |
|
T4 |
9 |
|
T6 |
1 |
|
T21 |
1 |
| others[3] |
435 |
1 |
|
T4 |
12 |
|
T48 |
1 |
|
T223 |
1 |
| false |
148 |
1 |
|
T4 |
8 |
|
T17 |
1 |
|
T200 |
1 |
| true |
3222 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9818 |
1 |
|
T3 |
1 |
|
T4 |
9 |
|
T44 |
140 |
| others[1] |
471 |
1 |
|
T4 |
13 |
|
T25 |
1 |
|
T20 |
1 |
| others[2] |
443 |
1 |
|
T4 |
11 |
|
T20 |
1 |
|
T21 |
1 |
| others[3] |
749 |
1 |
|
T4 |
16 |
|
T16 |
1 |
|
T25 |
1 |
| false |
218 |
1 |
|
T4 |
3 |
|
T22 |
2 |
|
T17 |
2 |
| true |
2268 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
49 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9576 |
1 |
|
T2 |
1 |
|
T4 |
10 |
|
T44 |
140 |
| others[1] |
265 |
1 |
|
T4 |
9 |
|
T33 |
1 |
|
T383 |
1 |
| others[2] |
287 |
1 |
|
T4 |
8 |
|
T25 |
1 |
|
T281 |
1 |
| others[3] |
496 |
1 |
|
T4 |
16 |
|
T6 |
1 |
|
T25 |
1 |
| false |
108 |
1 |
|
T4 |
4 |
|
T39 |
1 |
|
T17 |
1 |
| true |
3235 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
54 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9588 |
1 |
|
T4 |
10 |
|
T44 |
140 |
|
T90 |
1 |
| others[1] |
262 |
1 |
|
T4 |
10 |
|
T17 |
2 |
|
T18 |
1 |
| others[2] |
240 |
1 |
|
T4 |
4 |
|
T25 |
1 |
|
T61 |
1 |
| others[3] |
435 |
1 |
|
T4 |
19 |
|
T39 |
1 |
|
T57 |
1 |
| false |
114 |
1 |
|
T4 |
4 |
|
T48 |
1 |
|
T85 |
1 |
| true |
3328 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10135 |
1 |
|
T3 |
1 |
|
T4 |
20 |
|
T25 |
2 |
| others[1] |
804 |
1 |
|
T2 |
1 |
|
T4 |
17 |
|
T20 |
1 |
| others[2] |
814 |
1 |
|
T4 |
13 |
|
T20 |
2 |
|
T21 |
1 |
| others[3] |
1290 |
1 |
|
T4 |
40 |
|
T16 |
1 |
|
T20 |
1 |
| false |
428 |
1 |
|
T4 |
11 |
|
T21 |
1 |
|
T61 |
1 |
| true |
496 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10133 |
1 |
|
T4 |
18 |
|
T16 |
1 |
|
T44 |
140 |
| others[1] |
799 |
1 |
|
T3 |
1 |
|
T4 |
21 |
|
T7 |
1 |
| others[2] |
751 |
1 |
|
T4 |
17 |
|
T108 |
1 |
|
T20 |
2 |
| others[3] |
1332 |
1 |
|
T2 |
1 |
|
T4 |
37 |
|
T20 |
2 |
| false |
435 |
1 |
|
T4 |
8 |
|
T32 |
1 |
|
T281 |
1 |
| true |
517 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T25 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2396 |
1 |
|
T4 |
10 |
|
T44 |
26 |
|
T46 |
16 |
| others[1] |
2381 |
1 |
|
T4 |
12 |
|
T16 |
1 |
|
T25 |
1 |
| others[2] |
2364 |
1 |
|
T4 |
6 |
|
T44 |
34 |
|
T20 |
2 |
| others[3] |
4041 |
1 |
|
T3 |
1 |
|
T4 |
22 |
|
T25 |
1 |
| false |
1223 |
1 |
|
T2 |
1 |
|
T4 |
2 |
|
T108 |
1 |
| true |
1562 |
1 |
|
T1 |
1 |
|
T4 |
49 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9594 |
1 |
|
T4 |
9 |
|
T7 |
1 |
|
T44 |
140 |
| others[1] |
311 |
1 |
|
T4 |
13 |
|
T25 |
1 |
|
T21 |
1 |
| others[2] |
268 |
1 |
|
T4 |
6 |
|
T48 |
1 |
|
T281 |
1 |
| others[3] |
526 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
19 |
| false |
131 |
1 |
|
T4 |
3 |
|
T16 |
1 |
|
T40 |
1 |
| true |
3137 |
1 |
|
T3 |
1 |
|
T4 |
51 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9785 |
1 |
|
T4 |
10 |
|
T44 |
140 |
|
T46 |
67 |
| others[1] |
465 |
1 |
|
T4 |
11 |
|
T11 |
1 |
|
T20 |
1 |
| others[2] |
461 |
1 |
|
T4 |
5 |
|
T25 |
1 |
|
T20 |
1 |
| others[3] |
766 |
1 |
|
T4 |
11 |
|
T7 |
1 |
|
T25 |
1 |
| false |
262 |
1 |
|
T3 |
1 |
|
T4 |
6 |
|
T16 |
1 |
| true |
2228 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
58 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9609 |
1 |
|
T4 |
14 |
|
T44 |
140 |
|
T46 |
67 |
| others[1] |
251 |
1 |
|
T4 |
12 |
|
T6 |
1 |
|
T61 |
1 |
| others[2] |
267 |
1 |
|
T4 |
9 |
|
T214 |
1 |
|
T328 |
1 |
| others[3] |
467 |
1 |
|
T4 |
11 |
|
T25 |
1 |
|
T21 |
2 |
| false |
126 |
1 |
|
T4 |
4 |
|
T200 |
1 |
|
T113 |
1 |
| true |
3247 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9578 |
1 |
|
T4 |
11 |
|
T44 |
140 |
|
T21 |
1 |
| others[1] |
246 |
1 |
|
T4 |
13 |
|
T200 |
1 |
|
T316 |
1 |
| others[2] |
261 |
1 |
|
T2 |
1 |
|
T4 |
11 |
|
T17 |
1 |
| others[3] |
418 |
1 |
|
T4 |
14 |
|
T21 |
1 |
|
T17 |
2 |
| false |
140 |
1 |
|
T4 |
3 |
|
T289 |
2 |
|
T116 |
1 |
| true |
3324 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
49 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10137 |
1 |
|
T2 |
1 |
|
T4 |
16 |
|
T44 |
140 |
| others[1] |
781 |
1 |
|
T4 |
23 |
|
T32 |
1 |
|
T22 |
4 |
| others[2] |
796 |
1 |
|
T4 |
16 |
|
T20 |
2 |
|
T21 |
1 |
| others[3] |
1340 |
1 |
|
T4 |
38 |
|
T6 |
1 |
|
T16 |
1 |
| false |
421 |
1 |
|
T3 |
1 |
|
T4 |
8 |
|
T108 |
1 |
| true |
492 |
1 |
|
T1 |
1 |
|
T7 |
1 |
|
T25 |
2 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |