Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	225509	1		T1	535		T2	365		T3	56
auto[FlashEraseBank]	237825	1		T1	651		T2	666		T3	8

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	255749	1		T1	1186		T3	28		T4	313
auto[FlashOpProgram]	188074	1		T2	1031		T3	25		T4	618
auto[FlashOpErase]	15511	1		T3	11		T4	56		T15	13
auto[FlashOpInvalid]	4000	1		T60	200		T118	200		T137	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	255749	1		T1	1186		T3	28		T4	313
op[FlashOpProgram]	188074	1		T2	1031		T3	25		T4	618
op[FlashOpErase]	15511	1		T3	11		T4	56		T15	13
read_erase_read	730	1		T3	1		T4	4		T15	1
read_prog_read	1398	1		T3	5		T4	2		T20	1

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Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	323962	1		T1	952		T2	731		T3	64
auto[FlashPartInfo]	135932	1		T1	234		T2	300		T4	888
auto[FlashPartInfo1]	850	1		T21	9		T48	5		T39	3
auto[FlashPartInfo2]	2590	1		T7	32		T20	1		T21	1

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	193010	1		T1	952		T3	28		T4	25
auto[FlashPartData]	auto[FlashOpProgram]	123311	1		T2	731		T3	25		T4	42
auto[FlashPartData]	auto[FlashOpErase]	3719	1		T3	11		T4	32		T25	1
auto[FlashPartData]	auto[FlashOpInvalid]	3922	1		T60	192		T118	192		T137	196
auto[FlashPartInfo]	auto[FlashOpRead]	60401	1		T1	234		T4	288		T6	242
auto[FlashPartInfo]	auto[FlashOpProgram]	63714	1		T2	300		T4	576		T15	288
auto[FlashPartInfo]	auto[FlashOpErase]	11753	1		T4	24		T15	13		T44	217
auto[FlashPartInfo]	auto[FlashOpInvalid]	64	1		T60	4		T118	8		T137	4
auto[FlashPartInfo1]	auto[FlashOpRead]	713	1		T21	9		T48	5		T39	3
auto[FlashPartInfo1]	auto[FlashOpProgram]	131	1		T60	2		T75	32		T123	32
auto[FlashPartInfo1]	auto[FlashOpErase]	2	1		T60	2		-	-		-	-
auto[FlashPartInfo1]	auto[FlashOpInvalid]	4	1		T60	4		-	-		-	-
auto[FlashPartInfo2]	auto[FlashOpRead]	1625	1		T7	32		T20	1		T21	1
auto[FlashPartInfo2]	auto[FlashOpProgram]	918	1		T48	9		T61	3		T39	10
auto[FlashPartInfo2]	auto[FlashOpErase]	37	1		T165	1		T70	1		T413	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	10	1		T413	2		T414	2		T415	2