Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
85.71	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	6	26	81.25

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	6	26	81.25	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	29532	1		T4	20		T44	440		T21	4
auto[1]	12	1		T290	1		T330	2		T331	1
auto[2]	222	1		T47	23		T24	8		T114	16
auto[3]	340	1		T45	1		T41	1		T82	1

---

Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7551	1		T4	5		T44	110		T21	1
evic_idx[1]	7533	1		T4	5		T44	110		T21	1
evic_idx[2]	7516	1		T4	5		T44	110		T21	1
evic_idx[3]	7506	1		T4	5		T44	110		T21	1

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	29037	1		T44	440		T46	196		T34	312
evic_op[2]	562	1		T45	1		T47	30		T41	1

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	6	26	81.25	6

Automatically Generated Cross Bins for evic_all_cross

Uncovered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
[evic_idx[0] , evic_idx[1]]	[evic_op[1]]	[auto[1] - auto[2]]	--	--	4
[evic_idx[2] , evic_idx[3]]	[evic_op[1]]	[auto[1]]	--	--	2

Covered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7190	1		T44	110		T46	49		T34	78
evic_idx[0]	evic_op[1]	auto[3]	96	1		T332	3		T333	6		T334	30
evic_idx[0]	evic_op[2]	auto[0]	72	1		T47	1		T119	2		T227	4
evic_idx[0]	evic_op[2]	auto[1]	3	1		T335	1		T336	1		T337	1
evic_idx[0]	evic_op[2]	auto[2]	51	1		T47	4		T114	5		T119	2
evic_idx[0]	evic_op[2]	auto[3]	11	1		T45	1		T101	1		T338	1
evic_idx[1]	evic_op[1]	auto[0]	7181	1		T44	110		T46	49		T34	78
evic_idx[1]	evic_op[1]	auto[3]	81	1		T332	1		T333	8		T334	24
evic_idx[1]	evic_op[2]	auto[0]	76	1		T47	5		T119	2		T138	2
evic_idx[1]	evic_op[2]	auto[1]	4	1		T330	1		T339	1		T336	1
evic_idx[1]	evic_op[2]	auto[2]	52	1		T47	6		T114	6		T119	3
evic_idx[1]	evic_op[2]	auto[3]	11	1		T101	1		T340	1		T341	1
evic_idx[2]	evic_op[1]	auto[0]	7183	1		T44	110		T46	49		T34	78
evic_idx[2]	evic_op[1]	auto[2]	1	1		T332	1		-	-		-	-
evic_idx[2]	evic_op[1]	auto[3]	64	1		T332	4		T333	9		T334	12
evic_idx[2]	evic_op[2]	auto[0]	79	1		T119	1		T342	1		T138	3
evic_idx[2]	evic_op[2]	auto[1]	2	1		T290	1		T330	1		-	-
evic_idx[2]	evic_op[2]	auto[2]	48	1		T47	10		T114	3		T119	3
evic_idx[2]	evic_op[2]	auto[3]	13	1		T41	1		T343	1		T344	1
evic_idx[3]	evic_op[1]	auto[0]	7186	1		T44	110		T46	49		T34	78
evic_idx[3]	evic_op[1]	auto[2]	5	1		T332	5		-	-		-	-
evic_idx[3]	evic_op[1]	auto[3]	50	1		T332	1		T333	4		T334	11
evic_idx[3]	evic_op[2]	auto[0]	74	1		T47	1		T119	1		T138	1
evic_idx[3]	evic_op[2]	auto[1]	3	1		T331	1		T336	1		T337	1
evic_idx[3]	evic_op[2]	auto[2]	49	1		T47	3		T114	2		T119	4
evic_idx[3]	evic_op[2]	auto[3]	14	1		T82	1		T267	1		T345	1