Summary for Variable instr_type_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
3 | 
0 | 
3 | 
100.00 | 
User Defined Bins for instr_type_cp
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others | 
5066 | 
1 | 
 | 
T26 | 
1 | 
 | 
T36 | 
130 | 
 | 
T37 | 
146 | 
| instr_types[0] | 
6694 | 
1 | 
 | 
T36 | 
143 | 
 | 
T37 | 
345 | 
 | 
T38 | 
319 | 
| instr_types[1] | 
4486631 | 
1 | 
 | 
T1 | 
16322 | 
 | 
T6 | 
16503 | 
 | 
T7 | 
16715 | 
Summary for Variable key_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for key_cp
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
4496528 | 
1 | 
 | 
T1 | 
16322 | 
 | 
T6 | 
16503 | 
 | 
T7 | 
16715 | 
| auto[1] | 
1863 | 
1 | 
 | 
T36 | 
188 | 
 | 
T37 | 
227 | 
 | 
T38 | 
224 | 
Summary for Cross key_instr_cross
Samples crossed: key_cp instr_type_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
6 | 
0 | 
6 | 
100.00 | 
 | 
Automatically Generated Cross Bins for key_instr_cross
Bins
| key_cp | instr_type_cp | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
others | 
4766 | 
1 | 
 | 
T26 | 
1 | 
 | 
T36 | 
89 | 
 | 
T37 | 
107 | 
| auto[0] | 
instr_types[0] | 
5913 | 
1 | 
 | 
T36 | 
117 | 
 | 
T37 | 
232 | 
 | 
T38 | 
183 | 
| auto[0] | 
instr_types[1] | 
4485849 | 
1 | 
 | 
T1 | 
16322 | 
 | 
T6 | 
16503 | 
 | 
T7 | 
16715 | 
| auto[1] | 
others | 
300 | 
1 | 
 | 
T36 | 
41 | 
 | 
T37 | 
39 | 
 | 
T360 | 
34 | 
| auto[1] | 
instr_types[0] | 
781 | 
1 | 
 | 
T36 | 
26 | 
 | 
T37 | 
113 | 
 | 
T38 | 
136 | 
| auto[1] | 
instr_types[1] | 
782 | 
1 | 
 | 
T36 | 
121 | 
 | 
T37 | 
75 | 
 | 
T38 | 
88 |