Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

---

Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	0	3	100.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for prog_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
prog_lvl[1]	48770	1		T78	2712		T79	4933		T80	1822
prog_lvl[2]	1827	1		T78	1		T80	910		T416	875
prog_lvl[3]	2	1		T80	1		T416	1		-	-

---

Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	13059	1		T1	2		T7	13		T224	53
rd_lvl[2]	26211	1		T1	8		T6	2		T224	89
rd_lvl[3]	18309	1		T1	16		T6	54		T224	69
rd_lvl[4]	11456	1		T1	21		T224	1045		T287	5
rd_lvl[5]	12508	1		T224	621		T287	9		T385	2
rd_lvl[6]	12797	1		T287	1		T417	1588		T215	87
rd_lvl[7]	11274	1		T223	961		T287	735		T385	786
rd_lvl[8]	5173	1		T223	519		T224	41		T215	810
rd_lvl[9]	3121	1		T57	647		T287	635		T385	474
rd_lvl[10]	5291	1		T57	259		T287	360		T418	556
rd_lvl[11]	7744	1		T418	264		T320	207		T212	331
rd_lvl[12]	7789	1		T1	824		T320	621		T212	882
rd_lvl[13]	5497	1		T1	337		T6	289		T287	10
rd_lvl[14]	5604	1		T6	793		T16	423		T113	428
rd_lvl[15]	3834	1		T7	559		T16	453		T381	488