Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	338377	1		T1	2401		T2	4125		T3	1
all_pins[1]	338377	1		T1	2401		T2	4125		T3	1
all_pins[2]	338377	1		T1	2401		T2	4125		T3	1
all_pins[3]	338377	1		T1	2401		T2	4125		T3	1
all_pins[4]	338377	1		T1	2401		T2	4125		T3	1
all_pins[5]	338377	1		T1	2401		T2	4125		T3	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1648627	1		T1	11962		T2	19595		T3	6
values[0x1]	381635	1		T1	2444		T2	5155		T6	3166
transitions[0x0=>0x1]	364818	1		T1	2425		T2	5155		T6	3059
transitions[0x1=>0x0]	364827	1		T1	2425		T2	5155		T6	3059

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	274500	1		T1	2401		T2	1		T3	1
all_pins[0]	values[0x1]	63877	1		T2	4124		T109	4324		T78	2215
all_pins[0]	transitions[0x0=>0x1]	63867	1		T2	4124		T109	4324		T78	2215
all_pins[0]	transitions[0x1=>0x0]	58386	1		T78	3617		T79	4933		T80	3644
all_pins[1]	values[0x0]	279981	1		T1	2401		T2	4125		T3	1
all_pins[1]	values[0x1]	58396	1		T78	3617		T79	4933		T80	3644
all_pins[1]	transitions[0x0=>0x1]	58382	1		T78	3617		T79	4933		T80	3644
all_pins[1]	transitions[0x1=>0x0]	8545	1		T1	25		T6	783		T7	1097
all_pins[2]	values[0x0]	329818	1		T1	2376		T2	4125		T3	1
all_pins[2]	values[0x1]	8559	1		T1	25		T6	783		T7	1097
all_pins[2]	transitions[0x0=>0x1]	7456	1		T1	25		T6	783		T7	828
all_pins[2]	transitions[0x1=>0x0]	150414	1		T1	1233		T6	1192		T7	792
all_pins[3]	values[0x0]	186860	1		T1	1168		T2	4125		T3	1
all_pins[3]	values[0x1]	151517	1		T1	1233		T6	1192		T7	1061
all_pins[3]	transitions[0x0=>0x1]	135861	1		T1	1214		T6	1085		T7	428
all_pins[3]	transitions[0x1=>0x0]	83572	1		T1	1167		T2	1031		T6	1084
all_pins[4]	values[0x0]	239149	1		T1	1215		T2	3094		T3	1
all_pins[4]	values[0x1]	99228	1		T1	1186		T2	1031		T6	1191
all_pins[4]	transitions[0x0=>0x1]	99216	1		T1	1186		T2	1031		T6	1191
all_pins[4]	transitions[0x1=>0x0]	46	1		T240	1		T241	2		T351	2
all_pins[5]	values[0x0]	338319	1		T1	2401		T2	4125		T3	1
all_pins[5]	values[0x1]	58	1		T240	1		T241	2		T242	2
all_pins[5]	transitions[0x0=>0x1]	36	1		T240	1		T241	1		T242	2
all_pins[5]	transitions[0x1=>0x0]	63864	1		T2	4124		T109	4324		T78	2215