Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	275	1		T240	7		T241	4		T242	7
all_values[1]	275	1		T240	7		T241	4		T242	7
all_values[2]	275	1		T240	7		T241	4		T242	7
all_values[3]	275	1		T240	7		T241	4		T242	7
all_values[4]	275	1		T240	7		T241	4		T242	7
all_values[5]	275	1		T240	7		T241	4		T242	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	927	1		T240	16		T241	14		T242	22
auto[1]	723	1		T240	26		T241	10		T242	20

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	680	1		T240	20		T241	11		T242	10
auto[1]	970	1		T240	22		T241	13		T242	32

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1021	1		T240	25		T241	14		T242	25
auto[1]	629	1		T240	17		T241	10		T242	17

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	36	0	36	100.00
Automatically Generated Cross Bins	36	0	36	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	62	1		T240	1		T241	1		T242	1
all_values[0]	auto[0]	auto[0]	auto[1]	26	1		T352	1		T351	1		T353	2
all_values[0]	auto[0]	auto[1]	auto[0]	56	1		T240	1		T241	1		T354	1
all_values[0]	auto[0]	auto[1]	auto[1]	27	1		T240	2		T242	1		T355	1
all_values[0]	auto[1]	auto[0]	auto[1]	56	1		T240	1		T241	2		T242	2
all_values[0]	auto[1]	auto[1]	auto[1]	48	1		T240	2		T242	3		T355	2
all_values[1]	auto[0]	auto[0]	auto[0]	76	1		T241	2		T242	2		T355	2
all_values[1]	auto[0]	auto[0]	auto[1]	30	1		T348	1		T356	1		T357	1
all_values[1]	auto[0]	auto[1]	auto[0]	53	1		T240	2		T241	1		T242	2
all_values[1]	auto[0]	auto[1]	auto[1]	22	1		T240	1		T242	2		T355	1
all_values[1]	auto[1]	auto[0]	auto[1]	44	1		T240	1		T241	1		T242	1
all_values[1]	auto[1]	auto[1]	auto[1]	50	1		T240	3		T355	1		T352	1
all_values[2]	auto[0]	auto[0]	auto[0]	62	1		T240	2		T241	1		T355	2
all_values[2]	auto[0]	auto[0]	auto[1]	25	1		T242	1		T354	1		T358	2
all_values[2]	auto[0]	auto[1]	auto[0]	48	1		T240	3		T241	1		T242	3
all_values[2]	auto[0]	auto[1]	auto[1]	29	1		T352	1		T354	1		T351	2
all_values[2]	auto[1]	auto[0]	auto[1]	66	1		T240	2		T242	3		T352	2
all_values[2]	auto[1]	auto[1]	auto[1]	45	1		T241	2		T355	2		T351	1
all_values[3]	auto[0]	auto[0]	auto[0]	56	1		T242	2		T352	3		T359	1
all_values[3]	auto[0]	auto[0]	auto[1]	38	1		T240	1		T241	1		T242	1
all_values[3]	auto[0]	auto[1]	auto[0]	48	1		T352	1		T359	2		T351	1
all_values[3]	auto[0]	auto[1]	auto[1]	21	1		T240	1		T241	1		T242	2
all_values[3]	auto[1]	auto[0]	auto[1]	64	1		T240	2		T241	1		T242	2
all_values[3]	auto[1]	auto[1]	auto[1]	48	1		T240	3		T241	1		T355	1
all_values[4]	auto[0]	auto[0]	auto[0]	64	1		T240	4		T241	3		T352	3
all_values[4]	auto[0]	auto[0]	auto[1]	31	1		T354	3		T351	3		T350	1
all_values[4]	auto[0]	auto[1]	auto[0]	56	1		T240	2		T241	1		T355	2
all_values[4]	auto[0]	auto[1]	auto[1]	25	1		T242	3		T351	2		T356	1
all_values[4]	auto[1]	auto[0]	auto[1]	61	1		T240	1		T242	1		T355	2
all_values[4]	auto[1]	auto[1]	auto[1]	38	1		T242	3		T351	1		T356	2
all_values[5]	auto[0]	auto[0]	auto[0]	55	1		T240	1		T352	2		T354	1
all_values[5]	auto[0]	auto[0]	auto[1]	36	1		T241	1		T242	4		T355	1
all_values[5]	auto[0]	auto[1]	auto[0]	44	1		T240	4		T354	3		T358	1
all_values[5]	auto[0]	auto[1]	auto[1]	31	1		T242	1		T355	1		T351	2
all_values[5]	auto[1]	auto[0]	auto[1]	75	1		T241	1		T242	2		T355	2
all_values[5]	auto[1]	auto[1]	auto[1]	34	1		T240	2		T241	2		T352	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal