Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	21412479	1		T1	15167		T2	2983		T3	8216
full_word	7307212	1		T1	10019		T2	440		T3	5802

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	28719381	1		T1	25186		T2	3423		T3	14018
auto[TlIntgErrCmd]	96	1		T44	3		T226	6		T227	8
auto[TlIntgErrData]	116	1		T44	1		T226	10		T227	6
auto[TlIntgErrBoth]	98	1		T44	6		T226	4		T227	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	24612728	1		T1	17625		T2	3155		T3	11866
auto[1]	4106963	1		T1	7561		T2	268		T3	2152

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	20809966	1		T1	14155		T2	2908		T3	7652
auto[TlIntgErrNone]	partial	auto[1]	602236	1		T1	1012		T2	75		T3	564
auto[TlIntgErrNone]	full_word	auto[0]	3802628	1		T1	3470		T2	247		T3	4214
auto[TlIntgErrNone]	full_word	auto[1]	3504551	1		T1	6549		T2	193		T3	1588
auto[TlIntgErrCmd]	partial	auto[0]	30	1		T44	2		T226	2		T227	1
auto[TlIntgErrCmd]	partial	auto[1]	58	1		T226	4		T227	6		T270	1
auto[TlIntgErrCmd]	full_word	auto[0]	6	1		T44	1		T270	1		T302	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1		T227	1		T360	1		-	-
auto[TlIntgErrData]	partial	auto[0]	51	1		T226	4		T227	3		T270	2
auto[TlIntgErrData]	partial	auto[1]	50	1		T44	1		T226	5		T227	2
auto[TlIntgErrData]	full_word	auto[0]	8	1		T227	1		T360	3		T302	1
auto[TlIntgErrData]	full_word	auto[1]	7	1		T226	1		T359	1		T363	1
auto[TlIntgErrBoth]	partial	auto[0]	35	1		T44	2		T226	3		T227	1
auto[TlIntgErrBoth]	partial	auto[1]	53	1		T44	4		T226	1		T227	4
auto[TlIntgErrBoth]	full_word	auto[0]	4	1		T227	1		T270	1		T359	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1		T361	1		T359	1		T360	1

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	19498	1		T187	1299		T44	9		T46	7
full_word	4202516	1		T2	18		T3	16922		T4	142

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4221726	1		T2	18		T3	16922		T4	142
auto[TlIntgErrCmd]	107	1		T44	3		T226	9		T227	10
auto[TlIntgErrData]	106	1		T44	3		T226	8		T227	4
auto[TlIntgErrBoth]	75	1		T44	3		T226	3		T227	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	4196872	1		T2	18		T3	16922		T4	142
auto[1]	25142	1		T187	1627		T44	7		T46	12

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1330	1		T187	96		T46	1		T213	73
auto[TlIntgErrNone]	partial	auto[1]	17909	1		T187	1203		T46	6		T213	1228
auto[TlIntgErrNone]	full_word	auto[0]	4195415	1		T2	18		T3	16922		T4	142
auto[TlIntgErrNone]	full_word	auto[1]	7072	1		T187	424		T46	6		T213	471
auto[TlIntgErrCmd]	partial	auto[0]	41	1		T226	5		T227	5		T270	3
auto[TlIntgErrCmd]	partial	auto[1]	53	1		T44	3		T226	4		T227	5
auto[TlIntgErrCmd]	full_word	auto[0]	4	1		T364	1		T365	2		T366	1
auto[TlIntgErrCmd]	full_word	auto[1]	9	1		T361	1		T360	1		T302	1
auto[TlIntgErrData]	partial	auto[0]	48	1		T44	1		T226	2		T227	1
auto[TlIntgErrData]	partial	auto[1]	50	1		T44	2		T226	6		T227	2
auto[TlIntgErrData]	full_word	auto[0]	4	1		T270	1		T297	1		T363	1
auto[TlIntgErrData]	full_word	auto[1]	4	1		T227	1		T361	1		T269	1
auto[TlIntgErrBoth]	partial	auto[0]	27	1		T44	1		T226	2		T227	2
auto[TlIntgErrBoth]	partial	auto[1]	40	1		T44	2		T226	1		T227	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T302	1		T364	1		T367	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1		T227	1		T302	1		T362	1