Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1609759992	1606500064	0	0
CheckNGreaterZero_A	4240	4240	0	0
GntImpliesReady_A	1609759992	434192381	0	0
GntImpliesValid_A	1609759992	434192381	0	0
GrantKnown_A	1609759992	1606500064	0	0
IdxKnown_A	1609759992	1606500064	0	0
IndexIsCorrect_A	1609759992	434192381	0	0
NoReadyValidNoGrant_A	1609759992	177468184	0	0
Priority_A	1609759992	458533407	0	0
ReadyAndValidImplyGrant_A	1609759992	434192381	0	0
ReqAndReadyImplyGrant_A	1609759992	434192381	0	0
ReqImpliesValid_A	1609759992	458533407	0	0
ValidKnown_A	1609759992	1606500064	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1609759992	1606500064	0	0
T1	988416	949036	0	0
T2	31256	30716	0	0
T3	155632	155256	0	0
T4	285100	284880	0	0
T5	394628	394264	0	0
T6	654484	654196	0	0
T10	13096	10688	0	0
T11	3536	3216	0	0
T15	12696	12396	0	0
T16	6436	5848	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4240	4240	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T10	4	4	0	0
T11	4	4	0	0
T15	4	4	0	0
T16	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1609759992	434192381	0	0
T1	494208	180064	0	0
T2	15628	9664	0	0
T3	155632	41596	0	0
T4	285100	136284	0	0
T5	394628	85270	0	0
T6	654484	3136	0	0
T10	13096	352	0	0
T11	3536	584	0	0
T12	0	852616	0	0
T15	12696	676	0	0
T16	6436	540	0	0
T19	0	858	0	0
T20	373188	164558	0	0
T37	4182	0	0	0
T38	0	158804	0	0
T40	0	16618	0	0
T41	0	27678	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1609759992	434192381	0	0
T1	494208	180064	0	0
T2	15628	9664	0	0
T3	155632	41596	0	0
T4	285100	136284	0	0
T5	394628	85270	0	0
T6	654484	3136	0	0
T10	13096	352	0	0
T11	3536	584	0	0
T12	0	852616	0	0
T15	12696	676	0	0
T16	6436	540	0	0
T19	0	858	0	0
T20	373188	164558	0	0
T37	4182	0	0	0
T38	0	158804	0	0
T40	0	16618	0	0
T41	0	27678	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1609759992	1606500064	0	0
T1	988416	949036	0	0
T2	31256	30716	0	0
T3	155632	155256	0	0
T4	285100	284880	0	0
T5	394628	394264	0	0
T6	654484	654196	0	0
T10	13096	10688	0	0
T11	3536	3216	0	0
T15	12696	12396	0	0
T16	6436	5848	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1609759992	1606500064	0	0
T1	988416	949036	0	0
T2	31256	30716	0	0
T3	155632	155256	0	0
T4	285100	284880	0	0
T5	394628	394264	0	0
T6	654484	654196	0	0
T10	13096	10688	0	0
T11	3536	3216	0	0
T15	12696	12396	0	0
T16	6436	5848	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1609759992	434192381	0	0
T1	494208	180064	0	0
T2	15628	9664	0	0
T3	155632	41596	0	0
T4	285100	136284	0	0
T5	394628	85270	0	0
T6	654484	3136	0	0
T10	13096	352	0	0
T11	3536	584	0	0
T12	0	852616	0	0
T15	12696	676	0	0
T16	6436	540	0	0
T19	0	858	0	0
T20	373188	164558	0	0
T37	4182	0	0	0
T38	0	158804	0	0
T40	0	16618	0	0
T41	0	27678	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1609759992	177468184	0	0
T1	494208	48376	0	0
T2	15628	940	0	0
T3	155632	53714	0	0
T4	285100	1200	0	0
T5	394628	126646	0	0
T6	654484	5760	0	0
T10	13096	1308	0	0
T11	3536	256	0	0
T12	0	1048772	0	0
T15	12696	398	0	0
T16	6436	728	0	0
T20	373188	0	0	0
T32	0	1068	0	0
T37	4182	0	0	0
T38	0	109756	0	0
T41	0	47170	0	0
T43	0	458	0	0
T47	0	1292	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1609759992	458533407	0	0
T1	494208	180064	0	0
T2	15628	9664	0	0
T3	155632	53670	0	0
T4	285100	136496	0	0
T5	394628	120158	0	0
T6	654484	3136	0	0
T10	13096	352	0	0
T11	3536	584	0	0
T12	0	852616	0	0
T15	12696	676	0	0
T16	6436	540	0	0
T19	0	858	0	0
T20	373188	164558	0	0
T37	4182	0	0	0
T38	0	198216	0	0
T40	0	16618	0	0
T41	0	31106	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1609759992	434192381	0	0
T1	494208	180064	0	0
T2	15628	9664	0	0
T3	155632	41596	0	0
T4	285100	136284	0	0
T5	394628	85270	0	0
T6	654484	3136	0	0
T10	13096	352	0	0
T11	3536	584	0	0
T12	0	852616	0	0
T15	12696	676	0	0
T16	6436	540	0	0
T19	0	858	0	0
T20	373188	164558	0	0
T37	4182	0	0	0
T38	0	158804	0	0
T40	0	16618	0	0
T41	0	27678	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1609759992	434192381	0	0
T1	494208	180064	0	0
T2	15628	9664	0	0
T3	155632	41596	0	0
T4	285100	136284	0	0
T5	394628	85270	0	0
T6	654484	3136	0	0
T10	13096	352	0	0
T11	3536	584	0	0
T12	0	852616	0	0
T15	12696	676	0	0
T16	6436	540	0	0
T19	0	858	0	0
T20	373188	164558	0	0
T37	4182	0	0	0
T38	0	158804	0	0
T40	0	16618	0	0
T41	0	27678	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1609759992	458533407	0	0
T1	494208	180064	0	0
T2	15628	9664	0	0
T3	155632	53670	0	0
T4	285100	136496	0	0
T5	394628	120158	0	0
T6	654484	3136	0	0
T10	13096	352	0	0
T11	3536	584	0	0
T12	0	852616	0	0
T15	12696	676	0	0
T16	6436	540	0	0
T19	0	858	0	0
T20	373188	164558	0	0
T37	4182	0	0	0
T38	0	198216	0	0
T40	0	16618	0	0
T41	0	31106	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1609759992	1606500064	0	0
T1	988416	949036	0	0
T2	31256	30716	0	0
T3	155632	155256	0	0
T4	285100	284880	0	0
T5	394628	394264	0	0
T6	654484	654196	0	0
T10	13096	10688	0	0
T11	3536	3216	0	0
T15	12696	12396	0	0
T16	6436	5848	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	402439998	401625016	0	0
CheckNGreaterZero_A	1060	1060	0	0
GntImpliesReady_A	402439998	119435725	0	0
GntImpliesValid_A	402439998	119435725	0	0
GrantKnown_A	402439998	401625016	0	0
IdxKnown_A	402439998	401625016	0	0
IndexIsCorrect_A	402439998	119435725	0	0
NoReadyValidNoGrant_A	402439998	46154172	0	0
Priority_A	402439998	125601135	0	0
ReadyAndValidImplyGrant_A	402439998	119435725	0	0
ReqAndReadyImplyGrant_A	402439998	119435725	0	0
ReqImpliesValid_A	402439998	125601135	0	0
ValidKnown_A	402439998	401625016	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402439998	401625016	0	0
T1	247104	237259	0	0
T2	7814	7679	0	0
T3	38908	38814	0	0
T4	71275	71220	0	0
T5	98657	98566	0	0
T6	163621	163549	0	0
T10	3274	2672	0	0
T11	884	804	0	0
T15	3174	3099	0	0
T16	1609	1462	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1060	1060	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402439998	119435725	0	0
T1	247104	90032	0	0
T2	7814	4832	0	0
T3	38908	8904	0	0
T4	71275	65802	0	0
T5	98657	23144	0	0
T6	163621	1568	0	0
T10	3274	176	0	0
T11	884	292	0	0
T15	3174	55	0	0
T16	1609	270	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402439998	119435725	0	0
T1	247104	90032	0	0
T2	7814	4832	0	0
T3	38908	8904	0	0
T4	71275	65802	0	0
T5	98657	23144	0	0
T6	163621	1568	0	0
T10	3274	176	0	0
T11	884	292	0	0
T15	3174	55	0	0
T16	1609	270	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402439998	401625016	0	0
T1	247104	237259	0	0
T2	7814	7679	0	0
T3	38908	38814	0	0
T4	71275	71220	0	0
T5	98657	98566	0	0
T6	163621	163549	0	0
T10	3274	2672	0	0
T11	884	804	0	0
T15	3174	3099	0	0
T16	1609	1462	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402439998	401625016	0	0
T1	247104	237259	0	0
T2	7814	7679	0	0
T3	38908	38814	0	0
T4	71275	71220	0	0
T5	98657	98566	0	0
T6	163621	163549	0	0
T10	3274	2672	0	0
T11	884	804	0	0
T15	3174	3099	0	0
T16	1609	1462	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402439998	119435725	0	0
T1	247104	90032	0	0
T2	7814	4832	0	0
T3	38908	8904	0	0
T4	71275	65802	0	0
T5	98657	23144	0	0
T6	163621	1568	0	0
T10	3274	176	0	0
T11	884	292	0	0
T15	3174	55	0	0
T16	1609	270	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402439998	46154172	0	0
T1	247104	24188	0	0
T2	7814	470	0	0
T3	38908	12114	0	0
T4	71275	410	0	0
T5	98657	33203	0	0
T6	163621	2880	0	0
T10	3274	654	0	0
T11	884	128	0	0
T15	3174	164	0	0
T16	1609	364	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402439998	125601135	0	0
T1	247104	90032	0	0
T2	7814	4832	0	0
T3	38908	11039	0	0
T4	71275	65855	0	0
T5	98657	35436	0	0
T6	163621	1568	0	0
T10	3274	176	0	0
T11	884	292	0	0
T15	3174	55	0	0
T16	1609	270	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402439998	119435725	0	0
T1	247104	90032	0	0
T2	7814	4832	0	0
T3	38908	8904	0	0
T4	71275	65802	0	0
T5	98657	23144	0	0
T6	163621	1568	0	0
T10	3274	176	0	0
T11	884	292	0	0
T15	3174	55	0	0
T16	1609	270	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402439998	119435725	0	0
T1	247104	90032	0	0
T2	7814	4832	0	0
T3	38908	8904	0	0
T4	71275	65802	0	0
T5	98657	23144	0	0
T6	163621	1568	0	0
T10	3274	176	0	0
T11	884	292	0	0
T15	3174	55	0	0
T16	1609	270	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402439998	125601135	0	0
T1	247104	90032	0	0
T2	7814	4832	0	0
T3	38908	11039	0	0
T4	71275	65855	0	0
T5	98657	35436	0	0
T6	163621	1568	0	0
T10	3274	176	0	0
T11	884	292	0	0
T15	3174	55	0	0
T16	1609	270	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402439998	401625016	0	0
T1	247104	237259	0	0
T2	7814	7679	0	0
T3	38908	38814	0	0
T4	71275	71220	0	0
T5	98657	98566	0	0
T6	163621	163549	0	0
T10	3274	2672	0	0
T11	884	804	0	0
T15	3174	3099	0	0
T16	1609	1462	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	402439998	401625016	0	0
CheckNGreaterZero_A	1060	1060	0	0
GntImpliesReady_A	402439998	119275482	0	0
GntImpliesValid_A	402439998	119275482	0	0
GrantKnown_A	402439998	401625016	0	0
IdxKnown_A	402439998	401625016	0	0
IndexIsCorrect_A	402439998	119275482	0	0
NoReadyValidNoGrant_A	402439998	46154172	0	0
Priority_A	402439998	125440892	0	0
ReadyAndValidImplyGrant_A	402439998	119275482	0	0
ReqAndReadyImplyGrant_A	402439998	119275482	0	0
ReqImpliesValid_A	402439998	125440892	0	0
ValidKnown_A	402439998	401625016	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402439998	401625016	0	0
T1	247104	237259	0	0
T2	7814	7679	0	0
T3	38908	38814	0	0
T4	71275	71220	0	0
T5	98657	98566	0	0
T6	163621	163549	0	0
T10	3274	2672	0	0
T11	884	804	0	0
T15	3174	3099	0	0
T16	1609	1462	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1060	1060	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402439998	119275482	0	0
T1	247104	90032	0	0
T2	7814	4832	0	0
T3	38908	8904	0	0
T4	71275	65802	0	0
T5	98657	23144	0	0
T6	163621	1568	0	0
T10	3274	176	0	0
T11	884	292	0	0
T15	3174	55	0	0
T16	1609	270	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402439998	119275482	0	0
T1	247104	90032	0	0
T2	7814	4832	0	0
T3	38908	8904	0	0
T4	71275	65802	0	0
T5	98657	23144	0	0
T6	163621	1568	0	0
T10	3274	176	0	0
T11	884	292	0	0
T15	3174	55	0	0
T16	1609	270	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402439998	401625016	0	0
T1	247104	237259	0	0
T2	7814	7679	0	0
T3	38908	38814	0	0
T4	71275	71220	0	0
T5	98657	98566	0	0
T6	163621	163549	0	0
T10	3274	2672	0	0
T11	884	804	0	0
T15	3174	3099	0	0
T16	1609	1462	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402439998	401625016	0	0
T1	247104	237259	0	0
T2	7814	7679	0	0
T3	38908	38814	0	0
T4	71275	71220	0	0
T5	98657	98566	0	0
T6	163621	163549	0	0
T10	3274	2672	0	0
T11	884	804	0	0
T15	3174	3099	0	0
T16	1609	1462	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402439998	119275482	0	0
T1	247104	90032	0	0
T2	7814	4832	0	0
T3	38908	8904	0	0
T4	71275	65802	0	0
T5	98657	23144	0	0
T6	163621	1568	0	0
T10	3274	176	0	0
T11	884	292	0	0
T15	3174	55	0	0
T16	1609	270	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402439998	46154172	0	0
T1	247104	24188	0	0
T2	7814	470	0	0
T3	38908	12114	0	0
T4	71275	410	0	0
T5	98657	33203	0	0
T6	163621	2880	0	0
T10	3274	654	0	0
T11	884	128	0	0
T15	3174	164	0	0
T16	1609	364	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402439998	125440892	0	0
T1	247104	90032	0	0
T2	7814	4832	0	0
T3	38908	11039	0	0
T4	71275	65855	0	0
T5	98657	35436	0	0
T6	163621	1568	0	0
T10	3274	176	0	0
T11	884	292	0	0
T15	3174	55	0	0
T16	1609	270	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402439998	119275482	0	0
T1	247104	90032	0	0
T2	7814	4832	0	0
T3	38908	8904	0	0
T4	71275	65802	0	0
T5	98657	23144	0	0
T6	163621	1568	0	0
T10	3274	176	0	0
T11	884	292	0	0
T15	3174	55	0	0
T16	1609	270	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402439998	119275482	0	0
T1	247104	90032	0	0
T2	7814	4832	0	0
T3	38908	8904	0	0
T4	71275	65802	0	0
T5	98657	23144	0	0
T6	163621	1568	0	0
T10	3274	176	0	0
T11	884	292	0	0
T15	3174	55	0	0
T16	1609	270	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402439998	125440892	0	0
T1	247104	90032	0	0
T2	7814	4832	0	0
T3	38908	11039	0	0
T4	71275	65855	0	0
T5	98657	35436	0	0
T6	163621	1568	0	0
T10	3274	176	0	0
T11	884	292	0	0
T15	3174	55	0	0
T16	1609	270	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402439998	401625016	0	0
T1	247104	237259	0	0
T2	7814	7679	0	0
T3	38908	38814	0	0
T4	71275	71220	0	0
T5	98657	98566	0	0
T6	163621	163549	0	0
T10	3274	2672	0	0
T11	884	804	0	0
T15	3174	3099	0	0
T16	1609	1462	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5
1	1	Covered	T3,T4,T5

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T3,T4,T5

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T3,T4,T5

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T5

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	402439998	401625016	0	0
CheckNGreaterZero_A	1060	1060	0	0
GntImpliesReady_A	402439998	97740587	0	0
GntImpliesValid_A	402439998	97740587	0	0
GrantKnown_A	402439998	401625016	0	0
IdxKnown_A	402439998	401625016	0	0
IndexIsCorrect_A	402439998	97740587	0	0
NoReadyValidNoGrant_A	402439998	42579920	0	0
Priority_A	402439998	103745690	0	0
ReadyAndValidImplyGrant_A	402439998	97740587	0	0
ReqAndReadyImplyGrant_A	402439998	97740587	0	0
ReqImpliesValid_A	402439998	103745690	0	0
ValidKnown_A	402439998	401625016	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402439998	401625016	0	0
T1	247104	237259	0	0
T2	7814	7679	0	0
T3	38908	38814	0	0
T4	71275	71220	0	0
T5	98657	98566	0	0
T6	163621	163549	0	0
T10	3274	2672	0	0
T11	884	804	0	0
T15	3174	3099	0	0
T16	1609	1462	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1060	1060	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402439998	97740587	0	0
T3	38908	11894	0	0
T4	71275	2340	0	0
T5	98657	19491	0	0
T6	163621	0	0	0
T10	3274	0	0	0
T11	884	0	0	0
T12	0	426308	0	0
T15	3174	283	0	0
T16	1609	0	0	0
T19	0	429	0	0
T20	186594	82279	0	0
T37	2091	0	0	0
T38	0	79402	0	0
T40	0	8309	0	0
T41	0	13839	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402439998	97740587	0	0
T3	38908	11894	0	0
T4	71275	2340	0	0
T5	98657	19491	0	0
T6	163621	0	0	0
T10	3274	0	0	0
T11	884	0	0	0
T12	0	426308	0	0
T15	3174	283	0	0
T16	1609	0	0	0
T19	0	429	0	0
T20	186594	82279	0	0
T37	2091	0	0	0
T38	0	79402	0	0
T40	0	8309	0	0
T41	0	13839	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402439998	401625016	0	0
T1	247104	237259	0	0
T2	7814	7679	0	0
T3	38908	38814	0	0
T4	71275	71220	0	0
T5	98657	98566	0	0
T6	163621	163549	0	0
T10	3274	2672	0	0
T11	884	804	0	0
T15	3174	3099	0	0
T16	1609	1462	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402439998	401625016	0	0
T1	247104	237259	0	0
T2	7814	7679	0	0
T3	38908	38814	0	0
T4	71275	71220	0	0
T5	98657	98566	0	0
T6	163621	163549	0	0
T10	3274	2672	0	0
T11	884	804	0	0
T15	3174	3099	0	0
T16	1609	1462	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402439998	97740587	0	0
T3	38908	11894	0	0
T4	71275	2340	0	0
T5	98657	19491	0	0
T6	163621	0	0	0
T10	3274	0	0	0
T11	884	0	0	0
T12	0	426308	0	0
T15	3174	283	0	0
T16	1609	0	0	0
T19	0	429	0	0
T20	186594	82279	0	0
T37	2091	0	0	0
T38	0	79402	0	0
T40	0	8309	0	0
T41	0	13839	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402439998	42579920	0	0
T3	38908	14743	0	0
T4	71275	190	0	0
T5	98657	30120	0	0
T6	163621	0	0	0
T10	3274	0	0	0
T11	884	0	0	0
T12	0	524386	0	0
T15	3174	35	0	0
T16	1609	0	0	0
T20	186594	0	0	0
T32	0	534	0	0
T37	2091	0	0	0
T38	0	54878	0	0
T41	0	23585	0	0
T43	0	229	0	0
T47	0	646	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402439998	103745690	0	0
T3	38908	15796	0	0
T4	71275	2393	0	0
T5	98657	24643	0	0
T6	163621	0	0	0
T10	3274	0	0	0
T11	884	0	0	0
T12	0	426308	0	0
T15	3174	283	0	0
T16	1609	0	0	0
T19	0	429	0	0
T20	186594	82279	0	0
T37	2091	0	0	0
T38	0	99108	0	0
T40	0	8309	0	0
T41	0	15553	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402439998	97740587	0	0
T3	38908	11894	0	0
T4	71275	2340	0	0
T5	98657	19491	0	0
T6	163621	0	0	0
T10	3274	0	0	0
T11	884	0	0	0
T12	0	426308	0	0
T15	3174	283	0	0
T16	1609	0	0	0
T19	0	429	0	0
T20	186594	82279	0	0
T37	2091	0	0	0
T38	0	79402	0	0
T40	0	8309	0	0
T41	0	13839	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402439998	97740587	0	0
T3	38908	11894	0	0
T4	71275	2340	0	0
T5	98657	19491	0	0
T6	163621	0	0	0
T10	3274	0	0	0
T11	884	0	0	0
T12	0	426308	0	0
T15	3174	283	0	0
T16	1609	0	0	0
T19	0	429	0	0
T20	186594	82279	0	0
T37	2091	0	0	0
T38	0	79402	0	0
T40	0	8309	0	0
T41	0	13839	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402439998	103745690	0	0
T3	38908	15796	0	0
T4	71275	2393	0	0
T5	98657	24643	0	0
T6	163621	0	0	0
T10	3274	0	0	0
T11	884	0	0	0
T12	0	426308	0	0
T15	3174	283	0	0
T16	1609	0	0	0
T19	0	429	0	0
T20	186594	82279	0	0
T37	2091	0	0	0
T38	0	99108	0	0
T40	0	8309	0	0
T41	0	15553	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402439998	401625016	0	0
T1	247104	237259	0	0
T2	7814	7679	0	0
T3	38908	38814	0	0
T4	71275	71220	0	0
T5	98657	98566	0	0
T6	163621	163549	0	0
T10	3274	2672	0	0
T11	884	804	0	0
T15	3174	3099	0	0
T16	1609	1462	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5
1	1	Covered	T3,T4,T5

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T3,T4,T5

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T3,T4,T5

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T5

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	402439998	401625016	0	0
CheckNGreaterZero_A	1060	1060	0	0
GntImpliesReady_A	402439998	97740587	0	0
GntImpliesValid_A	402439998	97740587	0	0
GrantKnown_A	402439998	401625016	0	0
IdxKnown_A	402439998	401625016	0	0
IndexIsCorrect_A	402439998	97740587	0	0
NoReadyValidNoGrant_A	402439998	42579920	0	0
Priority_A	402439998	103745690	0	0
ReadyAndValidImplyGrant_A	402439998	97740587	0	0
ReqAndReadyImplyGrant_A	402439998	97740587	0	0
ReqImpliesValid_A	402439998	103745690	0	0
ValidKnown_A	402439998	401625016	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402439998	401625016	0	0
T1	247104	237259	0	0
T2	7814	7679	0	0
T3	38908	38814	0	0
T4	71275	71220	0	0
T5	98657	98566	0	0
T6	163621	163549	0	0
T10	3274	2672	0	0
T11	884	804	0	0
T15	3174	3099	0	0
T16	1609	1462	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1060	1060	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402439998	97740587	0	0
T3	38908	11894	0	0
T4	71275	2340	0	0
T5	98657	19491	0	0
T6	163621	0	0	0
T10	3274	0	0	0
T11	884	0	0	0
T12	0	426308	0	0
T15	3174	283	0	0
T16	1609	0	0	0
T19	0	429	0	0
T20	186594	82279	0	0
T37	2091	0	0	0
T38	0	79402	0	0
T40	0	8309	0	0
T41	0	13839	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402439998	97740587	0	0
T3	38908	11894	0	0
T4	71275	2340	0	0
T5	98657	19491	0	0
T6	163621	0	0	0
T10	3274	0	0	0
T11	884	0	0	0
T12	0	426308	0	0
T15	3174	283	0	0
T16	1609	0	0	0
T19	0	429	0	0
T20	186594	82279	0	0
T37	2091	0	0	0
T38	0	79402	0	0
T40	0	8309	0	0
T41	0	13839	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402439998	401625016	0	0
T1	247104	237259	0	0
T2	7814	7679	0	0
T3	38908	38814	0	0
T4	71275	71220	0	0
T5	98657	98566	0	0
T6	163621	163549	0	0
T10	3274	2672	0	0
T11	884	804	0	0
T15	3174	3099	0	0
T16	1609	1462	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402439998	401625016	0	0
T1	247104	237259	0	0
T2	7814	7679	0	0
T3	38908	38814	0	0
T4	71275	71220	0	0
T5	98657	98566	0	0
T6	163621	163549	0	0
T10	3274	2672	0	0
T11	884	804	0	0
T15	3174	3099	0	0
T16	1609	1462	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402439998	97740587	0	0
T3	38908	11894	0	0
T4	71275	2340	0	0
T5	98657	19491	0	0
T6	163621	0	0	0
T10	3274	0	0	0
T11	884	0	0	0
T12	0	426308	0	0
T15	3174	283	0	0
T16	1609	0	0	0
T19	0	429	0	0
T20	186594	82279	0	0
T37	2091	0	0	0
T38	0	79402	0	0
T40	0	8309	0	0
T41	0	13839	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402439998	42579920	0	0
T3	38908	14743	0	0
T4	71275	190	0	0
T5	98657	30120	0	0
T6	163621	0	0	0
T10	3274	0	0	0
T11	884	0	0	0
T12	0	524386	0	0
T15	3174	35	0	0
T16	1609	0	0	0
T20	186594	0	0	0
T32	0	534	0	0
T37	2091	0	0	0
T38	0	54878	0	0
T41	0	23585	0	0
T43	0	229	0	0
T47	0	646	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402439998	103745690	0	0
T3	38908	15796	0	0
T4	71275	2393	0	0
T5	98657	24643	0	0
T6	163621	0	0	0
T10	3274	0	0	0
T11	884	0	0	0
T12	0	426308	0	0
T15	3174	283	0	0
T16	1609	0	0	0
T19	0	429	0	0
T20	186594	82279	0	0
T37	2091	0	0	0
T38	0	99108	0	0
T40	0	8309	0	0
T41	0	15553	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402439998	97740587	0	0
T3	38908	11894	0	0
T4	71275	2340	0	0
T5	98657	19491	0	0
T6	163621	0	0	0
T10	3274	0	0	0
T11	884	0	0	0
T12	0	426308	0	0
T15	3174	283	0	0
T16	1609	0	0	0
T19	0	429	0	0
T20	186594	82279	0	0
T37	2091	0	0	0
T38	0	79402	0	0
T40	0	8309	0	0
T41	0	13839	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402439998	97740587	0	0
T3	38908	11894	0	0
T4	71275	2340	0	0
T5	98657	19491	0	0
T6	163621	0	0	0
T10	3274	0	0	0
T11	884	0	0	0
T12	0	426308	0	0
T15	3174	283	0	0
T16	1609	0	0	0
T19	0	429	0	0
T20	186594	82279	0	0
T37	2091	0	0	0
T38	0	79402	0	0
T40	0	8309	0	0
T41	0	13839	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402439998	103745690	0	0
T3	38908	15796	0	0
T4	71275	2393	0	0
T5	98657	24643	0	0
T6	163621	0	0	0
T10	3274	0	0	0
T11	884	0	0	0
T12	0	426308	0	0
T15	3174	283	0	0
T16	1609	0	0	0
T19	0	429	0	0
T20	186594	82279	0	0
T37	2091	0	0	0
T38	0	99108	0	0
T40	0	8309	0	0
T41	0	15553	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402439998	401625016	0	0
T1	247104	237259	0	0
T2	7814	7679	0	0
T3	38908	38814	0	0
T4	71275	71220	0	0
T5	98657	98566	0	0
T6	163621	163549	0	0
T10	3274	2672	0	0
T11	884	804	0	0
T15	3174	3099	0	0
T16	1609	1462	0	0