Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	24543674	1		T1	660281		T2	4404		T3	1743
full_word	7508249	1		T1	23817		T2	3370		T3	1641

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	32051613	1		T1	684098		T2	7774		T3	3384
auto[TlIntgErrCmd]	108	1		T207	5		T208	9		T232	2
auto[TlIntgErrData]	92	1		T207	6		T208	7		T232	4
auto[TlIntgErrBoth]	110	1		T207	9		T208	4		T232	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	27771354	1		T1	668607		T2	5275		T3	3319
auto[1]	4280569	1		T1	15491		T2	2499		T3	65

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	23919454	1		T1	659100		T2	4051		T3	1733
auto[TlIntgErrNone]	partial	auto[1]	623936	1		T1	1181		T2	353		T3	10
auto[TlIntgErrNone]	full_word	auto[0]	3851770	1		T1	9507		T2	1224		T3	1586
auto[TlIntgErrNone]	full_word	auto[1]	3656453	1		T1	14310		T2	2146		T3	55
auto[TlIntgErrCmd]	partial	auto[0]	42	1		T207	2		T208	4		T232	1
auto[TlIntgErrCmd]	partial	auto[1]	58	1		T207	2		T208	4		T232	1
auto[TlIntgErrCmd]	full_word	auto[0]	4	1		T265	1		T337	1		T338	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1		T207	1		T208	1		T339	1
auto[TlIntgErrData]	partial	auto[0]	37	1		T208	4		T232	3		T265	2
auto[TlIntgErrData]	partial	auto[1]	47	1		T207	5		T208	3		T232	1
auto[TlIntgErrData]	full_word	auto[0]	6	1		T207	1		T338	1		T261	1
auto[TlIntgErrData]	full_word	auto[1]	2	1		T290	1		T340	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	40	1		T207	4		T232	2		T267	2
auto[TlIntgErrBoth]	partial	auto[1]	60	1		T207	4		T208	4		T267	3
auto[TlIntgErrBoth]	full_word	auto[0]	1	1		T267	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	9	1		T207	1		T232	2		T265	1

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	23550	1		T177	1430		T50	621		T51	77
full_word	4306957	1		T7	16294		T18	344		T8	16613

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4330217	1		T7	16294		T18	344		T8	16613
auto[TlIntgErrCmd]	87	1		T207	6		T208	5		T232	1
auto[TlIntgErrData]	98	1		T207	8		T208	6		T232	3
auto[TlIntgErrBoth]	105	1		T207	6		T208	7		T232	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	4301462	1		T7	16294		T18	344		T8	16613
auto[1]	29045	1		T177	1530		T50	764		T51	128

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1498	1		T177	93		T50	55		T51	4
auto[TlIntgErrNone]	partial	auto[1]	21787	1		T177	1337		T50	566		T51	73
auto[TlIntgErrNone]	full_word	auto[0]	4299839	1		T7	16294		T18	344		T8	16613
auto[TlIntgErrNone]	full_word	auto[1]	7093	1		T177	193		T50	198		T51	55
auto[TlIntgErrCmd]	partial	auto[0]	32	1		T207	3		T208	2		T232	1
auto[TlIntgErrCmd]	partial	auto[1]	48	1		T207	3		T208	3		T267	1
auto[TlIntgErrCmd]	full_word	auto[0]	2	1		T341	1		T342	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	5	1		T267	1		T337	1		T261	1
auto[TlIntgErrData]	partial	auto[0]	42	1		T207	5		T208	1		T232	3
auto[TlIntgErrData]	partial	auto[1]	47	1		T207	2		T208	4		T267	3
auto[TlIntgErrData]	full_word	auto[0]	5	1		T207	1		T234	1		T341	1
auto[TlIntgErrData]	full_word	auto[1]	4	1		T208	1		T265	1		T343	1
auto[TlIntgErrBoth]	partial	auto[0]	37	1		T207	2		T208	3		T232	2
auto[TlIntgErrBoth]	partial	auto[1]	59	1		T207	3		T208	3		T232	3
auto[TlIntgErrBoth]	full_word	auto[0]	7	1		T207	1		T208	1		T267	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1		T267	1		T342	1		-	-