Unified Coverage Report :: Module :: flash_phy_scramble

Module : flash_phy_scramble

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.40	100.00	86.21			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_scramble.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_scramble	95.40	100.00	86.21			100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_scramble	95.40	100.00	86.21			100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_scramble

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.40	100.00	86.21			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.18	100.00	90.91	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.37	98.73	95.28		100.00	97.83	100.00	gen_flash_cores[0].u_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_gf_mult.u_mult	100.00	100.00	100.00			100.00	100.00
gen_prince.u_cipher	100.00			100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_scramble

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.40	100.00	86.21			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.18	100.00	90.91	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.29	96.20	83.96		100.00	91.30	100.00	gen_flash_cores[1].u_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_gf_mult.u_mult	100.00	100.00	100.00			100.00	100.00
gen_prince.u_cipher	100.00			100.00

Line Coverage for Module : flash_phy_scramble

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
ALWAYS	43	4	4	100.00
CONT_ASSIGN	50	1	1	100.00
CONT_ASSIGN	53	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	96	4	4	100.00
ALWAYS	112	3	3	100.00
CONT_ASSIGN	119	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	158	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_scramble.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_scramble.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
43	1	1
44	1	1
45	1	1
46	1	1
			MISSING_ELSE
50	1	1
53	1	1
89	1	1
96	1	1
97	1	1
98	1	1
99	1	1
			MISSING_ELSE
112	1	1
113	1	1
115	1	1
119	1	1
120	1	1
155	1	1
158	1	1

---

Cond Coverage for Module : flash_phy_scramble

	Total	Covered	Percent
Conditions	29	25	86.21
Logical	29	25	86.21
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((!calc_req_i)) || (calc_req_i && calc_ack_o))
             -------1-------    -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       45
 SUB-EXPRESSION (calc_req_i && calc_ack_o)
                 -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Unreachable	T1,T2,T3

 LINE       50
 EXPRESSION (addr_key_sel ? rand_addr_key_i : addr_key_i)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T6

 LINE       89
 EXPRESSION (op_type_i == DeScrambleOp)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (((!op_req_i)) || (op_req_i && op_ack_o))
             ------1------    -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       98
 SUB-EXPRESSION (op_req_i && op_ack_o)
                 ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       119
 EXPRESSION (op_ack_o ? '0 : (op_req_i & ((!cipher_valid_out))))
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       119
 SUB-EXPRESSION (op_req_i & ((!cipher_valid_out)))
                 ----1---   ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       120
 EXPRESSION (cipher_valid_in_q & cipher_valid_out)
             --------1--------   --------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (dec ? scrambled_data_i : plain_data_i)
             -1-

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (data_key_sel ? rand_data_key_i : data_key_i)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T6

 LINE       155
 EXPRESSION (dec ? data : scrambled_data_i)
             -1-

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       158
 EXPRESSION (dec ? plain_data_i : data)
             -1-

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

---

Branch Coverage for Module : flash_phy_scramble

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	50	2	2	100.00
TERNARY	119	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	158	2	2	100.00
TERNARY	132	2	2	100.00
TERNARY	132	2	2	100.00
IF	43	3	3	100.00
IF	96	3	3	100.00
IF	112	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_scramble.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_scramble.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	50	(addr_key_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	119	(op_ack_o) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	155	(dec) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	158	(dec) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	132	(dec) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	132	(data_key_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	43	if ((!rst_ni))
-2-:	45	if (((!calc_req_i) || (calc_req_i && calc_ack_o)))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if (((!op_req_i) || (op_req_i && op_ack_o)))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	112	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_scramble

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
ALWAYS	43	4	4	100.00
CONT_ASSIGN	50	1	1	100.00
CONT_ASSIGN	53	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	96	4	4	100.00
ALWAYS	112	3	3	100.00
CONT_ASSIGN	119	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	158	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_scramble.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_scramble.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
43	1	1
44	1	1
45	1	1
46	1	1
			MISSING_ELSE
50	1	1
53	1	1
89	1	1
96	1	1
97	1	1
98	1	1
99	1	1
			MISSING_ELSE
112	1	1
113	1	1
115	1	1
119	1	1
120	1	1
155	1	1
158	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_scramble

	Total	Covered	Percent
Conditions	29	25	86.21
Logical	29	25	86.21
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((!calc_req_i)) || (calc_req_i && calc_ack_o))
             -------1-------    -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       45
 SUB-EXPRESSION (calc_req_i && calc_ack_o)
                 -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Unreachable	T1,T2,T3

 LINE       50
 EXPRESSION (addr_key_sel ? rand_addr_key_i : addr_key_i)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T6

 LINE       89
 EXPRESSION (op_type_i == DeScrambleOp)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (((!op_req_i)) || (op_req_i && op_ack_o))
             ------1------    -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       98
 SUB-EXPRESSION (op_req_i && op_ack_o)
                 ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       119
 EXPRESSION (op_ack_o ? '0 : (op_req_i & ((!cipher_valid_out))))
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       119
 SUB-EXPRESSION (op_req_i & ((!cipher_valid_out)))
                 ----1---   ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       120
 EXPRESSION (cipher_valid_in_q & cipher_valid_out)
             --------1--------   --------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (dec ? scrambled_data_i : plain_data_i)
             -1-

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (data_key_sel ? rand_data_key_i : data_key_i)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T6

 LINE       155
 EXPRESSION (dec ? data : scrambled_data_i)
             -1-

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       158
 EXPRESSION (dec ? plain_data_i : data)
             -1-

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_scramble

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	50	2	2	100.00
TERNARY	119	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	158	2	2	100.00
TERNARY	132	2	2	100.00
TERNARY	132	2	2	100.00
IF	43	3	3	100.00
IF	96	3	3	100.00
IF	112	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_scramble.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_scramble.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	50	(addr_key_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	119	(op_ack_o) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	155	(dec) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	158	(dec) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	132	(dec) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	132	(data_key_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	43	if ((!rst_ni))
-2-:	45	if (((!calc_req_i) || (calc_req_i && calc_ack_o)))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if (((!op_req_i) || (op_req_i && op_ack_o)))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	112	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_scramble

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
ALWAYS	43	4	4	100.00
CONT_ASSIGN	50	1	1	100.00
CONT_ASSIGN	53	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	96	4	4	100.00
ALWAYS	112	3	3	100.00
CONT_ASSIGN	119	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	158	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_scramble.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_scramble.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
43	1	1
44	1	1
45	1	1
46	1	1
			MISSING_ELSE
50	1	1
53	1	1
89	1	1
96	1	1
97	1	1
98	1	1
99	1	1
			MISSING_ELSE
112	1	1
113	1	1
115	1	1
119	1	1
120	1	1
155	1	1
158	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_scramble

	Total	Covered	Percent
Conditions	29	25	86.21
Logical	29	25	86.21
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((!calc_req_i)) || (calc_req_i && calc_ack_o))
             -------1-------    -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T8
0	1	Unreachable	T3,T6,T8
1	0	Covered	T1,T2,T3

 LINE       45
 SUB-EXPRESSION (calc_req_i && calc_ack_o)
                 -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T3,T6,T8
1	1	Unreachable	T3,T6,T8

 LINE       50
 EXPRESSION (addr_key_sel ? rand_addr_key_i : addr_key_i)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T6

 LINE       89
 EXPRESSION (op_type_i == DeScrambleOp)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (((!op_req_i)) || (op_req_i && op_ack_o))
             ------1------    -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T8
0	1	Covered	T3,T6,T8
1	0	Covered	T1,T2,T3

 LINE       98
 SUB-EXPRESSION (op_req_i && op_ack_o)
                 ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T6,T8
1	1	Covered	T3,T6,T8

 LINE       119
 EXPRESSION (op_ack_o ? '0 : (op_req_i & ((!cipher_valid_out))))
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T6,T8

 LINE       119
 SUB-EXPRESSION (op_req_i & ((!cipher_valid_out)))
                 ----1---   ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T6,T8

 LINE       120
 EXPRESSION (cipher_valid_in_q & cipher_valid_out)
             --------1--------   --------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T3,T6,T8

 LINE       132
 EXPRESSION (dec ? scrambled_data_i : plain_data_i)
             -1-

-1-	Status	Tests
0	Covered	T3,T20,T27
1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (data_key_sel ? rand_data_key_i : data_key_i)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T6

 LINE       155
 EXPRESSION (dec ? data : scrambled_data_i)
             -1-

-1-	Status	Tests
0	Covered	T3,T20,T27
1	Covered	T1,T2,T3

 LINE       158
 EXPRESSION (dec ? plain_data_i : data)
             -1-

-1-	Status	Tests
0	Covered	T3,T20,T27
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_scramble

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	50	2	2	100.00
TERNARY	119	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	158	2	2	100.00
TERNARY	132	2	2	100.00
TERNARY	132	2	2	100.00
IF	43	3	3	100.00
IF	96	3	3	100.00
IF	112	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_scramble.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_scramble.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	50	(addr_key_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	119	(op_ack_o) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T6,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	155	(dec) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T20,T27

	LineNo.	Expression
-1-:	158	(dec) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T20,T27

	LineNo.	Expression
-1-:	132	(dec) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T20,T27

	LineNo.	Expression
-1-:	132	(data_key_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	43	if ((!rst_ni))
-2-:	45	if (((!calc_req_i) || (calc_req_i && calc_ack_o)))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T3,T6,T8

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if (((!op_req_i) || (op_req_i && op_ack_o)))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T3,T6,T8

	LineNo.	Expression
-1-:	112	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3