Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T18,T8

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T7,T18,T8
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T7,T18,T8
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T18,T8

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T18,T8
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T9
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T7,T18,T8

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T7,T18,T8

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1664655632	1661235332	0	0
CheckNGreaterZero_A	4244	4244	0	0
GntImpliesReady_A	1664655632	457694895	0	0
GntImpliesValid_A	1664655632	457694895	0	0
GrantKnown_A	1664655632	1661235332	0	0
IdxKnown_A	1664655632	1661235332	0	0
IndexIsCorrect_A	1664655632	457694895	0	0
NoReadyValidNoGrant_A	1664655632	180682064	0	0
Priority_A	1664655632	481570917	0	0
ReadyAndValidImplyGrant_A	1664655632	457694895	0	0
ReqAndReadyImplyGrant_A	1664655632	457694895	0	0
ReqImpliesValid_A	1664655632	481570917	0	0
ValidKnown_A	1664655632	1661235332	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1664655632	1661235332	0	0
T1	547804	547784	0	0
T2	356668	343124	0	0
T3	1541820	1541756	0	0
T4	2468	2188	0	0
T5	6500	5936	0	0
T6	2808	2436	0	0
T7	3266996	3266408	0	0
T16	10308	10024	0	0
T17	386196	385808	0	0
T18	109972	109652	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4244	4244	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T7	4	4	0	0
T16	4	4	0	0
T17	4	4	0	0
T18	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1664655632	457694895	0	0
T1	547804	2578248	0	0
T2	356668	53888	0	0
T3	1541820	514652	0	0
T4	2468	196	0	0
T5	6500	132	0	0
T6	2808	92	0	0
T7	3266996	57968	0	0
T8	0	29480	0	0
T9	0	19950	0	0
T16	10308	64	0	0
T17	386196	122084	0	0
T18	109972	36292	0	0
T19	0	30714	0	0
T43	0	34470	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1664655632	457694895	0	0
T1	547804	2578248	0	0
T2	356668	53888	0	0
T3	1541820	514652	0	0
T4	2468	196	0	0
T5	6500	132	0	0
T6	2808	92	0	0
T7	3266996	57968	0	0
T8	0	29480	0	0
T9	0	19950	0	0
T16	10308	64	0	0
T17	386196	122084	0	0
T18	109972	36292	0	0
T19	0	30714	0	0
T43	0	34470	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1664655632	1661235332	0	0
T1	547804	547784	0	0
T2	356668	343124	0	0
T3	1541820	1541756	0	0
T4	2468	2188	0	0
T5	6500	5936	0	0
T6	2808	2436	0	0
T7	3266996	3266408	0	0
T16	10308	10024	0	0
T17	386196	385808	0	0
T18	109972	109652	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1664655632	1661235332	0	0
T1	547804	547784	0	0
T2	356668	343124	0	0
T3	1541820	1541756	0	0
T4	2468	2188	0	0
T5	6500	5936	0	0
T6	2808	2436	0	0
T7	3266996	3266408	0	0
T16	10308	10024	0	0
T17	386196	385808	0	0
T18	109972	109652	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1664655632	457694895	0	0
T1	547804	2578248	0	0
T2	356668	53888	0	0
T3	1541820	514652	0	0
T4	2468	196	0	0
T5	6500	132	0	0
T6	2808	92	0	0
T7	3266996	57968	0	0
T8	0	29480	0	0
T9	0	19950	0	0
T16	10308	64	0	0
T17	386196	122084	0	0
T18	109972	36292	0	0
T19	0	30714	0	0
T43	0	34470	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1664655632	180682064	0	0
T1	547804	14682	0	0
T2	356668	16784	0	0
T3	1541820	2109952	0	0
T4	2468	256	0	0
T5	6500	512	0	0
T6	2808	326	0	0
T7	3266996	1843008	0	0
T8	0	80014	0	0
T9	0	26776	0	0
T16	10308	256	0	0
T17	386196	7396	0	0
T18	109972	3856	0	0
T19	0	83892	0	0
T20	0	256	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1664655632	481570917	0	0
T1	547804	2578248	0	0
T2	356668	53888	0	0
T3	1541820	514652	0	0
T4	2468	196	0	0
T5	6500	132	0	0
T6	2808	92	0	0
T7	3266996	599364	0	0
T8	0	30964	0	0
T9	0	24724	0	0
T16	10308	64	0	0
T17	386196	122084	0	0
T18	109972	36292	0	0
T19	0	32146	0	0
T43	0	34470	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1664655632	457694895	0	0
T1	547804	2578248	0	0
T2	356668	53888	0	0
T3	1541820	514652	0	0
T4	2468	196	0	0
T5	6500	132	0	0
T6	2808	92	0	0
T7	3266996	57968	0	0
T8	0	29480	0	0
T9	0	19950	0	0
T16	10308	64	0	0
T17	386196	122084	0	0
T18	109972	36292	0	0
T19	0	30714	0	0
T43	0	34470	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1664655632	457694895	0	0
T1	547804	2578248	0	0
T2	356668	53888	0	0
T3	1541820	514652	0	0
T4	2468	196	0	0
T5	6500	132	0	0
T6	2808	92	0	0
T7	3266996	57968	0	0
T8	0	29480	0	0
T9	0	19950	0	0
T16	10308	64	0	0
T17	386196	122084	0	0
T18	109972	36292	0	0
T19	0	30714	0	0
T43	0	34470	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1664655632	481570917	0	0
T1	547804	2578248	0	0
T2	356668	53888	0	0
T3	1541820	514652	0	0
T4	2468	196	0	0
T5	6500	132	0	0
T6	2808	92	0	0
T7	3266996	599364	0	0
T8	0	30964	0	0
T9	0	24724	0	0
T16	10308	64	0	0
T17	386196	122084	0	0
T18	109972	36292	0	0
T19	0	32146	0	0
T43	0	34470	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1664655632	1661235332	0	0
T1	547804	547784	0	0
T2	356668	343124	0	0
T3	1541820	1541756	0	0
T4	2468	2188	0	0
T5	6500	5936	0	0
T6	2808	2436	0	0
T7	3266996	3266408	0	0
T16	10308	10024	0	0
T17	386196	385808	0	0
T18	109972	109652	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T18,T8

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T7,T18,T8
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T7,T18,T8
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T18,T8

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T18,T8
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T9
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T7,T18,T8

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T7,T18,T8

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	416163908	415308833	0	0
CheckNGreaterZero_A	1061	1061	0	0
GntImpliesReady_A	416163908	122729224	0	0
GntImpliesValid_A	416163908	122729224	0	0
GrantKnown_A	416163908	415308833	0	0
IdxKnown_A	416163908	415308833	0	0
IndexIsCorrect_A	416163908	122729224	0	0
NoReadyValidNoGrant_A	416163908	46935299	0	0
Priority_A	416163908	128869567	0	0
ReadyAndValidImplyGrant_A	416163908	122729224	0	0
ReqAndReadyImplyGrant_A	416163908	122729224	0	0
ReqImpliesValid_A	416163908	128869567	0	0
ValidKnown_A	416163908	415308833	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416163908	415308833	0	0
T1	136951	136946	0	0
T2	89167	85781	0	0
T3	385455	385439	0	0
T4	617	547	0	0
T5	1625	1484	0	0
T6	702	609	0	0
T7	816749	816602	0	0
T16	2577	2506	0	0
T17	96549	96452	0	0
T18	27493	27413	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1061	1061	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416163908	122729224	0	0
T1	136951	546479	0	0
T2	89167	26944	0	0
T3	385455	129429	0	0
T4	617	98	0	0
T5	1625	66	0	0
T6	702	32	0	0
T7	816749	15467	0	0
T16	2577	32	0	0
T17	96549	33631	0	0
T18	27493	12449	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416163908	122729224	0	0
T1	136951	546479	0	0
T2	89167	26944	0	0
T3	385455	129429	0	0
T4	617	98	0	0
T5	1625	66	0	0
T6	702	32	0	0
T7	816749	15467	0	0
T16	2577	32	0	0
T17	96549	33631	0	0
T18	27493	12449	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416163908	415308833	0	0
T1	136951	136946	0	0
T2	89167	85781	0	0
T3	385455	385439	0	0
T4	617	547	0	0
T5	1625	1484	0	0
T6	702	609	0	0
T7	816749	816602	0	0
T16	2577	2506	0	0
T17	96549	96452	0	0
T18	27493	27413	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416163908	415308833	0	0
T1	136951	136946	0	0
T2	89167	85781	0	0
T3	385455	385439	0	0
T4	617	547	0	0
T5	1625	1484	0	0
T6	702	609	0	0
T7	816749	816602	0	0
T16	2577	2506	0	0
T17	96549	96452	0	0
T18	27493	27413	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416163908	122729224	0	0
T1	136951	546479	0	0
T2	89167	26944	0	0
T3	385455	129429	0	0
T4	617	98	0	0
T5	1625	66	0	0
T6	702	32	0	0
T7	816749	15467	0	0
T16	2577	32	0	0
T17	96549	33631	0	0
T18	27493	12449	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416163908	46935299	0	0
T1	136951	4821	0	0
T2	89167	8392	0	0
T3	385455	530688	0	0
T4	617	128	0	0
T5	1625	256	0	0
T6	702	128	0	0
T7	816749	485854	0	0
T16	2577	128	0	0
T17	96549	2096	0	0
T18	27493	1358	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416163908	128869567	0	0
T1	136951	546479	0	0
T2	89167	26944	0	0
T3	385455	129429	0	0
T4	617	98	0	0
T5	1625	66	0	0
T6	702	32	0	0
T7	816749	162636	0	0
T16	2577	32	0	0
T17	96549	33631	0	0
T18	27493	12449	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416163908	122729224	0	0
T1	136951	546479	0	0
T2	89167	26944	0	0
T3	385455	129429	0	0
T4	617	98	0	0
T5	1625	66	0	0
T6	702	32	0	0
T7	816749	15467	0	0
T16	2577	32	0	0
T17	96549	33631	0	0
T18	27493	12449	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416163908	122729224	0	0
T1	136951	546479	0	0
T2	89167	26944	0	0
T3	385455	129429	0	0
T4	617	98	0	0
T5	1625	66	0	0
T6	702	32	0	0
T7	816749	15467	0	0
T16	2577	32	0	0
T17	96549	33631	0	0
T18	27493	12449	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416163908	128869567	0	0
T1	136951	546479	0	0
T2	89167	26944	0	0
T3	385455	129429	0	0
T4	617	98	0	0
T5	1625	66	0	0
T6	702	32	0	0
T7	816749	162636	0	0
T16	2577	32	0	0
T17	96549	33631	0	0
T18	27493	12449	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416163908	415308833	0	0
T1	136951	136946	0	0
T2	89167	85781	0	0
T3	385455	385439	0	0
T4	617	547	0	0
T5	1625	1484	0	0
T6	702	609	0	0
T7	816749	816602	0	0
T16	2577	2506	0	0
T17	96549	96452	0	0
T18	27493	27413	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T18,T8

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T7,T18,T8
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T7,T18,T8
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T18,T8

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T18,T8
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T9
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T7,T18,T8

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T7,T18,T8

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	416163908	415308833	0	0
CheckNGreaterZero_A	1061	1061	0	0
GntImpliesReady_A	416163908	122471879	0	0
GntImpliesValid_A	416163908	122471879	0	0
GrantKnown_A	416163908	415308833	0	0
IdxKnown_A	416163908	415308833	0	0
IndexIsCorrect_A	416163908	122471879	0	0
NoReadyValidNoGrant_A	416163908	46935299	0	0
Priority_A	416163908	128612222	0	0
ReadyAndValidImplyGrant_A	416163908	122471879	0	0
ReqAndReadyImplyGrant_A	416163908	122471879	0	0
ReqImpliesValid_A	416163908	128612222	0	0
ValidKnown_A	416163908	415308833	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416163908	415308833	0	0
T1	136951	136946	0	0
T2	89167	85781	0	0
T3	385455	385439	0	0
T4	617	547	0	0
T5	1625	1484	0	0
T6	702	609	0	0
T7	816749	816602	0	0
T16	2577	2506	0	0
T17	96549	96452	0	0
T18	27493	27413	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1061	1061	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416163908	122471879	0	0
T1	136951	546479	0	0
T2	89167	26944	0	0
T3	385455	129429	0	0
T4	617	98	0	0
T5	1625	66	0	0
T6	702	32	0	0
T7	816749	15467	0	0
T16	2577	32	0	0
T17	96549	33631	0	0
T18	27493	12449	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416163908	122471879	0	0
T1	136951	546479	0	0
T2	89167	26944	0	0
T3	385455	129429	0	0
T4	617	98	0	0
T5	1625	66	0	0
T6	702	32	0	0
T7	816749	15467	0	0
T16	2577	32	0	0
T17	96549	33631	0	0
T18	27493	12449	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416163908	415308833	0	0
T1	136951	136946	0	0
T2	89167	85781	0	0
T3	385455	385439	0	0
T4	617	547	0	0
T5	1625	1484	0	0
T6	702	609	0	0
T7	816749	816602	0	0
T16	2577	2506	0	0
T17	96549	96452	0	0
T18	27493	27413	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416163908	415308833	0	0
T1	136951	136946	0	0
T2	89167	85781	0	0
T3	385455	385439	0	0
T4	617	547	0	0
T5	1625	1484	0	0
T6	702	609	0	0
T7	816749	816602	0	0
T16	2577	2506	0	0
T17	96549	96452	0	0
T18	27493	27413	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416163908	122471879	0	0
T1	136951	546479	0	0
T2	89167	26944	0	0
T3	385455	129429	0	0
T4	617	98	0	0
T5	1625	66	0	0
T6	702	32	0	0
T7	816749	15467	0	0
T16	2577	32	0	0
T17	96549	33631	0	0
T18	27493	12449	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416163908	46935299	0	0
T1	136951	4821	0	0
T2	89167	8392	0	0
T3	385455	530688	0	0
T4	617	128	0	0
T5	1625	256	0	0
T6	702	128	0	0
T7	816749	485854	0	0
T16	2577	128	0	0
T17	96549	2096	0	0
T18	27493	1358	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416163908	128612222	0	0
T1	136951	546479	0	0
T2	89167	26944	0	0
T3	385455	129429	0	0
T4	617	98	0	0
T5	1625	66	0	0
T6	702	32	0	0
T7	816749	162636	0	0
T16	2577	32	0	0
T17	96549	33631	0	0
T18	27493	12449	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416163908	122471879	0	0
T1	136951	546479	0	0
T2	89167	26944	0	0
T3	385455	129429	0	0
T4	617	98	0	0
T5	1625	66	0	0
T6	702	32	0	0
T7	816749	15467	0	0
T16	2577	32	0	0
T17	96549	33631	0	0
T18	27493	12449	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416163908	122471879	0	0
T1	136951	546479	0	0
T2	89167	26944	0	0
T3	385455	129429	0	0
T4	617	98	0	0
T5	1625	66	0	0
T6	702	32	0	0
T7	816749	15467	0	0
T16	2577	32	0	0
T17	96549	33631	0	0
T18	27493	12449	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416163908	128612222	0	0
T1	136951	546479	0	0
T2	89167	26944	0	0
T3	385455	129429	0	0
T4	617	98	0	0
T5	1625	66	0	0
T6	702	32	0	0
T7	816749	162636	0	0
T16	2577	32	0	0
T17	96549	33631	0	0
T18	27493	12449	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416163908	415308833	0	0
T1	136951	136946	0	0
T2	89167	85781	0	0
T3	385455	385439	0	0
T4	617	547	0	0
T5	1625	1484	0	0
T6	702	609	0	0
T7	816749	816602	0	0
T16	2577	2506	0	0
T17	96549	96452	0	0
T18	27493	27413	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T17
1	0	Covered	T7,T18,T8

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T7,T18,T8
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T7,T18,T8
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T3,T17
1	1	Covered	T7,T18,T8

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T18,T8
1	1	Covered	T1,T3,T17

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T9
1	1	Covered	T1,T3,T17

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T7,T18,T8

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T7,T18,T8

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	416163908	415308833	0	0
CheckNGreaterZero_A	1061	1061	0	0
GntImpliesReady_A	416163908	106246896	0	0
GntImpliesValid_A	416163908	106246896	0	0
GrantKnown_A	416163908	415308833	0	0
IdxKnown_A	416163908	415308833	0	0
IndexIsCorrect_A	416163908	106246896	0	0
NoReadyValidNoGrant_A	416163908	43405733	0	0
Priority_A	416163908	112044564	0	0
ReadyAndValidImplyGrant_A	416163908	106246896	0	0
ReqAndReadyImplyGrant_A	416163908	106246896	0	0
ReqImpliesValid_A	416163908	112044564	0	0
ValidKnown_A	416163908	415308833	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416163908	415308833	0	0
T1	136951	136946	0	0
T2	89167	85781	0	0
T3	385455	385439	0	0
T4	617	547	0	0
T5	1625	1484	0	0
T6	702	609	0	0
T7	816749	816602	0	0
T16	2577	2506	0	0
T17	96549	96452	0	0
T18	27493	27413	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1061	1061	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416163908	106246896	0	0
T1	136951	742645	0	0
T2	89167	0	0	0
T3	385455	127897	0	0
T4	617	0	0	0
T5	1625	0	0	0
T6	702	14	0	0
T7	816749	13517	0	0
T8	0	14740	0	0
T9	0	9975	0	0
T16	2577	0	0	0
T17	96549	27411	0	0
T18	27493	5697	0	0
T19	0	15357	0	0
T43	0	17235	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416163908	106246896	0	0
T1	136951	742645	0	0
T2	89167	0	0	0
T3	385455	127897	0	0
T4	617	0	0	0
T5	1625	0	0	0
T6	702	14	0	0
T7	816749	13517	0	0
T8	0	14740	0	0
T9	0	9975	0	0
T16	2577	0	0	0
T17	96549	27411	0	0
T18	27493	5697	0	0
T19	0	15357	0	0
T43	0	17235	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416163908	415308833	0	0
T1	136951	136946	0	0
T2	89167	85781	0	0
T3	385455	385439	0	0
T4	617	547	0	0
T5	1625	1484	0	0
T6	702	609	0	0
T7	816749	816602	0	0
T16	2577	2506	0	0
T17	96549	96452	0	0
T18	27493	27413	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416163908	415308833	0	0
T1	136951	136946	0	0
T2	89167	85781	0	0
T3	385455	385439	0	0
T4	617	547	0	0
T5	1625	1484	0	0
T6	702	609	0	0
T7	816749	816602	0	0
T16	2577	2506	0	0
T17	96549	96452	0	0
T18	27493	27413	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416163908	106246896	0	0
T1	136951	742645	0	0
T2	89167	0	0	0
T3	385455	127897	0	0
T4	617	0	0	0
T5	1625	0	0	0
T6	702	14	0	0
T7	816749	13517	0	0
T8	0	14740	0	0
T9	0	9975	0	0
T16	2577	0	0	0
T17	96549	27411	0	0
T18	27493	5697	0	0
T19	0	15357	0	0
T43	0	17235	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416163908	43405733	0	0
T1	136951	2520	0	0
T2	89167	0	0	0
T3	385455	524288	0	0
T4	617	0	0	0
T5	1625	0	0	0
T6	702	35	0	0
T7	816749	435650	0	0
T8	0	40007	0	0
T9	0	13388	0	0
T16	2577	0	0	0
T17	96549	1602	0	0
T18	27493	570	0	0
T19	0	41946	0	0
T20	0	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416163908	112044564	0	0
T1	136951	742645	0	0
T2	89167	0	0	0
T3	385455	127897	0	0
T4	617	0	0	0
T5	1625	0	0	0
T6	702	14	0	0
T7	816749	137046	0	0
T8	0	15482	0	0
T9	0	12362	0	0
T16	2577	0	0	0
T17	96549	27411	0	0
T18	27493	5697	0	0
T19	0	16073	0	0
T43	0	17235	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416163908	106246896	0	0
T1	136951	742645	0	0
T2	89167	0	0	0
T3	385455	127897	0	0
T4	617	0	0	0
T5	1625	0	0	0
T6	702	14	0	0
T7	816749	13517	0	0
T8	0	14740	0	0
T9	0	9975	0	0
T16	2577	0	0	0
T17	96549	27411	0	0
T18	27493	5697	0	0
T19	0	15357	0	0
T43	0	17235	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416163908	106246896	0	0
T1	136951	742645	0	0
T2	89167	0	0	0
T3	385455	127897	0	0
T4	617	0	0	0
T5	1625	0	0	0
T6	702	14	0	0
T7	816749	13517	0	0
T8	0	14740	0	0
T9	0	9975	0	0
T16	2577	0	0	0
T17	96549	27411	0	0
T18	27493	5697	0	0
T19	0	15357	0	0
T43	0	17235	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416163908	112044564	0	0
T1	136951	742645	0	0
T2	89167	0	0	0
T3	385455	127897	0	0
T4	617	0	0	0
T5	1625	0	0	0
T6	702	14	0	0
T7	816749	137046	0	0
T8	0	15482	0	0
T9	0	12362	0	0
T16	2577	0	0	0
T17	96549	27411	0	0
T18	27493	5697	0	0
T19	0	16073	0	0
T43	0	17235	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416163908	415308833	0	0
T1	136951	136946	0	0
T2	89167	85781	0	0
T3	385455	385439	0	0
T4	617	547	0	0
T5	1625	1484	0	0
T6	702	609	0	0
T7	816749	816602	0	0
T16	2577	2506	0	0
T17	96549	96452	0	0
T18	27493	27413	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T17
1	0	Covered	T7,T18,T8

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T7,T18,T8
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T7,T18,T8
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T3,T17
1	1	Covered	T7,T18,T8

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T18,T8
1	1	Covered	T1,T3,T17

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T9
1	1	Covered	T1,T3,T17

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T7,T18,T8

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T7,T18,T8

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	416163908	415308833	0	0
CheckNGreaterZero_A	1061	1061	0	0
GntImpliesReady_A	416163908	106246896	0	0
GntImpliesValid_A	416163908	106246896	0	0
GrantKnown_A	416163908	415308833	0	0
IdxKnown_A	416163908	415308833	0	0
IndexIsCorrect_A	416163908	106246896	0	0
NoReadyValidNoGrant_A	416163908	43405733	0	0
Priority_A	416163908	112044564	0	0
ReadyAndValidImplyGrant_A	416163908	106246896	0	0
ReqAndReadyImplyGrant_A	416163908	106246896	0	0
ReqImpliesValid_A	416163908	112044564	0	0
ValidKnown_A	416163908	415308833	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416163908	415308833	0	0
T1	136951	136946	0	0
T2	89167	85781	0	0
T3	385455	385439	0	0
T4	617	547	0	0
T5	1625	1484	0	0
T6	702	609	0	0
T7	816749	816602	0	0
T16	2577	2506	0	0
T17	96549	96452	0	0
T18	27493	27413	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1061	1061	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416163908	106246896	0	0
T1	136951	742645	0	0
T2	89167	0	0	0
T3	385455	127897	0	0
T4	617	0	0	0
T5	1625	0	0	0
T6	702	14	0	0
T7	816749	13517	0	0
T8	0	14740	0	0
T9	0	9975	0	0
T16	2577	0	0	0
T17	96549	27411	0	0
T18	27493	5697	0	0
T19	0	15357	0	0
T43	0	17235	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416163908	106246896	0	0
T1	136951	742645	0	0
T2	89167	0	0	0
T3	385455	127897	0	0
T4	617	0	0	0
T5	1625	0	0	0
T6	702	14	0	0
T7	816749	13517	0	0
T8	0	14740	0	0
T9	0	9975	0	0
T16	2577	0	0	0
T17	96549	27411	0	0
T18	27493	5697	0	0
T19	0	15357	0	0
T43	0	17235	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416163908	415308833	0	0
T1	136951	136946	0	0
T2	89167	85781	0	0
T3	385455	385439	0	0
T4	617	547	0	0
T5	1625	1484	0	0
T6	702	609	0	0
T7	816749	816602	0	0
T16	2577	2506	0	0
T17	96549	96452	0	0
T18	27493	27413	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416163908	415308833	0	0
T1	136951	136946	0	0
T2	89167	85781	0	0
T3	385455	385439	0	0
T4	617	547	0	0
T5	1625	1484	0	0
T6	702	609	0	0
T7	816749	816602	0	0
T16	2577	2506	0	0
T17	96549	96452	0	0
T18	27493	27413	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416163908	106246896	0	0
T1	136951	742645	0	0
T2	89167	0	0	0
T3	385455	127897	0	0
T4	617	0	0	0
T5	1625	0	0	0
T6	702	14	0	0
T7	816749	13517	0	0
T8	0	14740	0	0
T9	0	9975	0	0
T16	2577	0	0	0
T17	96549	27411	0	0
T18	27493	5697	0	0
T19	0	15357	0	0
T43	0	17235	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416163908	43405733	0	0
T1	136951	2520	0	0
T2	89167	0	0	0
T3	385455	524288	0	0
T4	617	0	0	0
T5	1625	0	0	0
T6	702	35	0	0
T7	816749	435650	0	0
T8	0	40007	0	0
T9	0	13388	0	0
T16	2577	0	0	0
T17	96549	1602	0	0
T18	27493	570	0	0
T19	0	41946	0	0
T20	0	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416163908	112044564	0	0
T1	136951	742645	0	0
T2	89167	0	0	0
T3	385455	127897	0	0
T4	617	0	0	0
T5	1625	0	0	0
T6	702	14	0	0
T7	816749	137046	0	0
T8	0	15482	0	0
T9	0	12362	0	0
T16	2577	0	0	0
T17	96549	27411	0	0
T18	27493	5697	0	0
T19	0	16073	0	0
T43	0	17235	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416163908	106246896	0	0
T1	136951	742645	0	0
T2	89167	0	0	0
T3	385455	127897	0	0
T4	617	0	0	0
T5	1625	0	0	0
T6	702	14	0	0
T7	816749	13517	0	0
T8	0	14740	0	0
T9	0	9975	0	0
T16	2577	0	0	0
T17	96549	27411	0	0
T18	27493	5697	0	0
T19	0	15357	0	0
T43	0	17235	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416163908	106246896	0	0
T1	136951	742645	0	0
T2	89167	0	0	0
T3	385455	127897	0	0
T4	617	0	0	0
T5	1625	0	0	0
T6	702	14	0	0
T7	816749	13517	0	0
T8	0	14740	0	0
T9	0	9975	0	0
T16	2577	0	0	0
T17	96549	27411	0	0
T18	27493	5697	0	0
T19	0	15357	0	0
T43	0	17235	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416163908	112044564	0	0
T1	136951	742645	0	0
T2	89167	0	0	0
T3	385455	127897	0	0
T4	617	0	0	0
T5	1625	0	0	0
T6	702	14	0	0
T7	816749	137046	0	0
T8	0	15482	0	0
T9	0	12362	0	0
T16	2577	0	0	0
T17	96549	27411	0	0
T18	27493	5697	0	0
T19	0	16073	0	0
T43	0	17235	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416163908	415308833	0	0
T1	136951	136946	0	0
T2	89167	85781	0	0
T3	385455	385439	0	0
T4	617	547	0	0
T5	1625	1484	0	0
T6	702	609	0	0
T7	816749	816602	0	0
T16	2577	2506	0	0
T17	96549	96452	0	0
T18	27493	27413	0	0