Unified Coverage Report :: Module Instance :: tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

Module Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	418652244	35662601	0	0
DepthKnown_A	418652244	417709661	0	0
RvalidKnown_A	418652244	417709661	0	0
WreadyKnown_A	418652244	417709661	0	0
gen_passthru_fifo.paramCheckPass	1276	1276	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418652244	35662601	0	0
T1	136951	684098	0	0
T2	89167	7774	0	0
T3	385455	3384	0	0
T4	617	148	0	0
T5	1625	117	0	0
T6	702	146	0	0
T7	816749	19973	0	0
T16	2577	151	0	0
T17	96549	42885	0	0
T18	27493	12618	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418652244	417709661	0	0
T1	136951	136946	0	0
T2	89167	85781	0	0
T3	385455	385439	0	0
T4	617	547	0	0
T5	1625	1484	0	0
T6	702	609	0	0
T7	816749	816602	0	0
T16	2577	2506	0	0
T17	96549	96452	0	0
T18	27493	27413	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418652244	417709661	0	0
T1	136951	136946	0	0
T2	89167	85781	0	0
T3	385455	385439	0	0
T4	617	547	0	0
T5	1625	1484	0	0
T6	702	609	0	0
T7	816749	816602	0	0
T16	2577	2506	0	0
T17	96549	96452	0	0
T18	27493	27413	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418652244	417709661	0	0
T1	136951	136946	0	0
T2	89167	85781	0	0
T3	385455	385439	0	0
T4	617	547	0	0
T5	1625	1484	0	0
T6	702	609	0	0
T7	816749	816602	0	0
T16	2577	2506	0	0
T17	96549	96452	0	0
T18	27493	27413	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1276	1276	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	418652244	38906079	0	0
DepthKnown_A	418652244	417709661	0	0
RvalidKnown_A	418652244	417709661	0	0
WreadyKnown_A	418652244	417709661	0	0
gen_passthru_fifo.paramCheckPass	1276	1276	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418652244	38906079	0	0
T1	136951	684098	0	0
T2	89167	35004	0	0
T3	385455	3384	0	0
T4	617	148	0	0
T5	1625	117	0	0
T6	702	146	0	0
T7	816749	19973	0	0
T16	2577	151	0	0
T17	96549	42885	0	0
T18	27493	12618	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418652244	417709661	0	0
T1	136951	136946	0	0
T2	89167	85781	0	0
T3	385455	385439	0	0
T4	617	547	0	0
T5	1625	1484	0	0
T6	702	609	0	0
T7	816749	816602	0	0
T16	2577	2506	0	0
T17	96549	96452	0	0
T18	27493	27413	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418652244	417709661	0	0
T1	136951	136946	0	0
T2	89167	85781	0	0
T3	385455	385439	0	0
T4	617	547	0	0
T5	1625	1484	0	0
T6	702	609	0	0
T7	816749	816602	0	0
T16	2577	2506	0	0
T17	96549	96452	0	0
T18	27493	27413	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418652244	417709661	0	0
T1	136951	136946	0	0
T2	89167	85781	0	0
T3	385455	385439	0	0
T4	617	547	0	0
T5	1625	1484	0	0
T6	702	609	0	0
T7	816749	816602	0	0
T16	2577	2506	0	0
T17	96549	96452	0	0
T18	27493	27413	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1276	1276	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	418652244	4225581	0	0
DepthKnown_A	418652244	417709661	0	0
RvalidKnown_A	418652244	417709661	0	0
WreadyKnown_A	418652244	417709661	0	0
gen_passthru_fifo.paramCheckPass	1276	1276	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418652244	4225581	0	0
T1	136951	7611	0	0
T2	89167	488	0	0
T3	385455	0	0	0
T4	617	2	0	0
T5	1625	3	0	0
T6	702	2	0	0
T7	816749	0	0	0
T16	2577	0	0	0
T17	96549	1190	0	0
T18	27493	774	0	0
T20	0	15	0	0
T23	0	2700	0	0
T43	0	1015	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418652244	417709661	0	0
T1	136951	136946	0	0
T2	89167	85781	0	0
T3	385455	385439	0	0
T4	617	547	0	0
T5	1625	1484	0	0
T6	702	609	0	0
T7	816749	816602	0	0
T16	2577	2506	0	0
T17	96549	96452	0	0
T18	27493	27413	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418652244	417709661	0	0
T1	136951	136946	0	0
T2	89167	85781	0	0
T3	385455	385439	0	0
T4	617	547	0	0
T5	1625	1484	0	0
T6	702	609	0	0
T7	816749	816602	0	0
T16	2577	2506	0	0
T17	96549	96452	0	0
T18	27493	27413	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418652244	417709661	0	0
T1	136951	136946	0	0
T2	89167	85781	0	0
T3	385455	385439	0	0
T4	617	547	0	0
T5	1625	1484	0	0
T6	702	609	0	0
T7	816749	816602	0	0
T16	2577	2506	0	0
T17	96549	96452	0	0
T18	27493	27413	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1276	1276	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	418652244	2729429	0	0
DepthKnown_A	418652244	417709661	0	0
RvalidKnown_A	418652244	417709661	0	0
WreadyKnown_A	418652244	417709661	0	0
gen_passthru_fifo.paramCheckPass	1276	1276	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418652244	2729429	0	0
T1	136951	7611	0	0
T2	89167	2136	0	0
T3	385455	0	0	0
T4	617	2	0	0
T5	1625	3	0	0
T6	702	2	0	0
T7	816749	0	0	0
T16	2577	0	0	0
T17	96549	1190	0	0
T18	27493	774	0	0
T20	0	15	0	0
T23	0	2700	0	0
T43	0	1015	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418652244	417709661	0	0
T1	136951	136946	0	0
T2	89167	85781	0	0
T3	385455	385439	0	0
T4	617	547	0	0
T5	1625	1484	0	0
T6	702	609	0	0
T7	816749	816602	0	0
T16	2577	2506	0	0
T17	96549	96452	0	0
T18	27493	27413	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418652244	417709661	0	0
T1	136951	136946	0	0
T2	89167	85781	0	0
T3	385455	385439	0	0
T4	617	547	0	0
T5	1625	1484	0	0
T6	702	609	0	0
T7	816749	816602	0	0
T16	2577	2506	0	0
T17	96549	96452	0	0
T18	27493	27413	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418652244	417709661	0	0
T1	136951	136946	0	0
T2	89167	85781	0	0
T3	385455	385439	0	0
T4	617	547	0	0
T5	1625	1484	0	0
T6	702	609	0	0
T7	816749	816602	0	0
T16	2577	2506	0	0
T17	96549	96452	0	0
T18	27493	27413	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1276	1276	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0