Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	318922	1		T1	2		T2	2		T3	1
all_values[1]	318922	1		T1	2		T2	2		T3	1
all_values[2]	318922	1		T1	2		T2	2		T3	1
all_values[3]	318922	1		T1	2		T2	2		T3	1
all_values[4]	318922	1		T1	2		T2	2		T3	1
all_values[5]	318922	1		T1	2		T2	2		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	10248	1		T1	12		T2	12		T3	6
auto[1]	1903284	1		T48	10548		T18	17712		T73	13386

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1545713	1		T1	11		T2	10		T3	6
auto[1]	367819	1		T1	1		T2	2		T4	4

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	1273	1		T1	2		T2	1		T3	1
all_values[0]	auto[0]	auto[1]	417	1		T2	1		T4	1		T16	1
all_values[0]	auto[1]	auto[0]	248197	1		T48	1758		T18	2952		T73	2231
all_values[0]	auto[1]	auto[1]	69035	1		T70	2381		T71	3176		T72	2593
all_values[1]	auto[0]	auto[0]	1636	1		T1	2		T2	2		T3	1
all_values[1]	auto[0]	auto[1]	73	1		T261	3		T262	2		T344	4
all_values[1]	auto[1]	auto[0]	277033	1		T48	1758		T18	2952		T73	2231
all_values[1]	auto[1]	auto[1]	40180	1		T70	3953		T71	4153		T72	4637
all_values[2]	auto[0]	auto[0]	1589	1		T1	2		T2	2		T3	1
all_values[2]	auto[0]	auto[1]	131	1		T4	1		T74	1		T75	1
all_values[2]	auto[1]	auto[0]	309796	1		T48	1758		T18	2952		T73	2226
all_values[2]	auto[1]	auto[1]	7406	1		T73	5		T34	56		T76	24
all_values[3]	auto[0]	auto[0]	1557	1		T1	2		T2	2		T3	1
all_values[3]	auto[0]	auto[1]	156	1		T4	1		T74	1		T25	1
all_values[3]	auto[1]	auto[0]	164574	1		T48	879		T18	794		T73	259
all_values[3]	auto[1]	auto[1]	152635	1		T48	879		T18	2158		T73	1972
all_values[4]	auto[0]	auto[0]	1181	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	530	1		T1	1		T2	1		T4	1
all_values[4]	auto[1]	auto[0]	220182	1		T48	879		T18	2150		T73	1145
all_values[4]	auto[1]	auto[1]	97029	1		T48	879		T18	802		T73	1086
all_values[5]	auto[0]	auto[0]	1555	1		T1	2		T2	2		T3	1
all_values[5]	auto[0]	auto[1]	150	1		T7	1		T47	1		T41	1
all_values[5]	auto[1]	auto[0]	317140	1		T48	1758		T18	2952		T73	2231
all_values[5]	auto[1]	auto[1]	77	1		T260	2		T262	1		T345	3