---

Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.PrimRspPayLoad_A	0	0	439702502	0	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.LockArbDecision_A	0	0	439702502	0	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.ReqStaysHighUntilGranted0_M	0	0	439702502	0	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.LockArbDecision_A	0	0	439702502	0	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.ReqStaysHighUntilGranted0_M	0	0	439702502	0	0	0
tb.dut.u_prog_tl_gate.OutStandingOvfl_A	0	0	439702502	0	0	0
tb.dut.u_tl_gate.OutStandingOvfl_A	0	0	439702502	0	0	0
tb.dut.u_to_prog_fifo.rvalidHighReqFifoEmpty	0	0	439702502	0	0	0
tb.dut.u_to_prog_fifo.rvalidHighWhenRspFifoFull	0	0	439702502	0	0	0
tb.dut.u_to_prog_fifo.u_rspfifo.DataKnown_A	0	0	439702502	0	0	0
tb.dut.u_to_prog_fifo.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	439702502	0	0	0
tb.dut.u_to_prog_fifo.u_sramreqfifo.DataKnown_A	0	0	439702502	0	0	0
tb.dut.u_to_prog_fifo.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	439702502	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.FifoDepthCheck_A	0	0	1061	1061	0	0
tb.dut.FlashAddrKnown_A	0	0	439702502	301144142	0	0
tb.dut.FlashAddrKnown_AKnownEnable	0	0	439702502	438818875	0	0
tb.dut.FlashKnownO_A	0	0	439702502	438818875	0	0
tb.dut.FlashProgKnown_A	0	0	439702502	182883798	0	0
tb.dut.FlashProgKnown_AKnownEnable	0	0	439702502	438818875	0	0
tb.dut.FpvSecCmAddrCntAlertCheck_A	0	0	439702502	50	0	0
tb.dut.FpvSecCmArbFsmCheck_A	0	0	439702502	50	0	0
tb.dut.FpvSecCmLcCtrlFsmCheck_A	0	0	439702502	50	0	0
tb.dut.FpvSecCmLcCtrlRmaFsmCheck_A	0	0	439702502	50	0	0
tb.dut.FpvSecCmPageCntAlertCheck_A	0	0	439702502	50	0	0
tb.dut.FpvSecCmProgCnt_A	0	0	439702502	50	0	0
tb.dut.FpvSecCmRdCnt_A	0	0	439702502	50	0	0
tb.dut.FpvSecCmRdFifoRptrCheck_A	0	0	439702502	50	0	0
tb.dut.FpvSecCmRdFifoWptrCheck_A	0	0	439702502	50	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	439702502	50	0	0
tb.dut.FpvSecCmSeedCntAlertCheck_A	0	0	439702502	50	0	0
tb.dut.FpvSecCmTlLcGateFsm_A	0	0	439702502	50	0	0
tb.dut.FpvSecCmTlProgLcGateFsm_A	0	0	439702502	50	0	0
tb.dut.FpvSecCmWipeIdx_A	0	0	439702502	50	0	0
tb.dut.FpvSecCmWordCntAlertCheck_A	0	0	439702502	50	0	0
tb.dut.IntrErrO_A	0	0	439702502	438818875	0	0
tb.dut.IntrOpDoneKnownO_A	0	0	439702502	438818875	0	0
tb.dut.IntrProgEmptyKnownO_A	0	0	439702502	438818875	0	0
tb.dut.IntrProgLvlKnownO_A	0	0	439702502	438818875	0	0
tb.dut.IntrProgRdFullKnownO_A	0	0	439702502	438818875	0	0
tb.dut.IntrRdLvlKnownO_A	0	0	439702502	438818875	0	0
tb.dut.MemRspPayLoad_A	0	0	439702502	5806283	0	0
tb.dut.MemRspPayLoad_AKnownEnable	0	0	439702502	438818875	0	0
tb.dut.MemTlAReadyKnownO_A	0	0	439702502	438818875	0	0
tb.dut.MemTlDValidKnownO_A	0	0	439702502	438818875	0	0
tb.dut.PrimRspPayLoad_AKnownEnable	0	0	439702502	438818875	0	0
tb.dut.PrimTlAReadyKnownO_A	0	0	439702502	438818875	0	0
tb.dut.PrimTlDValidKnownO_A	0	0	439702502	438818875	0	0
tb.dut.RspPayLoad_A	0	0	439484458	38097412	0	0
tb.dut.RspPayLoad_AKnownEnable	0	0	439702502	438818875	0	0
tb.dut.TdoEnIsOne_A	0	0	439702502	438818875	0	0
tb.dut.TdoKnown_A	0	0	439702502	438818875	0	0
tb.dut.TlAReadyKnownO_A	0	0	439702502	438818875	0	0
tb.dut.TlDValidKnownO_A	0	0	439702502	438818875	0	0
tb.dut.flash_ctrl_core_csr_assert.TlulOOBAddrErr_A	0	0	442382404	4443	0	0
tb.dut.flash_ctrl_core_csr_assert.addr_rd_A	0	0	442382404	1368	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_0_rd_A	0	0	442382404	2146	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_1_rd_A	0	0	442382404	2045	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_2_rd_A	0	0	442382404	2207	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_3_rd_A	0	0	442382404	2307	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_4_rd_A	0	0	442382404	2108	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_5_rd_A	0	0	442382404	2242	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_6_rd_A	0	0	442382404	1568	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_7_rd_A	0	0	442382404	2233	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_8_rd_A	0	0	442382404	2064	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_9_rd_A	0	0	442382404	2156	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_0_rd_A	0	0	442382404	694	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_1_rd_A	0	0	442382404	1180	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_2_rd_A	0	0	442382404	1212	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_3_rd_A	0	0	442382404	1241	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_4_rd_A	0	0	442382404	1440	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_5_rd_A	0	0	442382404	1355	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_6_rd_A	0	0	442382404	1331	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_7_rd_A	0	0	442382404	1276	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_8_rd_A	0	0	442382404	1389	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_9_rd_A	0	0	442382404	1260	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info1_page_cfg_rd_A	0	0	442382404	1757	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info1_regwen_rd_A	0	0	442382404	1273	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_page_cfg_0_rd_A	0	0	442382404	1967	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_page_cfg_1_rd_A	0	0	442382404	2246	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_regwen_0_rd_A	0	0	442382404	1256	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_regwen_1_rd_A	0	0	442382404	835	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_0_rd_A	0	0	442382404	2042	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_1_rd_A	0	0	442382404	1697	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_2_rd_A	0	0	442382404	2147	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_3_rd_A	0	0	442382404	1586	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_4_rd_A	0	0	442382404	1640	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_5_rd_A	0	0	442382404	1780	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_6_rd_A	0	0	442382404	2207	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_7_rd_A	0	0	442382404	1571	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_8_rd_A	0	0	442382404	2116	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_9_rd_A	0	0	442382404	2103	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_0_rd_A	0	0	442382404	845	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_1_rd_A	0	0	442382404	1310	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_2_rd_A	0	0	442382404	812	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_3_rd_A	0	0	442382404	1352	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_4_rd_A	0	0	442382404	1466	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_5_rd_A	0	0	442382404	1345	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_6_rd_A	0	0	442382404	1330	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_7_rd_A	0	0	442382404	1204	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_8_rd_A	0	0	442382404	831	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_9_rd_A	0	0	442382404	1387	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info1_page_cfg_rd_A	0	0	442382404	1599	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info1_regwen_rd_A	0	0	442382404	1261	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_page_cfg_0_rd_A	0	0	442382404	2282	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_page_cfg_1_rd_A	0	0	442382404	2239	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_regwen_0_rd_A	0	0	442382404	1201	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_regwen_1_rd_A	0	0	442382404	845	0	0
tb.dut.flash_ctrl_core_csr_assert.bank_cfg_regwen_rd_A	0	0	442382404	872	0	0
tb.dut.flash_ctrl_core_csr_assert.default_region_rd_A	0	0	442382404	2160	0	0
tb.dut.flash_ctrl_core_csr_assert.exec_rd_A	0	0	442382404	1208	0	0
tb.dut.flash_ctrl_core_csr_assert.fifo_lvl_rd_A	0	0	442382404	1438	0	0
tb.dut.flash_ctrl_core_csr_assert.fifo_rst_rd_A	0	0	442382404	1351	0	0
tb.dut.flash_ctrl_core_csr_assert.hw_info_cfg_override_rd_A	0	0	442382404	947	0	0
tb.dut.flash_ctrl_core_csr_assert.intr_enable_rd_A	0	0	442382404	2077	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_0_rd_A	0	0	442382404	1404	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_1_rd_A	0	0	442382404	1445	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_2_rd_A	0	0	442382404	1476	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_3_rd_A	0	0	442382404	1532	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_4_rd_A	0	0	442382404	973	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_5_rd_A	0	0	442382404	969	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_6_rd_A	0	0	442382404	1533	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_7_rd_A	0	0	442382404	1515	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_0_rd_A	0	0	442382404	2056	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_1_rd_A	0	0	442382404	1903	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_2_rd_A	0	0	442382404	2208	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_3_rd_A	0	0	442382404	2285	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_4_rd_A	0	0	442382404	2332	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_5_rd_A	0	0	442382404	1987	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_6_rd_A	0	0	442382404	2039	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_7_rd_A	0	0	442382404	2255	0	0
tb.dut.flash_ctrl_core_csr_assert.phy_alert_cfg_rd_A	0	0	442382404	656	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_0_rd_A	0	0	442382404	1394	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_1_rd_A	0	0	442382404	1312	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_2_rd_A	0	0	442382404	1252	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_3_rd_A	0	0	442382404	1295	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_4_rd_A	0	0	442382404	852	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_5_rd_A	0	0	442382404	1411	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_6_rd_A	0	0	442382404	1273	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_7_rd_A	0	0	442382404	1372	0	0
tb.dut.flash_ctrl_core_csr_assert.scratch_rd_A	0	0	442382404	1076	0	0
tb.dut.gen_phy_assertions[0].FpvSecCmPhyFsmCheck_A	0	0	439702502	50	0	0
tb.dut.gen_phy_assertions[0].FpvSecCmPhyProgFsmCheck_A	0	0	439702502	50	0	0
tb.dut.gen_phy_assertions[1].FpvSecCmPhyFsmCheck_A	0	0	439702502	50	0	0
tb.dut.gen_phy_assertions[1].FpvSecCmPhyProgFsmCheck_A	0	0	439702502	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyHostCnt_A	0	0	439702502	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdDataFifoRPtr_A	0	0	439702502	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdDataFifoWPtr_A	0	0	439702502	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdRspFifoRPtr_A	0	0	439702502	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdRspFifoWPtr_A	0	0	439702502	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRspFifoRPtr_A	0	0	439702502	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRspFifoWPtr_A	0	0	439702502	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyHostCnt_A	0	0	439702502	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdDataFifoRPtr_A	0	0	439702502	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdDataFifoWPtr_A	0	0	439702502	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdRspFifoRPtr_A	0	0	439702502	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdRspFifoWPtr_A	0	0	439702502	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRspFifoRPtr_A	0	0	439702502	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRspFifoWPtr_A	0	0	439702502	50	0	0
tb.dut.gen_reg_we_assert_generic.FpvSecCmPrimRegWeOnehotCheck_A	0	0	439702502	30	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	442382185	36354583	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	442382185	441418588	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	442382185	441418588	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	442382185	38778406	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	442382185	441418588	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	442382185	441418588	0	0
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A	0	0	1271	1271	0	0
tb.dut.tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A	0	0	1271	1271	0	0
tb.dut.tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A	0	0	1271	1271	0	0
tb.dut.tlul_assert_device.gen_assert_final[102].noOutstandingReqsAtEndOfSim_A	0	0	1271	1271	0	0
tb.dut.tlul_assert_device.gen_assert_final[103].noOutstandingReqsAtEndOfSim_A	0	0	1271	1271	0	0
tb.dut.tlul_assert_device.gen_assert_final[104].noOutstandingReqsAtEndOfSim_A	0	0	1271	1271	0	0
tb.dut.tlul_assert_device.gen_assert_final[105].noOutstandingReqsAtEndOfSim_A	0	0	1271	1271	0	0
tb.dut.tlul_assert_device.gen_assert_final[106].noOutstandingReqsAtEndOfSim_A	0	0	1271	1271	0	0
tb.dut.tlul_assert_device.gen_assert_final[107].noOutstandingReqsAtEndOfSim_A	0	0	1271	1271	0	0
tb.dut.tlul_assert_device.gen_assert_final[108].noOutstandingReqsAtEndOfSim_A	0	0	1271	1271	0	0
tb.dut.tlul_assert_device.gen_assert_final[109].noOutstandingReqsAtEndOfSim_A	0	0	1271	1271	0	0
tb.dut.tlul_assert_device.gen_assert_final[10].noOutstandingReqsAtEndOfSim_A	0	0	1271	1271	0	0
tb.dut.tlul_assert_device.gen_assert_final[110].noOutstandingReqsAtEndOfSim_A	0	0	1271	1271	0	0
tb.dut.tlul_assert_device.gen_assert_final[111].noOutstandingReqsAtEndOfSim_A	0	0	1271	1271	0	0
tb.dut.tlul_assert_device.gen_assert_final[112].noOutstandingReqsAtEndOfSim_A	0	0	1271	1271	0	0
tb.dut.tlul_assert_device.gen_assert_final[113].noOutstandingReqsAtEndOfSim_A	0	0	1271	1271	0	0
tb.dut.tlul_assert_device.gen_assert_final[114].noOutstandingReqsAtEndOfSim_A	0	0	1271	1271	0	0
tb.dut.tlul_assert_device.gen_assert_final[115].noOutstandingReqsAtEndOfSim_A	0	0	1271	1271	0	0
tb.dut.tlul_assert_device.gen_assert_final[116].noOutstandingReqsAtEndOfSim_A	0	0	1271	1271	0	0
tb.dut.tlul_assert_device.gen_assert_final[117].noOutstandingReqsAtEndOfSim_A	0	0	1271	1271	0	0
tb.dut.tlul_assert_device.gen_assert_final[118].noOutstandingReqsAtEndOfSim_A	0	0	1271	1271	0	0
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tb.dut.tlul_assert_device.gen_assert_final[43].noOutstandingReqsAtEndOfSim_A	0	0	1271	1271	0	0
tb.dut.tlul_assert_device.gen_assert_final[44].noOutstandingReqsAtEndOfSim_A	0	0	1271	1271	0	0
tb.dut.tlul_assert_device.gen_assert_final[45].noOutstandingReqsAtEndOfSim_A	0	0	1271	1271	0	0
tb.dut.tlul_assert_device.gen_assert_final[46].noOutstandingReqsAtEndOfSim_A	0	0	1271	1271	0	0
tb.dut.tlul_assert_device.gen_assert_final[47].noOutstandingReqsAtEndOfSim_A	0	0	1271	1271	0	0
tb.dut.tlul_assert_device.gen_assert_final[48].noOutstandingReqsAtEndOfSim_A	0	0	1271	1271	0	0
tb.dut.tlul_assert_device.gen_assert_final[49].noOutstandingReqsAtEndOfSim_A	0	0	1271	1271	0	0
tb.dut.tlul_assert_device.gen_assert_final[4].noOutstandingReqsAtEndOfSim_A	0	0	1271	1271	0	0
tb.dut.tlul_assert_device.gen_assert_final[50].noOutstandingReqsAtEndOfSim_A	0	0	1271	1271	0	0
tb.dut.tlul_assert_device.gen_assert_final[51].noOutstandingReqsAtEndOfSim_A	0	0	1271	1271	0	0
tb.dut.tlul_assert_device.gen_assert_final[52].noOutstandingReqsAtEndOfSim_A	0	0	1271	1271	0	0
tb.dut.tlul_assert_device.gen_assert_final[53].noOutstandingReqsAtEndOfSim_A	0	0	1271	1271	0	0
tb.dut.tlul_assert_device.gen_assert_final[54].noOutstandingReqsAtEndOfSim_A	0	0	1271	1271	0	0
tb.dut.tlul_assert_device.gen_assert_final[55].noOutstandingReqsAtEndOfSim_A	0	0	1271	1271	0	0
tb.dut.tlul_assert_device.gen_assert_final[56].noOutstandingReqsAtEndOfSim_A	0	0	1271	1271	0	0
tb.dut.tlul_assert_device.gen_assert_final[57].noOutstandingReqsAtEndOfSim_A	0	0	1271	1271	0	0
tb.dut.tlul_assert_device.gen_assert_final[58].noOutstandingReqsAtEndOfSim_A	0	0	1271	1271	0	0
tb.dut.tlul_assert_device.gen_assert_final[59].noOutstandingReqsAtEndOfSim_A	0	0	1271	1271	0	0
tb.dut.tlul_assert_device.gen_assert_final[5].noOutstandingReqsAtEndOfSim_A	0	0	1271	1271	0	0
tb.dut.tlul_assert_device.gen_assert_final[60].noOutstandingReqsAtEndOfSim_A	0	0	1271	1271	0	0
tb.dut.tlul_assert_device.gen_assert_final[61].noOutstandingReqsAtEndOfSim_A	0	0	1271	1271	0	0
tb.dut.tlul_assert_device.gen_assert_final[62].noOutstandingReqsAtEndOfSim_A	0	0	1271	1271	0	0
tb.dut.tlul_assert_device.gen_assert_final[63].noOutstandingReqsAtEndOfSim_A	0	0	1271	1271	0	0
tb.dut.tlul_assert_device.gen_assert_final[64].noOutstandingReqsAtEndOfSim_A	0	0	1271	1271	0	0
tb.dut.tlul_assert_device.gen_assert_final[65].noOutstandingReqsAtEndOfSim_A	0	0	1271	1271	0	0
tb.dut.tlul_assert_device.gen_assert_final[66].noOutstandingReqsAtEndOfSim_A	0	0	1271	1271	0	0
tb.dut.tlul_assert_device.gen_assert_final[67].noOutstandingReqsAtEndOfSim_A	0	0	1271	1271	0	0
tb.dut.tlul_assert_device.gen_assert_final[68].noOutstandingReqsAtEndOfSim_A	0	0	1271	1271	0	0
tb.dut.tlul_assert_device.gen_assert_final[69].noOutstandingReqsAtEndOfSim_A	0	0	1271	1271	0	0
tb.dut.tlul_assert_device.gen_assert_final[6].noOutstandingReqsAtEndOfSim_A	0	0	1271	1271	0	0
tb.dut.tlul_assert_device.gen_assert_final[70].noOutstandingReqsAtEndOfSim_A	0	0	1271	1271	0	0
tb.dut.tlul_assert_device.gen_assert_final[71].noOutstandingReqsAtEndOfSim_A	0	0	1271	1271	0	0
tb.dut.tlul_assert_device.gen_assert_final[72].noOutstandingReqsAtEndOfSim_A	0	0	1271	1271	0	0
tb.dut.tlul_assert_device.gen_assert_final[73].noOutstandingReqsAtEndOfSim_A	0	0	1271	1271	0	0
tb.dut.tlul_assert_device.gen_assert_final[74].noOutstandingReqsAtEndOfSim_A	0	0	1271	1271	0	0
tb.dut.tlul_assert_device.gen_assert_final[75].noOutstandingReqsAtEndOfSim_A	0	0	1271	1271	0	0
tb.dut.tlul_assert_device.gen_assert_final[76].noOutstandingReqsAtEndOfSim_A	0	0	1271	1271	0	0
tb.dut.tlul_assert_device.gen_assert_final[77].noOutstandingReqsAtEndOfSim_A	0	0	1271	1271	0	0
tb.dut.tlul_assert_device.gen_assert_final[78].noOutstandingReqsAtEndOfSim_A	0	0	1271	1271	0	0
tb.dut.tlul_assert_device.gen_assert_final[79].noOutstandingReqsAtEndOfSim_A	0	0	1271	1271	0	0
tb.dut.tlul_assert_device.gen_assert_final[7].noOutstandingReqsAtEndOfSim_A	0	0	1271	1271	0	0
tb.dut.tlul_assert_device.gen_assert_final[80].noOutstandingReqsAtEndOfSim_A	0	0	1271	1271	0	0
tb.dut.tlul_assert_device.gen_assert_final[81].noOutstandingReqsAtEndOfSim_A	0	0	1271	1271	0	0
tb.dut.tlul_assert_device.gen_assert_final[82].noOutstandingReqsAtEndOfSim_A	0	0	1271	1271	0	0
tb.dut.tlul_assert_device.gen_assert_final[83].noOutstandingReqsAtEndOfSim_A	0	0	1271	1271	0	0
tb.dut.tlul_assert_device.gen_assert_final[84].noOutstandingReqsAtEndOfSim_A	0	0	1271	1271	0	0
tb.dut.tlul_assert_device.gen_assert_final[85].noOutstandingReqsAtEndOfSim_A	0	0	1271	1271	0	0
tb.dut.tlul_assert_device.gen_assert_final[86].noOutstandingReqsAtEndOfSim_A	0	0	1271	1271	0	0
tb.dut.tlul_assert_device.gen_assert_final[87].noOutstandingReqsAtEndOfSim_A	0	0	1271	1271	0	0
tb.dut.tlul_assert_device.gen_assert_final[88].noOutstandingReqsAtEndOfSim_A	0	0	1271	1271	0	0
tb.dut.tlul_assert_device.gen_assert_final[89].noOutstandingReqsAtEndOfSim_A	0	0	1271	1271	0	0
tb.dut.tlul_assert_device.gen_assert_final[8].noOutstandingReqsAtEndOfSim_A	0	0	1271	1271	0	0
tb.dut.tlul_assert_device.gen_assert_final[90].noOutstandingReqsAtEndOfSim_A	0	0	1271	1271	0	0
tb.dut.tlul_assert_device.gen_assert_final[91].noOutstandingReqsAtEndOfSim_A	0	0	1271	1271	0	0
tb.dut.tlul_assert_device.gen_assert_final[92].noOutstandingReqsAtEndOfSim_A	0	0	1271	1271	0	0
tb.dut.tlul_assert_device.gen_assert_final[93].noOutstandingReqsAtEndOfSim_A	0	0	1271	1271	0	0
tb.dut.tlul_assert_device.gen_assert_final[94].noOutstandingReqsAtEndOfSim_A	0	0	1271	1271	0	0
tb.dut.tlul_assert_device.gen_assert_final[95].noOutstandingReqsAtEndOfSim_A	0	0	1271	1271	0	0
tb.dut.tlul_assert_device.gen_assert_final[96].noOutstandingReqsAtEndOfSim_A	0	0	1271	1271	0	0
tb.dut.tlul_assert_device.gen_assert_final[97].noOutstandingReqsAtEndOfSim_A	0	0	1271	1271	0	0
tb.dut.tlul_assert_device.gen_assert_final[98].noOutstandingReqsAtEndOfSim_A	0	0	1271	1271	0	0
tb.dut.tlul_assert_device.gen_assert_final[99].noOutstandingReqsAtEndOfSim_A	0	0	1271	1271	0	0
tb.dut.tlul_assert_device.gen_assert_final[9].noOutstandingReqsAtEndOfSim_A	0	0	1271	1271	0	0
tb.dut.tlul_assert_device.gen_device.aDataKnown_M	0	0	442382899	8462875	0	0
tb.dut.tlul_assert_device.gen_device.addrSizeAlignedErr_A	0	0	442382185	6272	0	0
tb.dut.tlul_assert_device.gen_device.contigMask_M	0	0	442382899	31862589	0	0
tb.dut.tlul_assert_device.gen_device.dDataKnown_A	0	0	442164855	32223748	0	0
tb.dut.tlul_assert_device.gen_device.legalAOpcodeErr_A	0	0	442382185	5246	0	0
tb.dut.tlul_assert_device.gen_device.legalAParam_M	0	0	442382899	36354588	0	0
tb.dut.tlul_assert_device.gen_device.legalDParam_A	0	0	442382899	38778423	0	0
tb.dut.tlul_assert_device.gen_device.pendingReqPerSrc_M	0	0	442382899	36354588	0	0
tb.dut.tlul_assert_device.gen_device.respMustHaveReq_A	0	0	442382899	38778423	0	0
tb.dut.tlul_assert_device.gen_device.respOpcode_A	0	0	442382899	38778423	0	0
tb.dut.tlul_assert_device.gen_device.respSzEqReqSz_A	0	0	442382899	38778423	0	0
tb.dut.tlul_assert_device.gen_device.sizeGTEMaskErr_A	0	0	442382185	4603	0	0
tb.dut.tlul_assert_device.gen_device.sizeMatchesMaskErr_A	0	0	442382185	4728	0	0
tb.dut.tlul_assert_device.p_dbw.TlDbw_A	0	0	1276	1276	0	0
tb.dut.u_ctrl_arb.u_state_regs.AssertConnected_A	0	0	1061	1061	0	0
tb.dut.u_ctrl_arb.u_state_regs_A	0	0	439702721	438819094	0	0
tb.dut.u_disable_buf.NumCopiesMustBeGreaterZero_A	0	0	1061	1061	0	0
tb.dut.u_disable_buf.OutputsKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_disable_buf.gen_no_flops.OutputDelay_A	0	0	439702502	438818875	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.ArbCntMax_A	0	0	439702502	2376490	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.CtrlPrio_A	0	0	439702502	2376490	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.HostTransIdleChk_A	0	0	439702502	23448247	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.NoRemainder_A	0	0	1061	1061	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.OneHotReqs_A	0	0	439702502	438818875	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.Pow2Multiple_A	0	0	1061	1061	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.RdTxnCheck_A	0	0	439484458	438600831	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.OneDonePerTxn_A	0	0	439702502	1216551	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.PostPackRule_A	0	0	439702502	16755	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.PrePackRule_A	0	0	439702502	8744	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.WidthCheck_A	0	0	1061	1061	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.u_state_regs.AssertConnected_A	0	0	1061	1061	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.u_state_regs_A	0	0	439702502	438818875	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.NumCopiesMustBeGreaterZero_A	0	0	1061	1061	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.OutputsKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_no_flops.OutputDelay_A	0	0	439702502	438818875	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.CheckHotOne_A	0	0	439702502	438818875	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.CheckNGreaterZero_A	0	0	1061	1061	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.GntImpliesReady_A	0	0	439702502	121762903	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.GntImpliesValid_A	0	0	439702502	121762903	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.GrantKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.IdxKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.IndexIsCorrect_A	0	0	439702502	121762903	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.NoReadyValidNoGrant_A	0	0	439702502	47224648	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.Priority_A	0	0	439702502	128118363	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.ReadyAndValidImplyGrant_A	0	0	439702502	121762903	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.ReqAndReadyImplyGrant_A	0	0	439702502	121762903	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.ReqImpliesValid_A	0	0	439702502	128118363	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.ValidKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.CheckHotOne_A	0	0	439702502	438818875	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.CheckNGreaterZero_A	0	0	1061	1061	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.GntImpliesReady_A	0	0	439702502	121516329	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.GntImpliesValid_A	0	0	439702502	121516329	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.GrantKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.IdxKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.IndexIsCorrect_A	0	0	439702502	121516329	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.NoReadyValidNoGrant_A	0	0	439702502	47224648	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.Priority_A	0	0	439702502	127871789	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.ReadyAndValidImplyGrant_A	0	0	439702502	121516329	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.ReqAndReadyImplyGrant_A	0	0	439702502	121516329	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.ReqImpliesValid_A	0	0	439702502	127871789	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.ValidKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.BufferMatchEcc_A	0	0	439702502	844675	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.ExclusiveOps_A	0	0	439702502	438818875	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.ExclusiveProgHazard_A	0	0	439702502	438818875	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.ExclusiveState_A	0	0	439702502	438818875	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.ForwardCheck_A	0	0	439702502	2321625	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.IdleCheck_A	0	0	439702502	54428340	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.MaxBufs_A	0	0	1061	1061	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.OneHotAlloc_A	0	0	439702502	438818875	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.OneHotMatch_A	0	0	439702502	438818875	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.OneHotRspMatch_A	0	0	439702502	438818875	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.OneHotUpdate_A	0	0	439702502	438818875	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf.AllocCheck_A	0	0	439702502	729711	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf.UpdateCheck_A	0	0	439702502	729710	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf.AllocCheck_A	0	0	439702502	729575	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf.UpdateCheck_A	0	0	439702502	729574	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf.AllocCheck_A	0	0	439702502	729230	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf.UpdateCheck_A	0	0	439702502	729227	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf.AllocCheck_A	0	0	439702502	728868	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf.UpdateCheck_A	0	0	439702502	728864	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage.DataKnown_A	0	0	439702502	13287484	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage.DepthKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage.RvalidKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage.WreadyKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	439702502	13287484	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep.BufferDecrUnderRun_A	0	0	439702502	3762050	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep.BufferDepRsp_A	0	0	439702502	438818875	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep.BufferIncrOverFlow_A	0	0	439702502	3762061	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep.DepBufferRspOrder_A	0	0	439702502	9112380	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage.DataKnown_A	0	0	439484458	14206970	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage.DepthKnown_A	0	0	439484458	438600831	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage.RvalidKnown_A	0	0	439484458	438600831	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage.WreadyKnown_A	0	0	439484458	438600831	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	439484458	14206970	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo.DataKnown_A	0	0	439484458	54424642	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo.DepthKnown_A	0	0	439484458	438600831	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo.RvalidKnown_A	0	0	439484458	438600831	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo.WreadyKnown_A	0	0	439484458	438600831	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	439484458	54424642	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.CheckHotOne_A	0	0	439702502	438818875	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.CheckNGreaterZero_A	0	0	1061	1061	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.GntImpliesReady_A	0	0	439702502	2868401	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.GntImpliesValid_A	0	0	439702502	2868401	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.GrantKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.IdxKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.IndexIsCorrect_A	0	0	439702502	2868401	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.NoReadyValidNoGrant_A	0	0	439702502	307768006	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.ReadyAndValidImplyGrant_A	0	0	439702502	2868401	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.ReqAndReadyImplyGrant_A	0	0	439702502	2868401	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.ReqImpliesValid_A	0	0	439702502	125609193	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.RoundRobin_A	0	0	439702502	27105	0	1053
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.ValidKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_scramble.gen_gf_mult.u_mult.IntegerLoops_A	0	0	1061	1061	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_scramble.gen_gf_mult.u_mult.StagePow2_A	0	0	1061	1061	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_state_regs.AssertConnected_A	0	0	1061	1061	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_state_regs_A	0	0	439702502	438818875	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo.DataKnown_A	0	0	439484458	2918539	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo.DepthKnown_A	0	0	439484458	438600831	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo.RvalidKnown_A	0	0	439484458	438600831	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo.WreadyKnown_A	0	0	439484458	438600831	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	439484458	2918539	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.ArbCntMax_A	0	0	439702502	1997410	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.CtrlPrio_A	0	0	439702502	1997405	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.HostTransIdleChk_A	0	0	439702502	22682128	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.NoRemainder_A	0	0	1061	1061	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.OneHotReqs_A	0	0	439702502	438818875	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.Pow2Multiple_A	0	0	1061	1061	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.RdTxnCheck_A	0	0	439484458	438600831	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.OneDonePerTxn_A	0	0	439702502	1176387	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.PostPackRule_A	0	0	439702502	12927	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.PrePackRule_A	0	0	439702502	6225	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.WidthCheck_A	0	0	1061	1061	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.u_state_regs.AssertConnected_A	0	0	1061	1061	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.u_state_regs_A	0	0	439702502	438818875	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.NumCopiesMustBeGreaterZero_A	0	0	1061	1061	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.OutputsKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_no_flops.OutputDelay_A	0	0	439702502	438818875	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.CheckHotOne_A	0	0	439702502	438818875	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.CheckNGreaterZero_A	0	0	1061	1061	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.GntImpliesReady_A	0	0	439702502	101754003	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.GntImpliesValid_A	0	0	439702502	101754003	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.GrantKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.IdxKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.IndexIsCorrect_A	0	0	439702502	101754003	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.NoReadyValidNoGrant_A	0	0	439702502	43311693	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.Priority_A	0	0	439702502	107549031	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.ReadyAndValidImplyGrant_A	0	0	439702502	101754003	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.ReqAndReadyImplyGrant_A	0	0	439702502	101754003	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.ReqImpliesValid_A	0	0	439702502	107549031	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.ValidKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.CheckHotOne_A	0	0	439702502	438818875	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.CheckNGreaterZero_A	0	0	1061	1061	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.GntImpliesReady_A	0	0	439702502	101754003	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.GntImpliesValid_A	0	0	439702502	101754003	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.GrantKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.IdxKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.IndexIsCorrect_A	0	0	439702502	101754003	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.NoReadyValidNoGrant_A	0	0	439702502	43311693	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.Priority_A	0	0	439702502	107549031	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.ReadyAndValidImplyGrant_A	0	0	439702502	101754003	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.ReqAndReadyImplyGrant_A	0	0	439702502	101754003	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.ReqImpliesValid_A	0	0	439702502	107549031	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.ValidKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.BufferMatchEcc_A	0	0	439702502	642222	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.ExclusiveOps_A	0	0	439702502	438818875	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.ExclusiveProgHazard_A	0	0	439702502	438818875	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.ExclusiveState_A	0	0	439702502	438818875	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.ForwardCheck_A	0	0	439702502	1880461	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.IdleCheck_A	0	0	439702502	49969660	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.MaxBufs_A	0	0	1061	1061	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.OneHotAlloc_A	0	0	439702502	438818875	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.OneHotMatch_A	0	0	439702502	438818875	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.OneHotRspMatch_A	0	0	439702502	438818875	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.OneHotUpdate_A	0	0	439702502	438818875	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf.AllocCheck_A	0	0	439702502	673602	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf.UpdateCheck_A	0	0	439702502	673601	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf.AllocCheck_A	0	0	439702502	673595	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf.UpdateCheck_A	0	0	439702502	673593	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf.AllocCheck_A	0	0	439702502	673435	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf.UpdateCheck_A	0	0	439702502	673434	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf.AllocCheck_A	0	0	439702502	673129	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf.UpdateCheck_A	0	0	439702502	673129	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage.DataKnown_A	0	0	439702502	11738677	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage.DepthKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage.RvalidKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage.WreadyKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	439702502	11738677	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep.BufferDecrUnderRun_A	0	0	439702502	3335979	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep.BufferDepRsp_A	0	0	439702502	438818875	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep.BufferIncrOverFlow_A	0	0	439702502	3335986	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep.DepBufferRspOrder_A	0	0	439702503	7953982	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage.DataKnown_A	0	0	439484458	12732627	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage.DepthKnown_A	0	0	439484458	438600831	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage.RvalidKnown_A	0	0	439484458	438600831	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage.WreadyKnown_A	0	0	439484458	438600831	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	439484458	12732627	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo.DataKnown_A	0	0	439484458	49964453	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo.DepthKnown_A	0	0	439484458	438600831	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo.RvalidKnown_A	0	0	439484458	438600831	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo.WreadyKnown_A	0	0	439484458	438600831	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	439484458	49964453	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.CheckHotOne_A	0	0	439702502	438818875	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.CheckNGreaterZero_A	0	0	1061	1061	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.GntImpliesReady_A	0	0	439702502	2683434	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.GntImpliesValid_A	0	0	439702502	2683434	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.GrantKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.IdxKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.IndexIsCorrect_A	0	0	439702502	2683434	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.NoReadyValidNoGrant_A	0	0	439702502	315875982	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.ReadyAndValidImplyGrant_A	0	0	439702502	2683434	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.ReqAndReadyImplyGrant_A	0	0	439702502	2683434	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.ReqImpliesValid_A	0	0	439702502	118288489	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.RoundRobin_A	0	0	439702502	16473	0	1053
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.ValidKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_scramble.gen_gf_mult.u_mult.IntegerLoops_A	0	0	1061	1061	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_scramble.gen_gf_mult.u_mult.StagePow2_A	0	0	1061	1061	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_state_regs.AssertConnected_A	0	0	1061	1061	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_state_regs_A	0	0	439702502	438818875	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo.DataKnown_A	0	0	439484458	3106528	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo.DepthKnown_A	0	0	439484458	438600831	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo.RvalidKnown_A	0	0	439484458	438600831	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo.WreadyKnown_A	0	0	439484458	438600831	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	439484458	3106528	0	0
tb.dut.u_eflash.u_bank_sequence_fifo.DataKnown_A	0	0	439702502	34643248	0	0
tb.dut.u_eflash.u_bank_sequence_fifo.DepthKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_eflash.u_bank_sequence_fifo.RvalidKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_eflash.u_bank_sequence_fifo.WreadyKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_eflash.u_bank_sequence_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	439702502	34643248	0	0
tb.dut.u_eflash.u_disable_buf.NumCopiesMustBeGreaterZero_A	0	0	1061	1061	0	0
tb.dut.u_eflash.u_disable_buf.OutputsKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_eflash.u_disable_buf.gen_no_flops.OutputDelay_A	0	0	439702502	438818875	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic.DataBitsPerMaskCheck_A	0	0	1061	1061	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheck_A	0	0	439702502	20931772	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic.DataBitsPerMaskCheck_A	0	0	1061	1061	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheck_A	0	0	439702502	5202944	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic.DataBitsPerMaskCheck_A	0	0	1061	1061	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheck_A	0	0	439702502	5882570	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo.DataKnown_A	0	0	439702502	107027114	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo.DepthKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo.RvalidKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo.WreadyKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	439702502	107027114	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic.DataBitsPerMaskCheck_A	0	0	1061	1061	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheck_A	0	0	439702502	68962321	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic.DataBitsPerMaskCheck_A	0	0	1061	1061	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheck_A	0	0	439702502	6917886	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic.DataBitsPerMaskCheck_A	0	0	1061	1061	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheck_A	0	0	439702502	5858304	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic.DataBitsPerMaskCheck_A	0	0	1061	1061	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheck_A	0	0	439702502	5892372	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo.DataKnown_A	0	0	439702502	88219975	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo.DepthKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo.RvalidKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo.WreadyKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	439702502	88219975	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic.DataBitsPerMaskCheck_A	0	0	1061	1061	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheck_A	0	0	439702502	67964621	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.en2addrHit	0	0	442382185	56661	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.reAfterRv	0	0	442382185	56661	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.rePulse	0	0	442382185	37728	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_chk.PayLoadWidthCheck	0	0	1276	1276	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.AllowedLatency_A	0	0	1276	1276	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.MatchedWidthAssert	0	0	1276	1276	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.u_err.dataWidthOnly32_A	0	0	1276	1276	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A	0	0	1276	1276	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck	0	0	1276	1276	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_rsp_intg_gen.DataWidthCheck_A	0	0	1276	1276	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_rsp_intg_gen.PayLoadWidthCheck	0	0	1276	1276	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.wePulse	0	0	442382185	18933	0	0
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.NumCopiesMustBeGreaterZero_A	0	0	1061	1061	0	0
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.OutputsKnown_A	0	0	433650448	432766821	0	0
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_flops.OutputDelay_A	0	0	433650448	432732306	0	2769
tb.dut.u_flash_hw_if.DisableChk_A	0	0	427656319	6400696	0	45
tb.dut.u_flash_hw_if.ProgRdVerify_A	0	0	424075521	2043544	0	0
tb.dut.u_flash_hw_if.u_addr_sync_reqack.SyncReqAckAckNeedsReq	0	0	439702721	9771	0	0
tb.dut.u_flash_hw_if.u_addr_sync_reqack.SyncReqAckHoldReq	0	0	439608544	9438	0	0
tb.dut.u_flash_hw_if.u_data_sync_reqack.SyncReqAckAckNeedsReq	0	0	439702721	9732	0	0
tb.dut.u_flash_hw_if.u_data_sync_reqack.SyncReqAckHoldReq	0	0	424600703	9432	0	0
tb.dut.u_flash_hw_if.u_rma_state_regs.AssertConnected_A	0	0	1061	1061	0	0
tb.dut.u_flash_hw_if.u_rma_state_regs_A	0	0	439702721	438819094	0	0
tb.dut.u_flash_hw_if.u_state_regs.AssertConnected_A	0	0	1061	1061	0	0
tb.dut.u_flash_hw_if.u_state_regs_A	0	0	439702721	438819094	0	0
tb.dut.u_flash_hw_if.u_sync_rma_req.NumCopiesMustBeGreaterZero_A	0	0	1061	1061	0	0
tb.dut.u_flash_hw_if.u_sync_rma_req.OutputsKnown_A	0	0	433650667	432767040	0	0
tb.dut.u_flash_hw_if.u_sync_rma_req.gen_flops.OutputDelay_A	0	0	433650667	432732510	0	2769
tb.dut.u_flash_mp.BankEraseData_A	0	0	439702721	7866000	0	0
tb.dut.u_flash_mp.BankEraseInfo_A	0	0	439702721	11010720	0	0
tb.dut.u_flash_mp.DataReqToInfo_A	0	0	439702721	266703196	0	0
tb.dut.u_flash_mp.InReqOutReq_A	0	0	439702721	301255821	0	0
tb.dut.u_flash_mp.InfoReqToData_A	0	0	439702721	34552625	0	0
tb.dut.u_flash_mp.NoReqWhenErr_A	0	0	433412380	111426	0	0
tb.dut.u_flash_mp.bkEraseEnOnehot_A	0	0	439702721	18876720	0	0
tb.dut.u_flash_mp.hwInfoRuleOnehot_A	0	0	439702721	156080125	0	0
tb.dut.u_flash_mp.invalidReqOnehot_A	0	0	439702721	301144352	0	0
tb.dut.u_flash_mp.requestTypesOnehot_A	0	0	439702721	301144352	0	0
tb.dut.u_intr_corr_err.IntrTKind_A	0	0	1061	1061	0	0
tb.dut.u_intr_op_done.IntrTKind_A	0	0	1061	1061	0	0
tb.dut.u_intr_prog_empty.IntrTKind_A	0	0	1061	1061	0	0
tb.dut.u_intr_prog_lvl.IntrTKind_A	0	0	1061	1061	0	0
tb.dut.u_intr_rd_full.IntrTKind_A	0	0	1061	1061	0	0
tb.dut.u_intr_rd_lvl.IntrTKind_A	0	0	1061	1061	0	0
tb.dut.u_lc_escalation_en_sync.NumCopiesMustBeGreaterZero_A	0	0	1061	1061	0	0
tb.dut.u_lc_escalation_en_sync.OutputsKnown_A	0	0	433628502	432744875	0	0
tb.dut.u_lc_escalation_en_sync.gen_flops.OutputDelay_A	0	0	433628502	432710495	0	2619
tb.dut.u_lc_seed_hw_rd_en_sync.NumCopiesMustBeGreaterZero_A	0	0	1061	1061	0	0
tb.dut.u_lc_seed_hw_rd_en_sync.OutputsKnown_A	0	0	433650667	432767040	0	0
tb.dut.u_lc_seed_hw_rd_en_sync.gen_flops.OutputDelay_A	0	0	433650667	432732510	0	2769
tb.dut.u_prog_fifo.DataKnown_A	0	0	439702502	190397835	0	0
tb.dut.u_prog_fifo.DepthKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_prog_fifo.RvalidKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_prog_fifo.WreadyKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_prog_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	439702502	190397835	0	0
tb.dut.u_prog_tl_gate.u_err_en_sync.NumCopiesMustBeGreaterZero_A	0	0	1061	1061	0	0
tb.dut.u_prog_tl_gate.u_err_en_sync.OutputsKnown_A	0	0	433650448	432766821	0	0
tb.dut.u_prog_tl_gate.u_err_en_sync.gen_no_flops.OutputDelay_A	0	0	433650448	432766821	0	0
tb.dut.u_prog_tl_gate.u_state_regs.AssertConnected_A	0	0	1061	1061	0	0
tb.dut.u_prog_tl_gate.u_state_regs_A	0	0	439702502	438818875	0	0
tb.dut.u_prog_tl_gate.u_tlul_err_resp.u_intg_gen.DataWidthCheck_A	0	0	1061	1061	0	0
tb.dut.u_prog_tl_gate.u_tlul_err_resp.u_intg_gen.PayLoadWidthCheck	0	0	1061	1061	0	0
tb.dut.u_reg_core.en2addrHit	0	0	442382404	25716213	0	0
tb.dut.u_reg_core.reAfterRv	0	0	442382404	25716190	0	0
tb.dut.u_reg_core.rePulse	0	0	442382404	23430166	0	0
tb.dut.u_reg_core.u_chk.PayLoadWidthCheck	0	0	1276	1276	0	0
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_0.CheckSwAccessIsLegal_A	0	0	1276	1276	0	0
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_0.MubiIsNotYetSupported_A	0	0	442382404	441418807	0	0
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_1.CheckSwAccessIsLegal_A	0	0	1276	1276	0	0
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_1.MubiIsNotYetSupported_A	0	0	442382404	441418807	0	0
tb.dut.u_reg_core.u_reg_if.AllowedLatency_A	0	0	1276	1276	0	0
tb.dut.u_reg_core.u_reg_if.MatchedWidthAssert	0	0	1276	1276	0	0
tb.dut.u_reg_core.u_reg_if.u_err.dataWidthOnly32_A	0	0	1276	1276	0	0
tb.dut.u_reg_core.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A	0	0	1276	1276	0	0
tb.dut.u_reg_core.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck	0	0	1276	1276	0	0
tb.dut.u_reg_core.u_rsp_intg_gen.DataWidthCheck_A	0	0	1276	1276	0	0
tb.dut.u_reg_core.u_rsp_intg_gen.PayLoadWidthCheck	0	0	1276	1276	0	0
tb.dut.u_reg_core.u_socket.NotOverflowed_A	0	0	442382185	441418588	0	0
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.DataKnown_A	0	0	442382185	36354583	0	0
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.DepthKnown_A	0	0	442382185	441418588	0	0
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.RvalidKnown_A	0	0	442382185	441418588	0	0
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.WreadyKnown_A	0	0	442382185	441418588	0	0
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.gen_passthru_fifo.paramCheckPass	0	0	1276	1276	0	0
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.DataKnown_A	0	0	442382185	38778406	0	0
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.DepthKnown_A	0	0	442382185	441418588	0	0
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.RvalidKnown_A	0	0	442382185	441418588	0	0
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.WreadyKnown_A	0	0	442382185	441418588	0	0
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	1276	1276	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.DataKnown_A	0	0	442382185	6076260	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.DepthKnown_A	0	0	442382185	441418588	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.RvalidKnown_A	0	0	442382185	441418588	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.WreadyKnown_A	0	0	442382185	441418588	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass	0	0	1276	1276	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.DataKnown_A	0	0	442382185	3050646	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.DepthKnown_A	0	0	442382185	441418588	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.RvalidKnown_A	0	0	442382185	441418588	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.WreadyKnown_A	0	0	442382185	441418588	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	1276	1276	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.DataKnown_A	0	0	442382185	4115303	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.DepthKnown_A	0	0	442382185	441418588	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.RvalidKnown_A	0	0	442382185	441418588	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.WreadyKnown_A	0	0	442382185	441418588	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass	0	0	1276	1276	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.DataKnown_A	0	0	442382185	4327907	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.DepthKnown_A	0	0	442382185	441418588	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.RvalidKnown_A	0	0	442382185	441418588	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.WreadyKnown_A	0	0	442382185	441418588	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	1276	1276	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo.DataKnown_A	0	0	442382185	26095713	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo.DepthKnown_A	0	0	442382185	441418588	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo.RvalidKnown_A	0	0	442382185	441418588	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo.WreadyKnown_A	0	0	442382185	441418588	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass	0	0	1276	1276	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo.DataKnown_A	0	0	442382185	31399853	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo.DepthKnown_A	0	0	442382185	441418588	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo.RvalidKnown_A	0	0	442382185	441418588	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo.WreadyKnown_A	0	0	442382185	441418588	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	1276	1276	0	0
tb.dut.u_reg_core.u_socket.gen_err_resp.err_resp.u_intg_gen.DataWidthCheck_A	0	0	1276	1276	0	0
tb.dut.u_reg_core.u_socket.gen_err_resp.err_resp.u_intg_gen.PayLoadWidthCheck	0	0	1276	1276	0	0
tb.dut.u_reg_core.u_socket.maxN	0	0	1276	1276	0	0
tb.dut.u_reg_core.wePulse	0	0	442382404	2286024	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.InfoNoBiggerThanData_A	0	0	1061	1061	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.u_creator_mubi.OutputsKnown_A	0	0	439702721	438819094	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.u_owner_mubi.OutputsKnown_A	0	0	439702721	438819094	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.InfoNoBiggerThanData_A	0	0	1061	1061	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.u_creator_mubi.OutputsKnown_A	0	0	439702721	438819094	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.u_owner_mubi.OutputsKnown_A	0	0	439702721	438819094	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.InfoNoBiggerThanData_A	0	0	1061	1061	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.u_creator_mubi.OutputsKnown_A	0	0	439702721	438819094	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.u_owner_mubi.OutputsKnown_A	0	0	439702721	438819094	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.InfoNoBiggerThanData_A	0	0	1061	1061	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.u_creator_mubi.OutputsKnown_A	0	0	439702721	438819094	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.u_owner_mubi.OutputsKnown_A	0	0	439702721	438819094	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.InfoNoBiggerThanData_A	0	0	1061	1061	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.u_creator_mubi.OutputsKnown_A	0	0	439702721	438819094	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.u_owner_mubi.OutputsKnown_A	0	0	439702721	438819094	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.InfoNoBiggerThanData_A	0	0	1061	1061	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.u_creator_mubi.OutputsKnown_A	0	0	439702721	438819094	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.u_owner_mubi.OutputsKnown_A	0	0	439702721	438819094	0	0
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.NumCopiesMustBeGreaterZero_A	0	0	1061	1061	0	0
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.OutputsKnown_A	0	0	433650667	432767040	0	0
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.gen_flops.OutputDelay_A	0	0	433650667	432732510	0	2769
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.NumCopiesMustBeGreaterZero_A	0	0	1061	1061	0	0
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.OutputsKnown_A	0	0	433650667	432767040	0	0
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.gen_flops.OutputDelay_A	0	0	433650667	432732510	0	2769
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.NumCopiesMustBeGreaterZero_A	0	0	1061	1061	0	0
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.OutputsKnown_A	0	0	433650667	432767040	0	0
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_flops.OutputDelay_A	0	0	433650667	432732510	0	2769
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.NumCopiesMustBeGreaterZero_A	0	0	1061	1061	0	0
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.OutputsKnown_A	0	0	433650667	432767040	0	0
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.gen_flops.OutputDelay_A	0	0	433650667	432732510	0	2769
tb.dut.u_sw_rd_fifo.DataKnown_A	0	0	439702502	51621438	0	0
tb.dut.u_sw_rd_fifo.DepthKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_sw_rd_fifo.RvalidKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_sw_rd_fifo.WreadyKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_sw_rd_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	439702502	51621438	0	0
tb.dut.u_tl_adapter_eflash.AddrOutKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_tl_adapter_eflash.DataIntgOptions_A	0	0	1061	1061	0	0
tb.dut.u_tl_adapter_eflash.ReqOutKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_tl_adapter_eflash.SramDwHasByteGranularity_A	0	0	1061	1061	0	0
tb.dut.u_tl_adapter_eflash.SramDwIsMultipleOfTlulWidth_A	0	0	1061	1061	0	0
tb.dut.u_tl_adapter_eflash.TlOutKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_tl_adapter_eflash.TlOutPayloadKnown_A	0	0	439702502	5805980	0	0
tb.dut.u_tl_adapter_eflash.TlOutPayloadKnown_AKnownEnable	0	0	439702502	438818875	0	0
tb.dut.u_tl_adapter_eflash.WdataOutKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_tl_adapter_eflash.WeOutKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_tl_adapter_eflash.WmaskOutKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_tl_adapter_eflash.adapterNoReadOrWrite	0	0	1061	1061	0	0
tb.dut.u_tl_adapter_eflash.gen_cmd_intg_check.u_cmd_intg_chk.PayLoadWidthCheck	0	0	1061	1061	0	0
tb.dut.u_tl_adapter_eflash.rvalidHighReqFifoEmpty	0	0	439702502	4453941	0	0
tb.dut.u_tl_adapter_eflash.rvalidHighWhenRspFifoFull	0	0	439702502	4453941	0	0
tb.dut.u_tl_adapter_eflash.u_err.dataWidthOnly32_A	0	0	1061	1061	0	0
tb.dut.u_tl_adapter_eflash.u_reqfifo.DataKnown_A	0	0	439702502	35995036	0	0
tb.dut.u_tl_adapter_eflash.u_reqfifo.DepthKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_tl_adapter_eflash.u_reqfifo.RvalidKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_tl_adapter_eflash.u_reqfifo.WreadyKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_tl_adapter_eflash.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	439702502	35995036	0	0
tb.dut.u_tl_adapter_eflash.u_rsp_gen.DataWidthCheck_A	0	0	1061	1061	0	0
tb.dut.u_tl_adapter_eflash.u_rsp_gen.PayLoadWidthCheck	0	0	1061	1061	0	0
tb.dut.u_tl_adapter_eflash.u_rspfifo.DataKnown_A	0	0	439702502	5798658	0	0
tb.dut.u_tl_adapter_eflash.u_rspfifo.DepthKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_tl_adapter_eflash.u_rspfifo.RvalidKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_tl_adapter_eflash.u_rspfifo.WreadyKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_tl_adapter_eflash.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	439702502	5798658	0	0
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.DataKnown_A	0	0	439702502	34643248	0	0
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.DepthKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.RvalidKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.WreadyKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	439702502	34643248	0	0
tb.dut.u_tl_gate.u_err_en_sync.NumCopiesMustBeGreaterZero_A	0	0	1061	1061	0	0
tb.dut.u_tl_gate.u_err_en_sync.OutputsKnown_A	0	0	433650448	432766821	0	0
tb.dut.u_tl_gate.u_err_en_sync.gen_no_flops.OutputDelay_A	0	0	433650448	432766821	0	0
tb.dut.u_tl_gate.u_state_regs.AssertConnected_A	0	0	1061	1061	0	0
tb.dut.u_tl_gate.u_state_regs_A	0	0	439702502	438818875	0	0
tb.dut.u_tl_gate.u_tlul_err_resp.u_intg_gen.DataWidthCheck_A	0	0	1061	1061	0	0
tb.dut.u_tl_gate.u_tlul_err_resp.u_intg_gen.PayLoadWidthCheck	0	0	1061	1061	0	0
tb.dut.u_to_prog_fifo.AddrOutKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_to_prog_fifo.DataIntgOptions_A	0	0	1061	1061	0	0
tb.dut.u_to_prog_fifo.ReqOutKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_to_prog_fifo.SramDwHasByteGranularity_A	0	0	1061	1061	0	0
tb.dut.u_to_prog_fifo.SramDwIsMultipleOfTlulWidth_A	0	0	1061	1061	0	0
tb.dut.u_to_prog_fifo.TlOutKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_to_prog_fifo.TlOutPayloadKnown_A	0	0	439702502	3023440	0	0
tb.dut.u_to_prog_fifo.TlOutPayloadKnown_AKnownEnable	0	0	439702502	438818875	0	0
tb.dut.u_to_prog_fifo.WdataOutKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_to_prog_fifo.WeOutKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_to_prog_fifo.WmaskOutKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_to_prog_fifo.adapterNoReadOrWrite	0	0	1061	1061	0	0
tb.dut.u_to_prog_fifo.u_err.dataWidthOnly32_A	0	0	1061	1061	0	0
tb.dut.u_to_prog_fifo.u_reqfifo.DataKnown_A	0	0	439702502	3023440	0	0
tb.dut.u_to_prog_fifo.u_reqfifo.DepthKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_to_prog_fifo.u_reqfifo.RvalidKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_to_prog_fifo.u_reqfifo.WreadyKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_to_prog_fifo.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	439702502	3023440	0	0
tb.dut.u_to_prog_fifo.u_rsp_gen.DataWidthCheck_A	0	0	1061	1061	0	0
tb.dut.u_to_prog_fifo.u_rsp_gen.PayLoadWidthCheck	0	0	1061	1061	0	0
tb.dut.u_to_prog_fifo.u_rspfifo.DepthKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_to_prog_fifo.u_rspfifo.RvalidKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_to_prog_fifo.u_rspfifo.WreadyKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_to_prog_fifo.u_sramreqfifo.DepthKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_to_prog_fifo.u_sramreqfifo.RvalidKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_to_prog_fifo.u_sramreqfifo.WreadyKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_to_rd_fifo.AddrOutKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_to_rd_fifo.DataIntgOptions_A	0	0	1061	1061	0	0
tb.dut.u_to_rd_fifo.ReqOutKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_to_rd_fifo.SramDwHasByteGranularity_A	0	0	1061	1061	0	0
tb.dut.u_to_rd_fifo.SramDwIsMultipleOfTlulWidth_A	0	0	1061	1061	0	0
tb.dut.u_to_rd_fifo.TlOutKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_to_rd_fifo.TlOutPayloadKnown_A	0	0	439702502	4323888	0	0
tb.dut.u_to_rd_fifo.TlOutPayloadKnown_AKnownEnable	0	0	439702502	438818875	0	0
tb.dut.u_to_rd_fifo.WdataOutKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_to_rd_fifo.WeOutKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_to_rd_fifo.WmaskOutKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_to_rd_fifo.adapterNoReadOrWrite	0	0	1061	1061	0	0
tb.dut.u_to_rd_fifo.rvalidHighReqFifoEmpty	0	0	439702502	3148833	0	0
tb.dut.u_to_rd_fifo.rvalidHighWhenRspFifoFull	0	0	439040249	3142525	0	0
tb.dut.u_to_rd_fifo.u_err.dataWidthOnly32_A	0	0	1061	1061	0	0
tb.dut.u_to_rd_fifo.u_reqfifo.DataKnown_A	0	0	439702502	4323888	0	0
tb.dut.u_to_rd_fifo.u_reqfifo.DepthKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_to_rd_fifo.u_reqfifo.RvalidKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_to_rd_fifo.u_reqfifo.WreadyKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_to_rd_fifo.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	439702502	4323888	0	0
tb.dut.u_to_rd_fifo.u_rsp_gen.DataWidthCheck_A	0	0	1061	1061	0	0
tb.dut.u_to_rd_fifo.u_rsp_gen.PayLoadWidthCheck	0	0	1061	1061	0	0
tb.dut.u_to_rd_fifo.u_rspfifo.DataKnown_A	0	0	439484458	4316418	0	0
tb.dut.u_to_rd_fifo.u_rspfifo.DepthKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_to_rd_fifo.u_rspfifo.RvalidKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_to_rd_fifo.u_rspfifo.WreadyKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_to_rd_fifo.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	439702502	4327376	0	0
tb.dut.u_to_rd_fifo.u_sramreqfifo.DataKnown_A	0	0	439702502	3148833	0	0
tb.dut.u_to_rd_fifo.u_sramreqfifo.DepthKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_to_rd_fifo.u_sramreqfifo.RvalidKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_to_rd_fifo.u_sramreqfifo.WreadyKnown_A	0	0	439702502	438818875	0	0
tb.dut.u_to_rd_fifo.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	439702502	3148833	0	0

Assertions Incomplete:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.RoundRobin_A	0	0	439702502	27105	0	1053
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.RoundRobin_A	0	0	439702502	16473	0	1053
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_flops.OutputDelay_A	0	0	433650448	432732306	0	2769
tb.dut.u_flash_hw_if.DisableChk_A	0	0	427656319	6400696	0	45
tb.dut.u_flash_hw_if.u_sync_rma_req.gen_flops.OutputDelay_A	0	0	433650667	432732510	0	2769
tb.dut.u_lc_escalation_en_sync.gen_flops.OutputDelay_A	0	0	433628502	432710495	0	2619
tb.dut.u_lc_seed_hw_rd_en_sync.gen_flops.OutputDelay_A	0	0	433650667	432732510	0	2769
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.gen_flops.OutputDelay_A	0	0	433650667	432732510	0	2769
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.gen_flops.OutputDelay_A	0	0	433650667	432732510	0	2769
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_flops.OutputDelay_A	0	0	433650667	432732510	0	2769
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.gen_flops.OutputDelay_A	0	0	433650667	432732510	0	2769

---

Detail Report for Cover Sequences

Cover Sequences Uncovered:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	442382899	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	442382899	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	442382899	0	0	0

Cover Sequences All Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	442382899	132672	132672	0
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	442382899	25	25	0
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	442382899	12	12	0
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	442382899	15	15	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	442382899	11404	11404	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	442382899	297605	297605	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	442382899	15766030	15766030	1248

Cover Sequences First Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	442382899	132672	132672	0
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	442382899	25	25	0
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	442382899	12	12	0
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	442382899	15	15	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	442382899	11404	11404	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	442382899	297605	297605	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	442382899	15766030	15766030	1248