Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
218 |
1 |
|
T20 |
12 |
|
T21 |
13 |
|
T59 |
12 |
| others[1] |
226 |
1 |
|
T20 |
5 |
|
T21 |
11 |
|
T8 |
3 |
| others[2] |
230 |
1 |
|
T20 |
12 |
|
T21 |
9 |
|
T8 |
3 |
| others[3] |
337 |
1 |
|
T24 |
2 |
|
T20 |
13 |
|
T21 |
12 |
| false |
119 |
1 |
|
T20 |
5 |
|
T21 |
7 |
|
T59 |
4 |
| true |
13615 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9026 |
1 |
|
T2 |
1 |
|
T5 |
7 |
|
T22 |
202 |
| others[1] |
1280 |
1 |
|
T1 |
1 |
|
T5 |
11 |
|
T6 |
1 |
| others[2] |
1261 |
1 |
|
T5 |
8 |
|
T189 |
1 |
|
T45 |
7 |
| others[3] |
2093 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
16 |
| false |
647 |
1 |
|
T5 |
5 |
|
T37 |
1 |
|
T45 |
10 |
| true |
438 |
1 |
|
T7 |
1 |
|
T16 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9064 |
1 |
|
T1 |
1 |
|
T5 |
15 |
|
T22 |
202 |
| others[1] |
1317 |
1 |
|
T5 |
7 |
|
T45 |
21 |
|
T18 |
1 |
| others[2] |
1169 |
1 |
|
T5 |
6 |
|
T169 |
1 |
|
T28 |
1 |
| others[3] |
2111 |
1 |
|
T2 |
1 |
|
T5 |
13 |
|
T17 |
1 |
| false |
666 |
1 |
|
T2 |
1 |
|
T5 |
6 |
|
T12 |
1 |
| true |
418 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
111 |
1 |
|
T31 |
1 |
|
T20 |
5 |
|
T21 |
3 |
| others[1] |
110 |
1 |
|
T20 |
1 |
|
T21 |
5 |
|
T59 |
2 |
| others[2] |
107 |
1 |
|
T24 |
1 |
|
T20 |
2 |
|
T21 |
4 |
| others[3] |
171 |
1 |
|
T7 |
1 |
|
T17 |
1 |
|
T47 |
1 |
| false |
50 |
1 |
|
T24 |
1 |
|
T20 |
1 |
|
T21 |
4 |
| true |
14196 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
252 |
1 |
|
T31 |
1 |
|
T20 |
12 |
|
T21 |
5 |
| others[1] |
235 |
1 |
|
T47 |
1 |
|
T20 |
9 |
|
T21 |
12 |
| others[2] |
218 |
1 |
|
T111 |
1 |
|
T20 |
11 |
|
T21 |
11 |
| others[3] |
414 |
1 |
|
T6 |
1 |
|
T7 |
1 |
|
T24 |
1 |
| false |
129 |
1 |
|
T20 |
2 |
|
T21 |
7 |
|
T8 |
1 |
| true |
13497 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8873 |
1 |
|
T5 |
13 |
|
T22 |
202 |
|
T169 |
1 |
| others[1] |
1069 |
1 |
|
T5 |
13 |
|
T17 |
1 |
|
T189 |
1 |
| others[2] |
1085 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
8 |
| others[3] |
1790 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
11 |
| false |
559 |
1 |
|
T5 |
2 |
|
T45 |
6 |
|
T46 |
1 |
| true |
1369 |
1 |
|
T6 |
1 |
|
T29 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
210 |
1 |
|
T20 |
7 |
|
T21 |
8 |
|
T59 |
8 |
| others[1] |
247 |
1 |
|
T20 |
7 |
|
T21 |
10 |
|
T59 |
13 |
| others[2] |
233 |
1 |
|
T24 |
1 |
|
T20 |
14 |
|
T21 |
9 |
| others[3] |
383 |
1 |
|
T29 |
1 |
|
T20 |
16 |
|
T21 |
17 |
| false |
128 |
1 |
|
T20 |
7 |
|
T21 |
8 |
|
T136 |
7 |
| true |
13544 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
241 |
1 |
|
T20 |
11 |
|
T21 |
8 |
|
T8 |
1 |
| others[1] |
217 |
1 |
|
T7 |
1 |
|
T20 |
13 |
|
T21 |
8 |
| others[2] |
229 |
1 |
|
T20 |
8 |
|
T21 |
13 |
|
T8 |
1 |
| others[3] |
352 |
1 |
|
T17 |
1 |
|
T29 |
1 |
|
T24 |
1 |
| false |
118 |
1 |
|
T24 |
1 |
|
T47 |
1 |
|
T20 |
5 |
| true |
13588 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9058 |
1 |
|
T5 |
12 |
|
T22 |
202 |
|
T45 |
27 |
| others[1] |
1281 |
1 |
|
T2 |
1 |
|
T5 |
9 |
|
T45 |
17 |
| others[2] |
1234 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
7 |
| others[3] |
2077 |
1 |
|
T5 |
13 |
|
T17 |
1 |
|
T37 |
1 |
| false |
657 |
1 |
|
T5 |
6 |
|
T169 |
1 |
|
T45 |
11 |
| true |
438 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1275 |
1 |
|
T2 |
1 |
|
T5 |
6 |
|
T45 |
19 |
| others[1] |
1286 |
1 |
|
T2 |
1 |
|
T5 |
12 |
|
T45 |
19 |
| others[2] |
1212 |
1 |
|
T5 |
2 |
|
T45 |
19 |
|
T24 |
1 |
| others[3] |
2123 |
1 |
|
T1 |
1 |
|
T5 |
19 |
|
T17 |
1 |
| false |
663 |
1 |
|
T5 |
8 |
|
T169 |
1 |
|
T45 |
7 |
| true |
423 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
87 |
1 |
|
T20 |
1 |
|
T21 |
3 |
|
T59 |
2 |
| others[1] |
119 |
1 |
|
T17 |
1 |
|
T24 |
1 |
|
T20 |
3 |
| others[2] |
111 |
1 |
|
T24 |
1 |
|
T20 |
3 |
|
T21 |
2 |
| others[3] |
168 |
1 |
|
T31 |
1 |
|
T47 |
1 |
|
T20 |
2 |
| false |
54 |
1 |
|
T20 |
2 |
|
T21 |
1 |
|
T59 |
7 |
| true |
6443 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
237 |
1 |
|
T24 |
1 |
|
T36 |
1 |
|
T20 |
11 |
| others[1] |
222 |
1 |
|
T20 |
12 |
|
T21 |
9 |
|
T41 |
1 |
| others[2] |
242 |
1 |
|
T28 |
1 |
|
T20 |
14 |
|
T21 |
11 |
| others[3] |
399 |
1 |
|
T47 |
1 |
|
T73 |
1 |
|
T20 |
12 |
| false |
149 |
1 |
|
T24 |
1 |
|
T20 |
4 |
|
T21 |
6 |
| true |
5733 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1062 |
1 |
|
T2 |
1 |
|
T5 |
4 |
|
T7 |
1 |
| others[1] |
1045 |
1 |
|
T5 |
9 |
|
T29 |
1 |
|
T45 |
18 |
| others[2] |
1142 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
10 |
| others[3] |
1762 |
1 |
|
T5 |
15 |
|
T45 |
24 |
|
T31 |
1 |
| false |
555 |
1 |
|
T5 |
9 |
|
T6 |
1 |
|
T37 |
1 |
| true |
1416 |
1 |
|
T3 |
1 |
|
T16 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
209 |
1 |
|
T46 |
1 |
|
T20 |
11 |
|
T21 |
10 |
| others[1] |
211 |
1 |
|
T20 |
7 |
|
T21 |
5 |
|
T25 |
1 |
| others[2] |
234 |
1 |
|
T20 |
10 |
|
T21 |
8 |
|
T59 |
8 |
| others[3] |
387 |
1 |
|
T17 |
1 |
|
T20 |
15 |
|
T21 |
20 |
| false |
93 |
1 |
|
T20 |
3 |
|
T21 |
4 |
|
T59 |
6 |
| true |
5848 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
238 |
1 |
|
T29 |
1 |
|
T20 |
12 |
|
T21 |
11 |
| others[1] |
233 |
1 |
|
T20 |
12 |
|
T21 |
15 |
|
T59 |
11 |
| others[2] |
222 |
1 |
|
T24 |
1 |
|
T20 |
6 |
|
T21 |
12 |
| others[3] |
401 |
1 |
|
T20 |
23 |
|
T21 |
16 |
|
T42 |
1 |
| false |
113 |
1 |
|
T20 |
3 |
|
T21 |
2 |
|
T59 |
6 |
| true |
5775 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1237 |
1 |
|
T2 |
1 |
|
T5 |
9 |
|
T28 |
1 |
| others[1] |
1305 |
1 |
|
T5 |
11 |
|
T17 |
1 |
|
T37 |
1 |
| others[2] |
1288 |
1 |
|
T5 |
11 |
|
T45 |
17 |
|
T20 |
32 |
| others[3] |
2072 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
12 |
| false |
646 |
1 |
|
T1 |
1 |
|
T5 |
4 |
|
T45 |
12 |
| true |
434 |
1 |
|
T6 |
1 |
|
T7 |
1 |
|
T29 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1295 |
1 |
|
T5 |
12 |
|
T169 |
1 |
|
T45 |
21 |
| others[1] |
1208 |
1 |
|
T5 |
8 |
|
T37 |
1 |
|
T45 |
12 |
| others[2] |
1273 |
1 |
|
T5 |
8 |
|
T17 |
1 |
|
T12 |
1 |
| others[3] |
2157 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
14 |
| false |
632 |
1 |
|
T2 |
1 |
|
T5 |
5 |
|
T45 |
8 |
| true |
417 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
97 |
1 |
|
T20 |
3 |
|
T21 |
5 |
|
T59 |
3 |
| others[1] |
101 |
1 |
|
T17 |
1 |
|
T20 |
4 |
|
T21 |
6 |
| others[2] |
98 |
1 |
|
T20 |
4 |
|
T21 |
2 |
|
T59 |
3 |
| others[3] |
172 |
1 |
|
T24 |
1 |
|
T20 |
8 |
|
T21 |
7 |
| false |
55 |
1 |
|
T31 |
1 |
|
T24 |
1 |
|
T20 |
2 |
| true |
6459 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
256 |
1 |
|
T20 |
6 |
|
T21 |
5 |
|
T8 |
1 |
| others[1] |
234 |
1 |
|
T29 |
1 |
|
T31 |
1 |
|
T73 |
1 |
| others[2] |
218 |
1 |
|
T7 |
1 |
|
T47 |
1 |
|
T20 |
6 |
| others[3] |
365 |
1 |
|
T133 |
1 |
|
T20 |
17 |
|
T21 |
11 |
| false |
124 |
1 |
|
T17 |
1 |
|
T20 |
8 |
|
T21 |
7 |
| true |
5785 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1021 |
1 |
|
T5 |
4 |
|
T28 |
1 |
|
T45 |
18 |
| others[1] |
1064 |
1 |
|
T5 |
13 |
|
T37 |
1 |
|
T45 |
17 |
| others[2] |
1070 |
1 |
|
T2 |
1 |
|
T5 |
12 |
|
T16 |
1 |
| others[3] |
1844 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
12 |
| false |
578 |
1 |
|
T5 |
6 |
|
T45 |
12 |
|
T20 |
11 |
| true |
1405 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T29 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
233 |
1 |
|
T24 |
1 |
|
T20 |
9 |
|
T21 |
10 |
| others[1] |
248 |
1 |
|
T24 |
1 |
|
T73 |
1 |
|
T20 |
15 |
| others[2] |
231 |
1 |
|
T20 |
8 |
|
T21 |
11 |
|
T125 |
1 |
| others[3] |
363 |
1 |
|
T29 |
1 |
|
T31 |
1 |
|
T20 |
11 |
| false |
109 |
1 |
|
T20 |
4 |
|
T21 |
5 |
|
T41 |
1 |
| true |
5798 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
211 |
1 |
|
T20 |
8 |
|
T21 |
15 |
|
T8 |
1 |
| others[1] |
192 |
1 |
|
T31 |
1 |
|
T20 |
8 |
|
T21 |
6 |
| others[2] |
213 |
1 |
|
T20 |
7 |
|
T21 |
12 |
|
T42 |
1 |
| others[3] |
397 |
1 |
|
T24 |
1 |
|
T20 |
18 |
|
T21 |
14 |
| false |
117 |
1 |
|
T20 |
4 |
|
T21 |
5 |
|
T59 |
2 |
| true |
5852 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1256 |
1 |
|
T2 |
1 |
|
T5 |
11 |
|
T29 |
1 |
| others[1] |
1253 |
1 |
|
T5 |
7 |
|
T17 |
1 |
|
T189 |
1 |
| others[2] |
1296 |
1 |
|
T5 |
13 |
|
T12 |
1 |
|
T169 |
1 |
| others[3] |
2093 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
7 |
| false |
652 |
1 |
|
T5 |
9 |
|
T45 |
13 |
|
T20 |
6 |
| true |
432 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1219 |
1 |
|
T5 |
11 |
|
T45 |
16 |
|
T20 |
20 |
| others[1] |
1239 |
1 |
|
T2 |
1 |
|
T5 |
11 |
|
T45 |
19 |
| others[2] |
1381 |
1 |
|
T1 |
1 |
|
T5 |
10 |
|
T169 |
1 |
| others[3] |
2063 |
1 |
|
T2 |
1 |
|
T5 |
13 |
|
T17 |
1 |
| false |
665 |
1 |
|
T5 |
2 |
|
T45 |
9 |
|
T20 |
12 |
| true |
415 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
103 |
1 |
|
T24 |
1 |
|
T20 |
3 |
|
T21 |
4 |
| others[1] |
125 |
1 |
|
T20 |
4 |
|
T21 |
3 |
|
T59 |
5 |
| others[2] |
71 |
1 |
|
T17 |
1 |
|
T24 |
1 |
|
T20 |
1 |
| others[3] |
179 |
1 |
|
T20 |
6 |
|
T21 |
6 |
|
T125 |
1 |
| false |
58 |
1 |
|
T31 |
1 |
|
T20 |
3 |
|
T21 |
2 |
| true |
6446 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
237 |
1 |
|
T24 |
1 |
|
T133 |
1 |
|
T20 |
10 |
| others[1] |
240 |
1 |
|
T24 |
1 |
|
T20 |
10 |
|
T21 |
12 |
| others[2] |
241 |
1 |
|
T7 |
1 |
|
T20 |
18 |
|
T21 |
10 |
| others[3] |
391 |
1 |
|
T17 |
1 |
|
T29 |
1 |
|
T28 |
1 |
| false |
114 |
1 |
|
T20 |
3 |
|
T21 |
6 |
|
T59 |
4 |
| true |
5759 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1095 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
13 |
| others[1] |
1127 |
1 |
|
T5 |
5 |
|
T17 |
1 |
|
T45 |
17 |
| others[2] |
1100 |
1 |
|
T5 |
12 |
|
T29 |
1 |
|
T45 |
21 |
| others[3] |
1781 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
11 |
| false |
549 |
1 |
|
T5 |
6 |
|
T169 |
1 |
|
T45 |
8 |
| true |
1330 |
1 |
|
T6 |
1 |
|
T16 |
1 |
|
T47 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
231 |
1 |
|
T29 |
1 |
|
T24 |
1 |
|
T20 |
11 |
| others[1] |
241 |
1 |
|
T7 |
1 |
|
T73 |
1 |
|
T20 |
5 |
| others[2] |
241 |
1 |
|
T24 |
1 |
|
T20 |
13 |
|
T21 |
10 |
| others[3] |
397 |
1 |
|
T46 |
1 |
|
T20 |
19 |
|
T21 |
17 |
| false |
125 |
1 |
|
T17 |
1 |
|
T20 |
5 |
|
T21 |
5 |
| true |
5747 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
199 |
1 |
|
T17 |
1 |
|
T20 |
5 |
|
T21 |
5 |
| others[1] |
256 |
1 |
|
T7 |
1 |
|
T24 |
1 |
|
T20 |
9 |
| others[2] |
201 |
1 |
|
T20 |
10 |
|
T21 |
8 |
|
T8 |
1 |
| others[3] |
353 |
1 |
|
T20 |
13 |
|
T21 |
16 |
|
T8 |
3 |
| false |
128 |
1 |
|
T20 |
8 |
|
T21 |
3 |
|
T8 |
1 |
| true |
5845 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1278 |
1 |
|
T2 |
1 |
|
T5 |
9 |
|
T17 |
1 |
| others[1] |
1318 |
1 |
|
T5 |
13 |
|
T45 |
19 |
|
T31 |
1 |
| others[2] |
1233 |
1 |
|
T2 |
1 |
|
T5 |
6 |
|
T16 |
1 |
| others[3] |
2051 |
1 |
|
T1 |
1 |
|
T5 |
16 |
|
T29 |
1 |
| false |
672 |
1 |
|
T5 |
3 |
|
T45 |
7 |
|
T48 |
1 |
| true |
430 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1289 |
1 |
|
T5 |
10 |
|
T17 |
1 |
|
T45 |
18 |
| others[1] |
1333 |
1 |
|
T5 |
9 |
|
T189 |
1 |
|
T45 |
17 |
| others[2] |
1246 |
1 |
|
T2 |
1 |
|
T5 |
9 |
|
T37 |
1 |
| others[3] |
2060 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
| false |
638 |
1 |
|
T5 |
7 |
|
T45 |
8 |
|
T58 |
1 |
| true |
416 |
1 |
|
T6 |
1 |
|
T7 |
1 |
|
T16 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |