Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
104 |
1 |
|
T24 |
1 |
|
T20 |
3 |
|
T21 |
8 |
| others[1] |
95 |
1 |
|
T20 |
2 |
|
T21 |
1 |
|
T59 |
4 |
| others[2] |
119 |
1 |
|
T7 |
1 |
|
T20 |
6 |
|
T21 |
3 |
| others[3] |
181 |
1 |
|
T17 |
1 |
|
T31 |
1 |
|
T20 |
10 |
| false |
58 |
1 |
|
T24 |
1 |
|
T20 |
3 |
|
T21 |
1 |
| true |
6425 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
238 |
1 |
|
T24 |
1 |
|
T20 |
9 |
|
T21 |
13 |
| others[1] |
228 |
1 |
|
T7 |
1 |
|
T24 |
1 |
|
T20 |
14 |
| others[2] |
242 |
1 |
|
T6 |
1 |
|
T31 |
1 |
|
T20 |
8 |
| others[3] |
386 |
1 |
|
T28 |
1 |
|
T133 |
1 |
|
T20 |
17 |
| false |
99 |
1 |
|
T20 |
7 |
|
T21 |
5 |
|
T59 |
6 |
| true |
5789 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1094 |
1 |
|
T5 |
14 |
|
T37 |
1 |
|
T45 |
21 |
| others[1] |
1051 |
1 |
|
T2 |
1 |
|
T5 |
7 |
|
T29 |
1 |
| others[2] |
1084 |
1 |
|
T2 |
1 |
|
T5 |
11 |
|
T17 |
1 |
| others[3] |
1759 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T5 |
10 |
| false |
581 |
1 |
|
T5 |
5 |
|
T45 |
9 |
|
T24 |
1 |
| true |
1413 |
1 |
|
T6 |
1 |
|
T16 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
221 |
1 |
|
T20 |
14 |
|
T21 |
10 |
|
T125 |
1 |
| others[1] |
242 |
1 |
|
T20 |
7 |
|
T21 |
10 |
|
T42 |
1 |
| others[2] |
233 |
1 |
|
T24 |
1 |
|
T20 |
7 |
|
T21 |
8 |
| others[3] |
366 |
1 |
|
T7 |
1 |
|
T29 |
1 |
|
T46 |
1 |
| false |
111 |
1 |
|
T20 |
4 |
|
T21 |
6 |
|
T59 |
5 |
| true |
5809 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
205 |
1 |
|
T20 |
9 |
|
T21 |
12 |
|
T125 |
1 |
| others[1] |
226 |
1 |
|
T17 |
1 |
|
T31 |
1 |
|
T24 |
1 |
| others[2] |
220 |
1 |
|
T29 |
1 |
|
T20 |
10 |
|
T21 |
9 |
| others[3] |
374 |
1 |
|
T7 |
1 |
|
T24 |
1 |
|
T20 |
12 |
| false |
109 |
1 |
|
T20 |
5 |
|
T21 |
4 |
|
T8 |
4 |
| true |
5848 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1326 |
1 |
|
T1 |
1 |
|
T5 |
14 |
|
T169 |
1 |
| others[1] |
1253 |
1 |
|
T5 |
4 |
|
T17 |
1 |
|
T29 |
1 |
| others[2] |
1298 |
1 |
|
T5 |
15 |
|
T45 |
19 |
|
T24 |
1 |
| others[3] |
2040 |
1 |
|
T2 |
1 |
|
T5 |
8 |
|
T37 |
1 |
| false |
628 |
1 |
|
T2 |
1 |
|
T5 |
6 |
|
T45 |
8 |
| true |
437 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1273 |
1 |
|
T2 |
1 |
|
T5 |
11 |
|
T17 |
1 |
| others[1] |
1227 |
1 |
|
T5 |
8 |
|
T37 |
1 |
|
T45 |
17 |
| others[2] |
1279 |
1 |
|
T2 |
1 |
|
T5 |
4 |
|
T45 |
25 |
| others[3] |
2129 |
1 |
|
T1 |
1 |
|
T5 |
19 |
|
T6 |
1 |
| false |
656 |
1 |
|
T5 |
5 |
|
T169 |
1 |
|
T189 |
1 |
| true |
418 |
1 |
|
T3 |
1 |
|
T7 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
109 |
1 |
|
T31 |
1 |
|
T20 |
5 |
|
T21 |
4 |
| others[1] |
111 |
1 |
|
T20 |
5 |
|
T21 |
4 |
|
T42 |
1 |
| others[2] |
111 |
1 |
|
T20 |
2 |
|
T21 |
2 |
|
T59 |
4 |
| others[3] |
161 |
1 |
|
T17 |
1 |
|
T24 |
2 |
|
T20 |
5 |
| false |
63 |
1 |
|
T20 |
2 |
|
T21 |
2 |
|
T59 |
1 |
| true |
6427 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
229 |
1 |
|
T133 |
1 |
|
T20 |
15 |
|
T21 |
10 |
| others[1] |
239 |
1 |
|
T20 |
10 |
|
T21 |
13 |
|
T8 |
1 |
| others[2] |
272 |
1 |
|
T17 |
1 |
|
T20 |
6 |
|
T21 |
14 |
| others[3] |
382 |
1 |
|
T24 |
1 |
|
T47 |
1 |
|
T20 |
13 |
| false |
108 |
1 |
|
T31 |
1 |
|
T20 |
3 |
|
T21 |
4 |
| true |
5752 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1054 |
1 |
|
T1 |
1 |
|
T5 |
8 |
|
T7 |
1 |
| others[1] |
1059 |
1 |
|
T2 |
1 |
|
T5 |
9 |
|
T189 |
1 |
| others[2] |
1089 |
1 |
|
T5 |
7 |
|
T169 |
1 |
|
T28 |
1 |
| others[3] |
1848 |
1 |
|
T2 |
1 |
|
T5 |
15 |
|
T12 |
1 |
| false |
566 |
1 |
|
T5 |
8 |
|
T17 |
1 |
|
T29 |
1 |
| true |
1366 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
253 |
1 |
|
T29 |
1 |
|
T133 |
1 |
|
T20 |
8 |
| others[1] |
236 |
1 |
|
T73 |
1 |
|
T20 |
9 |
|
T21 |
5 |
| others[2] |
212 |
1 |
|
T20 |
10 |
|
T21 |
7 |
|
T125 |
1 |
| others[3] |
401 |
1 |
|
T24 |
1 |
|
T47 |
1 |
|
T20 |
11 |
| false |
111 |
1 |
|
T20 |
2 |
|
T21 |
5 |
|
T59 |
10 |
| true |
5769 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
221 |
1 |
|
T20 |
11 |
|
T21 |
9 |
|
T8 |
1 |
| others[1] |
232 |
1 |
|
T24 |
1 |
|
T20 |
15 |
|
T21 |
9 |
| others[2] |
218 |
1 |
|
T24 |
1 |
|
T47 |
1 |
|
T20 |
5 |
| others[3] |
353 |
1 |
|
T20 |
24 |
|
T21 |
14 |
|
T59 |
15 |
| false |
121 |
1 |
|
T17 |
1 |
|
T20 |
7 |
|
T21 |
4 |
| true |
5837 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1312 |
1 |
|
T5 |
4 |
|
T45 |
14 |
|
T46 |
1 |
| others[1] |
1255 |
1 |
|
T3 |
1 |
|
T5 |
11 |
|
T45 |
22 |
| others[2] |
1254 |
1 |
|
T5 |
9 |
|
T37 |
1 |
|
T45 |
19 |
| others[3] |
2060 |
1 |
|
T2 |
2 |
|
T5 |
21 |
|
T17 |
1 |
| false |
666 |
1 |
|
T1 |
1 |
|
T5 |
2 |
|
T169 |
1 |
| true |
435 |
1 |
|
T6 |
1 |
|
T7 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1254 |
1 |
|
T2 |
1 |
|
T5 |
10 |
|
T28 |
1 |
| others[1] |
1305 |
1 |
|
T1 |
1 |
|
T5 |
9 |
|
T6 |
1 |
| others[2] |
1233 |
1 |
|
T2 |
1 |
|
T5 |
12 |
|
T17 |
1 |
| others[3] |
2141 |
1 |
|
T5 |
12 |
|
T45 |
35 |
|
T194 |
1 |
| false |
629 |
1 |
|
T5 |
4 |
|
T45 |
6 |
|
T31 |
1 |
| true |
420 |
1 |
|
T3 |
1 |
|
T7 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
111 |
1 |
|
T20 |
4 |
|
T21 |
5 |
|
T59 |
4 |
| others[1] |
112 |
1 |
|
T20 |
4 |
|
T21 |
7 |
|
T59 |
2 |
| others[2] |
115 |
1 |
|
T17 |
1 |
|
T20 |
6 |
|
T21 |
4 |
| others[3] |
168 |
1 |
|
T31 |
1 |
|
T24 |
2 |
|
T20 |
11 |
| false |
52 |
1 |
|
T20 |
3 |
|
T21 |
1 |
|
T59 |
1 |
| true |
6424 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
228 |
1 |
|
T7 |
1 |
|
T36 |
1 |
|
T20 |
7 |
| others[1] |
230 |
1 |
|
T24 |
1 |
|
T133 |
1 |
|
T20 |
9 |
| others[2] |
234 |
1 |
|
T31 |
1 |
|
T24 |
1 |
|
T20 |
12 |
| others[3] |
387 |
1 |
|
T46 |
1 |
|
T47 |
1 |
|
T20 |
19 |
| false |
105 |
1 |
|
T17 |
1 |
|
T28 |
1 |
|
T20 |
2 |
| true |
5798 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1070 |
1 |
|
T2 |
1 |
|
T5 |
10 |
|
T37 |
1 |
| others[1] |
1158 |
1 |
|
T5 |
11 |
|
T6 |
1 |
|
T45 |
22 |
| others[2] |
1048 |
1 |
|
T1 |
1 |
|
T5 |
9 |
|
T45 |
24 |
| others[3] |
1782 |
1 |
|
T2 |
1 |
|
T5 |
12 |
|
T7 |
1 |
| false |
559 |
1 |
|
T5 |
5 |
|
T169 |
1 |
|
T189 |
1 |
| true |
1365 |
1 |
|
T3 |
1 |
|
T16 |
1 |
|
T29 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
249 |
1 |
|
T17 |
1 |
|
T20 |
15 |
|
T21 |
7 |
| others[1] |
214 |
1 |
|
T7 |
1 |
|
T133 |
1 |
|
T20 |
6 |
| others[2] |
241 |
1 |
|
T31 |
1 |
|
T73 |
1 |
|
T20 |
11 |
| others[3] |
380 |
1 |
|
T20 |
21 |
|
T21 |
19 |
|
T59 |
21 |
| false |
126 |
1 |
|
T20 |
3 |
|
T21 |
7 |
|
T59 |
5 |
| true |
5772 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
210 |
1 |
|
T29 |
1 |
|
T20 |
3 |
|
T21 |
10 |
| others[1] |
208 |
1 |
|
T24 |
2 |
|
T47 |
1 |
|
T20 |
12 |
| others[2] |
219 |
1 |
|
T7 |
1 |
|
T20 |
9 |
|
T21 |
9 |
| others[3] |
360 |
1 |
|
T20 |
18 |
|
T21 |
18 |
|
T8 |
1 |
| false |
115 |
1 |
|
T20 |
6 |
|
T21 |
9 |
|
T125 |
1 |
| true |
5870 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1296 |
1 |
|
T5 |
10 |
|
T45 |
16 |
|
T31 |
1 |
| others[1] |
1282 |
1 |
|
T5 |
5 |
|
T45 |
19 |
|
T48 |
1 |
| others[2] |
1311 |
1 |
|
T5 |
10 |
|
T45 |
16 |
|
T24 |
1 |
| others[3] |
2037 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
16 |
| false |
628 |
1 |
|
T2 |
1 |
|
T5 |
6 |
|
T17 |
1 |
| true |
428 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1261 |
1 |
|
T1 |
1 |
|
T5 |
6 |
|
T37 |
1 |
| others[1] |
1264 |
1 |
|
T5 |
12 |
|
T17 |
1 |
|
T169 |
1 |
| others[2] |
1333 |
1 |
|
T5 |
12 |
|
T45 |
17 |
|
T48 |
1 |
| others[3] |
2062 |
1 |
|
T2 |
2 |
|
T5 |
15 |
|
T45 |
29 |
| false |
650 |
1 |
|
T5 |
2 |
|
T45 |
15 |
|
T20 |
12 |
| true |
412 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
100 |
1 |
|
T20 |
4 |
|
T21 |
4 |
|
T136 |
4 |
| others[1] |
99 |
1 |
|
T17 |
1 |
|
T31 |
1 |
|
T24 |
1 |
| others[2] |
99 |
1 |
|
T20 |
3 |
|
T21 |
7 |
|
T59 |
8 |
| others[3] |
151 |
1 |
|
T24 |
1 |
|
T20 |
6 |
|
T21 |
4 |
| false |
56 |
1 |
|
T20 |
1 |
|
T21 |
1 |
|
T125 |
1 |
| true |
6477 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
195 |
1 |
|
T6 |
1 |
|
T20 |
14 |
|
T21 |
8 |
| others[1] |
232 |
1 |
|
T20 |
9 |
|
T21 |
7 |
|
T59 |
9 |
| others[2] |
243 |
1 |
|
T20 |
10 |
|
T21 |
12 |
|
T125 |
1 |
| others[3] |
424 |
1 |
|
T17 |
1 |
|
T29 |
1 |
|
T28 |
1 |
| false |
131 |
1 |
|
T20 |
6 |
|
T21 |
6 |
|
T134 |
1 |
| true |
5757 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1058 |
1 |
|
T3 |
1 |
|
T5 |
6 |
|
T7 |
1 |
| others[1] |
1080 |
1 |
|
T2 |
1 |
|
T5 |
10 |
|
T45 |
16 |
| others[2] |
1052 |
1 |
|
T1 |
1 |
|
T5 |
12 |
|
T17 |
1 |
| others[3] |
1830 |
1 |
|
T2 |
1 |
|
T5 |
13 |
|
T37 |
1 |
| false |
544 |
1 |
|
T5 |
6 |
|
T45 |
9 |
|
T24 |
1 |
| true |
1418 |
1 |
|
T6 |
1 |
|
T16 |
1 |
|
T29 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
231 |
1 |
|
T31 |
1 |
|
T24 |
1 |
|
T20 |
7 |
| others[1] |
222 |
1 |
|
T24 |
1 |
|
T73 |
1 |
|
T20 |
7 |
| others[2] |
244 |
1 |
|
T20 |
10 |
|
T21 |
12 |
|
T59 |
3 |
| others[3] |
374 |
1 |
|
T29 |
1 |
|
T46 |
1 |
|
T20 |
20 |
| false |
99 |
1 |
|
T133 |
1 |
|
T20 |
5 |
|
T21 |
8 |
| true |
5812 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
200 |
1 |
|
T20 |
6 |
|
T21 |
6 |
|
T125 |
1 |
| others[1] |
228 |
1 |
|
T20 |
12 |
|
T21 |
12 |
|
T8 |
1 |
| others[2] |
200 |
1 |
|
T47 |
1 |
|
T20 |
11 |
|
T21 |
9 |
| others[3] |
386 |
1 |
|
T24 |
1 |
|
T20 |
13 |
|
T21 |
16 |
| false |
129 |
1 |
|
T20 |
3 |
|
T21 |
5 |
|
T59 |
3 |
| true |
5839 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1280 |
1 |
|
T5 |
11 |
|
T17 |
1 |
|
T37 |
1 |
| others[1] |
1282 |
1 |
|
T5 |
4 |
|
T29 |
1 |
|
T12 |
1 |
| others[2] |
1218 |
1 |
|
T1 |
1 |
|
T5 |
6 |
|
T45 |
16 |
| others[3] |
2118 |
1 |
|
T2 |
2 |
|
T5 |
21 |
|
T45 |
29 |
| false |
648 |
1 |
|
T5 |
5 |
|
T189 |
1 |
|
T45 |
9 |
| true |
436 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1242 |
1 |
|
T2 |
1 |
|
T5 |
9 |
|
T45 |
16 |
| others[1] |
1259 |
1 |
|
T2 |
1 |
|
T5 |
17 |
|
T45 |
24 |
| others[2] |
1262 |
1 |
|
T1 |
1 |
|
T5 |
7 |
|
T169 |
1 |
| others[3] |
2164 |
1 |
|
T5 |
10 |
|
T17 |
1 |
|
T37 |
1 |
| false |
634 |
1 |
|
T5 |
4 |
|
T45 |
6 |
|
T48 |
1 |
| true |
421 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
118 |
1 |
|
T20 |
6 |
|
T21 |
4 |
|
T59 |
7 |
| others[1] |
106 |
1 |
|
T17 |
1 |
|
T20 |
5 |
|
T21 |
5 |
| others[2] |
109 |
1 |
|
T24 |
1 |
|
T21 |
5 |
|
T41 |
1 |
| others[3] |
188 |
1 |
|
T31 |
1 |
|
T24 |
1 |
|
T20 |
8 |
| false |
53 |
1 |
|
T20 |
4 |
|
T21 |
2 |
|
T125 |
1 |
| true |
6408 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
233 |
1 |
|
T36 |
1 |
|
T73 |
1 |
|
T20 |
10 |
| others[1] |
233 |
1 |
|
T6 |
1 |
|
T24 |
1 |
|
T133 |
1 |
| others[2] |
221 |
1 |
|
T20 |
8 |
|
T21 |
8 |
|
T59 |
9 |
| others[3] |
421 |
1 |
|
T7 |
1 |
|
T20 |
25 |
|
T21 |
20 |
| false |
107 |
1 |
|
T20 |
4 |
|
T21 |
6 |
|
T134 |
1 |
| true |
5767 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1063 |
1 |
|
T1 |
1 |
|
T5 |
11 |
|
T7 |
1 |
| others[1] |
1051 |
1 |
|
T5 |
6 |
|
T45 |
13 |
|
T20 |
16 |
| others[2] |
1094 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
15 |
| others[3] |
1808 |
1 |
|
T2 |
1 |
|
T5 |
14 |
|
T17 |
1 |
| false |
588 |
1 |
|
T5 |
1 |
|
T45 |
9 |
|
T105 |
1 |
| true |
1378 |
1 |
|
T6 |
1 |
|
T16 |
1 |
|
T29 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |