Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
228 |
1 |
|
T17 |
1 |
|
T31 |
1 |
|
T20 |
11 |
| others[1] |
222 |
1 |
|
T24 |
1 |
|
T20 |
6 |
|
T21 |
5 |
| others[2] |
228 |
1 |
|
T7 |
1 |
|
T133 |
1 |
|
T20 |
9 |
| others[3] |
379 |
1 |
|
T20 |
14 |
|
T21 |
19 |
|
T125 |
1 |
| false |
127 |
1 |
|
T20 |
7 |
|
T21 |
5 |
|
T59 |
5 |
| true |
5798 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
249 |
1 |
|
T20 |
9 |
|
T21 |
9 |
|
T8 |
1 |
| others[1] |
206 |
1 |
|
T20 |
9 |
|
T21 |
6 |
|
T125 |
1 |
| others[2] |
234 |
1 |
|
T7 |
1 |
|
T20 |
10 |
|
T21 |
14 |
| others[3] |
384 |
1 |
|
T29 |
1 |
|
T24 |
2 |
|
T20 |
10 |
| false |
102 |
1 |
|
T20 |
4 |
|
T21 |
3 |
|
T8 |
1 |
| true |
5807 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1227 |
1 |
|
T5 |
9 |
|
T45 |
16 |
|
T194 |
1 |
| others[1] |
1251 |
1 |
|
T2 |
1 |
|
T5 |
8 |
|
T189 |
1 |
| others[2] |
1267 |
1 |
|
T1 |
1 |
|
T5 |
11 |
|
T29 |
1 |
| others[3] |
2127 |
1 |
|
T2 |
1 |
|
T5 |
13 |
|
T17 |
1 |
| false |
674 |
1 |
|
T5 |
6 |
|
T45 |
10 |
|
T24 |
1 |
| true |
436 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1261 |
1 |
|
T5 |
8 |
|
T189 |
1 |
|
T45 |
19 |
| others[1] |
1264 |
1 |
|
T1 |
1 |
|
T5 |
8 |
|
T6 |
1 |
| others[2] |
1241 |
1 |
|
T2 |
1 |
|
T5 |
11 |
|
T37 |
1 |
| others[3] |
2155 |
1 |
|
T2 |
1 |
|
T5 |
17 |
|
T17 |
1 |
| false |
645 |
1 |
|
T5 |
3 |
|
T45 |
6 |
|
T46 |
1 |
| true |
416 |
1 |
|
T3 |
1 |
|
T7 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
89 |
1 |
|
T31 |
1 |
|
T20 |
9 |
|
T21 |
4 |
| others[1] |
103 |
1 |
|
T17 |
1 |
|
T20 |
2 |
|
T21 |
6 |
| others[2] |
94 |
1 |
|
T24 |
2 |
|
T20 |
4 |
|
T21 |
4 |
| others[3] |
180 |
1 |
|
T20 |
5 |
|
T21 |
5 |
|
T59 |
5 |
| false |
60 |
1 |
|
T20 |
4 |
|
T21 |
6 |
|
T59 |
5 |
| true |
6456 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
221 |
1 |
|
T36 |
1 |
|
T111 |
1 |
|
T20 |
7 |
| others[1] |
258 |
1 |
|
T3 |
1 |
|
T46 |
1 |
|
T20 |
12 |
| others[2] |
241 |
1 |
|
T20 |
8 |
|
T21 |
6 |
|
T41 |
1 |
| others[3] |
365 |
1 |
|
T24 |
1 |
|
T47 |
1 |
|
T20 |
12 |
| false |
125 |
1 |
|
T17 |
1 |
|
T20 |
11 |
|
T21 |
5 |
| true |
5772 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T5 |
47 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1101 |
1 |
|
T5 |
11 |
|
T45 |
20 |
|
T46 |
1 |
| others[1] |
1059 |
1 |
|
T2 |
1 |
|
T5 |
14 |
|
T45 |
16 |
| others[2] |
1051 |
1 |
|
T5 |
6 |
|
T45 |
15 |
|
T194 |
1 |
| others[3] |
1786 |
1 |
|
T2 |
1 |
|
T5 |
11 |
|
T17 |
1 |
| false |
576 |
1 |
|
T1 |
1 |
|
T5 |
5 |
|
T29 |
1 |
| true |
1409 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
235 |
1 |
|
T24 |
1 |
|
T20 |
6 |
|
T21 |
13 |
| others[1] |
244 |
1 |
|
T133 |
1 |
|
T20 |
24 |
|
T21 |
6 |
| others[2] |
231 |
1 |
|
T20 |
13 |
|
T21 |
13 |
|
T59 |
5 |
| others[3] |
380 |
1 |
|
T31 |
1 |
|
T20 |
16 |
|
T21 |
20 |
| false |
119 |
1 |
|
T20 |
3 |
|
T21 |
2 |
|
T125 |
1 |
| true |
5773 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
232 |
1 |
|
T29 |
1 |
|
T24 |
1 |
|
T20 |
11 |
| others[1] |
214 |
1 |
|
T20 |
15 |
|
T21 |
7 |
|
T59 |
10 |
| others[2] |
227 |
1 |
|
T20 |
12 |
|
T21 |
9 |
|
T8 |
2 |
| others[3] |
369 |
1 |
|
T24 |
1 |
|
T47 |
1 |
|
T20 |
12 |
| false |
99 |
1 |
|
T20 |
4 |
|
T21 |
6 |
|
T59 |
4 |
| true |
5841 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1270 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
11 |
| others[1] |
1255 |
1 |
|
T5 |
8 |
|
T45 |
17 |
|
T20 |
20 |
| others[2] |
1270 |
1 |
|
T5 |
9 |
|
T28 |
1 |
|
T45 |
21 |
| others[3] |
2058 |
1 |
|
T2 |
1 |
|
T5 |
16 |
|
T17 |
1 |
| false |
693 |
1 |
|
T5 |
3 |
|
T45 |
4 |
|
T48 |
1 |
| true |
436 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1266 |
1 |
|
T1 |
1 |
|
T5 |
5 |
|
T17 |
1 |
| others[1] |
1253 |
1 |
|
T5 |
10 |
|
T169 |
1 |
|
T28 |
1 |
| others[2] |
1248 |
1 |
|
T5 |
9 |
|
T37 |
1 |
|
T189 |
1 |
| others[3] |
2111 |
1 |
|
T5 |
20 |
|
T45 |
27 |
|
T24 |
1 |
| false |
688 |
1 |
|
T2 |
2 |
|
T5 |
3 |
|
T45 |
15 |
| true |
416 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
104 |
1 |
|
T20 |
1 |
|
T21 |
5 |
|
T59 |
5 |
| others[1] |
101 |
1 |
|
T20 |
1 |
|
T21 |
4 |
|
T125 |
1 |
| others[2] |
108 |
1 |
|
T20 |
5 |
|
T21 |
2 |
|
T59 |
3 |
| others[3] |
178 |
1 |
|
T17 |
1 |
|
T31 |
1 |
|
T24 |
2 |
| false |
58 |
1 |
|
T20 |
1 |
|
T59 |
1 |
|
T136 |
4 |
| true |
6433 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
228 |
1 |
|
T3 |
1 |
|
T24 |
1 |
|
T20 |
11 |
| others[1] |
225 |
1 |
|
T7 |
1 |
|
T29 |
1 |
|
T36 |
1 |
| others[2] |
243 |
1 |
|
T47 |
1 |
|
T20 |
15 |
|
T21 |
13 |
| others[3] |
387 |
1 |
|
T20 |
17 |
|
T21 |
14 |
|
T125 |
1 |
| false |
116 |
1 |
|
T21 |
5 |
|
T41 |
1 |
|
T59 |
3 |
| true |
5783 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T5 |
47 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1089 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T5 |
10 |
| others[1] |
1057 |
1 |
|
T5 |
13 |
|
T45 |
16 |
|
T46 |
1 |
| others[2] |
1072 |
1 |
|
T2 |
1 |
|
T5 |
9 |
|
T29 |
1 |
| others[3] |
1797 |
1 |
|
T5 |
13 |
|
T16 |
1 |
|
T45 |
24 |
| false |
544 |
1 |
|
T2 |
1 |
|
T5 |
2 |
|
T45 |
21 |
| true |
1423 |
1 |
|
T6 |
1 |
|
T12 |
1 |
|
T28 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
236 |
1 |
|
T20 |
15 |
|
T21 |
11 |
|
T59 |
9 |
| others[1] |
238 |
1 |
|
T29 |
1 |
|
T24 |
1 |
|
T133 |
1 |
| others[2] |
212 |
1 |
|
T20 |
15 |
|
T21 |
7 |
|
T125 |
1 |
| others[3] |
388 |
1 |
|
T46 |
1 |
|
T73 |
1 |
|
T20 |
10 |
| false |
133 |
1 |
|
T20 |
5 |
|
T21 |
3 |
|
T59 |
7 |
| true |
5775 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
219 |
1 |
|
T20 |
10 |
|
T21 |
11 |
|
T59 |
7 |
| others[1] |
207 |
1 |
|
T20 |
9 |
|
T21 |
5 |
|
T42 |
1 |
| others[2] |
216 |
1 |
|
T20 |
8 |
|
T21 |
8 |
|
T59 |
9 |
| others[3] |
359 |
1 |
|
T29 |
1 |
|
T31 |
1 |
|
T24 |
2 |
| false |
123 |
1 |
|
T20 |
10 |
|
T21 |
3 |
|
T59 |
3 |
| true |
5858 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1274 |
1 |
|
T2 |
2 |
|
T5 |
9 |
|
T45 |
25 |
| others[1] |
1315 |
1 |
|
T1 |
1 |
|
T5 |
12 |
|
T45 |
14 |
| others[2] |
1283 |
1 |
|
T5 |
7 |
|
T37 |
1 |
|
T45 |
18 |
| others[3] |
2053 |
1 |
|
T5 |
15 |
|
T169 |
1 |
|
T45 |
27 |
| false |
635 |
1 |
|
T5 |
4 |
|
T17 |
1 |
|
T189 |
1 |
| true |
422 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1249 |
1 |
|
T1 |
1 |
|
T5 |
5 |
|
T45 |
16 |
| others[1] |
1272 |
1 |
|
T5 |
7 |
|
T45 |
19 |
|
T24 |
1 |
| others[2] |
1293 |
1 |
|
T2 |
1 |
|
T5 |
13 |
|
T17 |
1 |
| others[3] |
2108 |
1 |
|
T2 |
1 |
|
T5 |
16 |
|
T37 |
1 |
| false |
653 |
1 |
|
T5 |
6 |
|
T45 |
6 |
|
T18 |
1 |
| true |
407 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
105 |
1 |
|
T31 |
1 |
|
T20 |
3 |
|
T21 |
4 |
| others[1] |
93 |
1 |
|
T20 |
1 |
|
T21 |
4 |
|
T59 |
6 |
| others[2] |
107 |
1 |
|
T24 |
2 |
|
T20 |
3 |
|
T21 |
9 |
| others[3] |
168 |
1 |
|
T17 |
1 |
|
T20 |
4 |
|
T21 |
9 |
| false |
59 |
1 |
|
T20 |
3 |
|
T21 |
2 |
|
T59 |
2 |
| true |
6450 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
240 |
1 |
|
T3 |
1 |
|
T7 |
1 |
|
T31 |
1 |
| others[1] |
248 |
1 |
|
T133 |
1 |
|
T20 |
9 |
|
T21 |
11 |
| others[2] |
225 |
1 |
|
T28 |
1 |
|
T20 |
12 |
|
T21 |
12 |
| others[3] |
385 |
1 |
|
T6 |
1 |
|
T24 |
1 |
|
T36 |
1 |
| false |
128 |
1 |
|
T46 |
1 |
|
T47 |
1 |
|
T20 |
7 |
| true |
5756 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T5 |
47 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1080 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
8 |
| others[1] |
1047 |
1 |
|
T5 |
9 |
|
T28 |
1 |
|
T45 |
19 |
| others[2] |
1103 |
1 |
|
T2 |
1 |
|
T5 |
10 |
|
T45 |
19 |
| others[3] |
1808 |
1 |
|
T5 |
14 |
|
T16 |
1 |
|
T17 |
1 |
| false |
541 |
1 |
|
T1 |
1 |
|
T5 |
6 |
|
T45 |
14 |
| true |
1403 |
1 |
|
T6 |
1 |
|
T29 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
224 |
1 |
|
T20 |
7 |
|
T21 |
9 |
|
T59 |
6 |
| others[1] |
233 |
1 |
|
T20 |
6 |
|
T21 |
9 |
|
T59 |
14 |
| others[2] |
199 |
1 |
|
T20 |
8 |
|
T21 |
9 |
|
T59 |
8 |
| others[3] |
417 |
1 |
|
T17 |
1 |
|
T46 |
1 |
|
T24 |
2 |
| false |
107 |
1 |
|
T20 |
3 |
|
T21 |
2 |
|
T59 |
5 |
| true |
5802 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
215 |
1 |
|
T31 |
1 |
|
T20 |
11 |
|
T21 |
10 |
| others[1] |
207 |
1 |
|
T17 |
1 |
|
T20 |
13 |
|
T21 |
8 |
| others[2] |
221 |
1 |
|
T20 |
7 |
|
T21 |
9 |
|
T59 |
10 |
| others[3] |
372 |
1 |
|
T20 |
17 |
|
T21 |
14 |
|
T41 |
1 |
| false |
120 |
1 |
|
T20 |
4 |
|
T21 |
2 |
|
T59 |
5 |
| true |
5847 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1229 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
6 |
| others[1] |
1271 |
1 |
|
T5 |
14 |
|
T45 |
24 |
|
T20 |
17 |
| others[2] |
1262 |
1 |
|
T5 |
8 |
|
T17 |
1 |
|
T169 |
1 |
| others[3] |
2153 |
1 |
|
T2 |
1 |
|
T5 |
13 |
|
T37 |
1 |
| false |
635 |
1 |
|
T1 |
1 |
|
T5 |
6 |
|
T45 |
8 |
| true |
432 |
1 |
|
T6 |
1 |
|
T7 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1243 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
11 |
| others[1] |
1316 |
1 |
|
T2 |
1 |
|
T5 |
7 |
|
T17 |
1 |
| others[2] |
1279 |
1 |
|
T5 |
8 |
|
T37 |
1 |
|
T189 |
1 |
| others[3] |
2102 |
1 |
|
T5 |
17 |
|
T45 |
30 |
|
T24 |
2 |
| false |
638 |
1 |
|
T5 |
4 |
|
T169 |
1 |
|
T45 |
13 |
| true |
404 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
90 |
1 |
|
T20 |
1 |
|
T21 |
7 |
|
T59 |
2 |
| others[1] |
110 |
1 |
|
T20 |
6 |
|
T21 |
5 |
|
T42 |
1 |
| others[2] |
104 |
1 |
|
T20 |
4 |
|
T21 |
5 |
|
T125 |
1 |
| others[3] |
179 |
1 |
|
T17 |
1 |
|
T31 |
1 |
|
T24 |
2 |
| false |
52 |
1 |
|
T21 |
1 |
|
T59 |
3 |
|
T136 |
2 |
| true |
6447 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
216 |
1 |
|
T20 |
6 |
|
T21 |
4 |
|
T125 |
1 |
| others[1] |
254 |
1 |
|
T24 |
1 |
|
T20 |
16 |
|
T21 |
19 |
| others[2] |
222 |
1 |
|
T20 |
17 |
|
T21 |
7 |
|
T8 |
1 |
| others[3] |
375 |
1 |
|
T46 |
1 |
|
T31 |
1 |
|
T47 |
1 |
| false |
111 |
1 |
|
T36 |
1 |
|
T133 |
1 |
|
T20 |
3 |
| true |
5804 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1160 |
1 |
|
T2 |
1 |
|
T5 |
12 |
|
T189 |
1 |
| others[1] |
1070 |
1 |
|
T5 |
10 |
|
T45 |
22 |
|
T46 |
1 |
| others[2] |
1058 |
1 |
|
T1 |
1 |
|
T5 |
7 |
|
T169 |
1 |
| others[3] |
1811 |
1 |
|
T2 |
1 |
|
T5 |
14 |
|
T7 |
1 |
| false |
563 |
1 |
|
T3 |
1 |
|
T5 |
4 |
|
T12 |
1 |
| true |
1320 |
1 |
|
T6 |
1 |
|
T16 |
1 |
|
T29 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
227 |
1 |
|
T20 |
5 |
|
T21 |
9 |
|
T59 |
14 |
| others[1] |
234 |
1 |
|
T46 |
1 |
|
T24 |
1 |
|
T73 |
1 |
| others[2] |
247 |
1 |
|
T47 |
1 |
|
T20 |
12 |
|
T21 |
7 |
| others[3] |
350 |
1 |
|
T20 |
13 |
|
T21 |
10 |
|
T125 |
1 |
| false |
114 |
1 |
|
T20 |
8 |
|
T21 |
7 |
|
T59 |
3 |
| true |
5810 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
231 |
1 |
|
T17 |
1 |
|
T31 |
1 |
|
T20 |
12 |
| others[1] |
221 |
1 |
|
T20 |
10 |
|
T21 |
12 |
|
T8 |
1 |
| others[2] |
203 |
1 |
|
T20 |
12 |
|
T21 |
4 |
|
T8 |
1 |
| others[3] |
389 |
1 |
|
T29 |
1 |
|
T24 |
1 |
|
T47 |
1 |
| false |
136 |
1 |
|
T24 |
1 |
|
T20 |
6 |
|
T21 |
7 |
| true |
5802 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1278 |
1 |
|
T5 |
16 |
|
T12 |
1 |
|
T45 |
20 |
| others[1] |
1237 |
1 |
|
T5 |
7 |
|
T169 |
1 |
|
T189 |
1 |
| others[2] |
1233 |
1 |
|
T5 |
3 |
|
T45 |
16 |
|
T48 |
1 |
| others[3] |
2121 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T5 |
12 |
| false |
683 |
1 |
|
T5 |
9 |
|
T37 |
1 |
|
T45 |
5 |
| true |
430 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T7 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |