Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.dis.val
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.dis.val
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.ecc_dis
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.ecc_dis
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.scramble_dis
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.scramble_dis
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1301 |
1 |
|
T5 |
11 |
|
T45 |
20 |
|
T18 |
1 |
| others[1] |
1247 |
1 |
|
T5 |
9 |
|
T17 |
1 |
|
T169 |
1 |
| others[2] |
1264 |
1 |
|
T2 |
1 |
|
T5 |
10 |
|
T37 |
1 |
| others[3] |
2064 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
14 |
| false |
690 |
1 |
|
T5 |
3 |
|
T45 |
9 |
|
T20 |
11 |
| true |
416 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
90 |
1 |
|
T31 |
1 |
|
T24 |
1 |
|
T20 |
2 |
| others[1] |
113 |
1 |
|
T20 |
4 |
|
T21 |
2 |
|
T59 |
5 |
| others[2] |
93 |
1 |
|
T24 |
1 |
|
T20 |
4 |
|
T21 |
2 |
| others[3] |
183 |
1 |
|
T20 |
8 |
|
T21 |
6 |
|
T125 |
1 |
| false |
49 |
1 |
|
T17 |
1 |
|
T20 |
2 |
|
T21 |
2 |
| true |
6454 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
200 |
1 |
|
T73 |
1 |
|
T111 |
1 |
|
T20 |
6 |
| others[1] |
229 |
1 |
|
T29 |
1 |
|
T31 |
1 |
|
T24 |
1 |
| others[2] |
231 |
1 |
|
T6 |
1 |
|
T20 |
13 |
|
T21 |
10 |
| others[3] |
404 |
1 |
|
T7 |
1 |
|
T133 |
1 |
|
T20 |
10 |
| false |
137 |
1 |
|
T20 |
8 |
|
T21 |
6 |
|
T134 |
1 |
| true |
5781 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1047 |
1 |
|
T5 |
9 |
|
T45 |
20 |
|
T36 |
1 |
| others[1] |
1093 |
1 |
|
T5 |
10 |
|
T6 |
1 |
|
T12 |
1 |
| others[2] |
1064 |
1 |
|
T2 |
1 |
|
T5 |
6 |
|
T37 |
1 |
| others[3] |
1826 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
18 |
| false |
548 |
1 |
|
T5 |
4 |
|
T7 |
1 |
|
T169 |
1 |
| true |
1404 |
1 |
|
T3 |
1 |
|
T16 |
1 |
|
T29 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
225 |
1 |
|
T20 |
10 |
|
T21 |
13 |
|
T59 |
10 |
| others[1] |
233 |
1 |
|
T31 |
1 |
|
T20 |
8 |
|
T21 |
11 |
| others[2] |
216 |
1 |
|
T17 |
1 |
|
T20 |
10 |
|
T21 |
10 |
| others[3] |
377 |
1 |
|
T29 |
1 |
|
T133 |
1 |
|
T20 |
10 |
| false |
110 |
1 |
|
T7 |
1 |
|
T20 |
5 |
|
T21 |
1 |
| true |
5821 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
243 |
1 |
|
T20 |
11 |
|
T21 |
13 |
|
T42 |
1 |
| others[1] |
217 |
1 |
|
T20 |
10 |
|
T21 |
7 |
|
T8 |
1 |
| others[2] |
210 |
1 |
|
T7 |
1 |
|
T20 |
11 |
|
T21 |
7 |
| others[3] |
417 |
1 |
|
T20 |
18 |
|
T21 |
26 |
|
T59 |
17 |
| false |
94 |
1 |
|
T20 |
8 |
|
T21 |
1 |
|
T8 |
2 |
| true |
5801 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1251 |
1 |
|
T5 |
12 |
|
T45 |
18 |
|
T31 |
1 |
| others[1] |
1238 |
1 |
|
T5 |
10 |
|
T189 |
1 |
|
T45 |
15 |
| others[2] |
1297 |
1 |
|
T2 |
1 |
|
T5 |
6 |
|
T17 |
1 |
| others[3] |
2108 |
1 |
|
T1 |
1 |
|
T5 |
16 |
|
T45 |
35 |
| false |
647 |
1 |
|
T2 |
1 |
|
T5 |
3 |
|
T37 |
1 |
| true |
441 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1246 |
1 |
|
T2 |
2 |
|
T5 |
9 |
|
T169 |
1 |
| others[1] |
1215 |
1 |
|
T5 |
11 |
|
T45 |
16 |
|
T46 |
1 |
| others[2] |
1301 |
1 |
|
T5 |
8 |
|
T17 |
1 |
|
T45 |
17 |
| others[3] |
2106 |
1 |
|
T1 |
1 |
|
T5 |
12 |
|
T37 |
1 |
| false |
693 |
1 |
|
T5 |
7 |
|
T45 |
9 |
|
T24 |
1 |
| true |
421 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
107 |
1 |
|
T20 |
3 |
|
T21 |
1 |
|
T42 |
1 |
| others[1] |
117 |
1 |
|
T24 |
1 |
|
T20 |
2 |
|
T21 |
3 |
| others[2] |
103 |
1 |
|
T31 |
1 |
|
T20 |
1 |
|
T21 |
2 |
| others[3] |
158 |
1 |
|
T17 |
1 |
|
T24 |
1 |
|
T20 |
6 |
| false |
66 |
1 |
|
T20 |
4 |
|
T21 |
4 |
|
T59 |
2 |
| true |
6431 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
234 |
1 |
|
T28 |
1 |
|
T73 |
1 |
|
T20 |
12 |
| others[1] |
234 |
1 |
|
T20 |
9 |
|
T21 |
7 |
|
T59 |
8 |
| others[2] |
244 |
1 |
|
T24 |
1 |
|
T20 |
8 |
|
T21 |
13 |
| others[3] |
397 |
1 |
|
T111 |
1 |
|
T20 |
11 |
|
T21 |
22 |
| false |
120 |
1 |
|
T17 |
1 |
|
T133 |
1 |
|
T20 |
4 |
| true |
5753 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1090 |
1 |
|
T5 |
10 |
|
T45 |
30 |
|
T47 |
1 |
| others[1] |
1136 |
1 |
|
T2 |
1 |
|
T5 |
8 |
|
T12 |
1 |
| others[2] |
1077 |
1 |
|
T5 |
9 |
|
T7 |
1 |
|
T29 |
1 |
| others[3] |
1773 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
17 |
| false |
562 |
1 |
|
T5 |
3 |
|
T17 |
1 |
|
T45 |
6 |
| true |
1344 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T28 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
244 |
1 |
|
T31 |
1 |
|
T20 |
8 |
|
T21 |
12 |
| others[1] |
230 |
1 |
|
T24 |
1 |
|
T20 |
15 |
|
T21 |
10 |
| others[2] |
235 |
1 |
|
T20 |
12 |
|
T21 |
5 |
|
T41 |
1 |
| others[3] |
369 |
1 |
|
T73 |
1 |
|
T133 |
1 |
|
T20 |
11 |
| false |
137 |
1 |
|
T24 |
1 |
|
T20 |
5 |
|
T21 |
4 |
| true |
5767 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
220 |
1 |
|
T20 |
7 |
|
T21 |
9 |
|
T59 |
11 |
| others[1] |
228 |
1 |
|
T20 |
7 |
|
T21 |
5 |
|
T8 |
2 |
| others[2] |
236 |
1 |
|
T24 |
1 |
|
T20 |
10 |
|
T21 |
7 |
| others[3] |
347 |
1 |
|
T17 |
1 |
|
T29 |
1 |
|
T20 |
12 |
| false |
104 |
1 |
|
T20 |
6 |
|
T21 |
4 |
|
T59 |
2 |
| true |
5847 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1291 |
1 |
|
T2 |
1 |
|
T5 |
13 |
|
T45 |
21 |
| others[1] |
1222 |
1 |
|
T5 |
9 |
|
T45 |
15 |
|
T24 |
1 |
| others[2] |
1263 |
1 |
|
T1 |
1 |
|
T5 |
9 |
|
T17 |
1 |
| others[3] |
2112 |
1 |
|
T5 |
14 |
|
T37 |
1 |
|
T169 |
1 |
| false |
663 |
1 |
|
T2 |
1 |
|
T5 |
2 |
|
T45 |
7 |
| true |
431 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1273 |
1 |
|
T5 |
10 |
|
T45 |
17 |
|
T194 |
1 |
| others[1] |
1257 |
1 |
|
T2 |
1 |
|
T5 |
9 |
|
T45 |
24 |
| others[2] |
1248 |
1 |
|
T1 |
1 |
|
T5 |
10 |
|
T169 |
1 |
| others[3] |
2122 |
1 |
|
T2 |
1 |
|
T5 |
16 |
|
T17 |
1 |
| false |
656 |
1 |
|
T5 |
2 |
|
T45 |
8 |
|
T24 |
1 |
| true |
426 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
100 |
1 |
|
T17 |
1 |
|
T31 |
1 |
|
T20 |
1 |
| others[1] |
107 |
1 |
|
T7 |
1 |
|
T24 |
1 |
|
T20 |
4 |
| others[2] |
101 |
1 |
|
T20 |
6 |
|
T21 |
3 |
|
T59 |
6 |
| others[3] |
165 |
1 |
|
T24 |
1 |
|
T20 |
8 |
|
T21 |
3 |
| false |
72 |
1 |
|
T20 |
2 |
|
T21 |
4 |
|
T59 |
2 |
| true |
6437 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
231 |
1 |
|
T28 |
1 |
|
T20 |
12 |
|
T21 |
12 |
| others[1] |
216 |
1 |
|
T46 |
1 |
|
T20 |
12 |
|
T21 |
13 |
| others[2] |
226 |
1 |
|
T31 |
1 |
|
T20 |
5 |
|
T21 |
10 |
| others[3] |
382 |
1 |
|
T133 |
1 |
|
T111 |
1 |
|
T20 |
16 |
| false |
117 |
1 |
|
T20 |
4 |
|
T21 |
6 |
|
T59 |
4 |
| true |
5810 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1041 |
1 |
|
T1 |
1 |
|
T5 |
5 |
|
T169 |
1 |
| others[1] |
1099 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
8 |
| others[2] |
1111 |
1 |
|
T2 |
1 |
|
T5 |
17 |
|
T189 |
1 |
| others[3] |
1784 |
1 |
|
T5 |
11 |
|
T37 |
1 |
|
T28 |
1 |
| false |
564 |
1 |
|
T5 |
6 |
|
T7 |
1 |
|
T17 |
1 |
| true |
1383 |
1 |
|
T6 |
1 |
|
T16 |
1 |
|
T29 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
216 |
1 |
|
T20 |
9 |
|
T21 |
9 |
|
T125 |
1 |
| others[1] |
232 |
1 |
|
T24 |
1 |
|
T133 |
1 |
|
T20 |
5 |
| others[2] |
248 |
1 |
|
T20 |
11 |
|
T21 |
12 |
|
T59 |
6 |
| others[3] |
382 |
1 |
|
T29 |
1 |
|
T24 |
1 |
|
T73 |
1 |
| false |
103 |
1 |
|
T20 |
2 |
|
T21 |
3 |
|
T59 |
5 |
| true |
5801 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
234 |
1 |
|
T31 |
1 |
|
T20 |
5 |
|
T21 |
11 |
| others[1] |
214 |
1 |
|
T17 |
1 |
|
T47 |
1 |
|
T20 |
9 |
| others[2] |
228 |
1 |
|
T24 |
1 |
|
T20 |
15 |
|
T21 |
14 |
| others[3] |
395 |
1 |
|
T20 |
16 |
|
T21 |
19 |
|
T125 |
1 |
| false |
112 |
1 |
|
T20 |
9 |
|
T21 |
2 |
|
T59 |
1 |
| true |
5799 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1241 |
1 |
|
T5 |
8 |
|
T17 |
1 |
|
T45 |
17 |
| others[1] |
1179 |
1 |
|
T1 |
1 |
|
T5 |
15 |
|
T16 |
1 |
| others[2] |
1295 |
1 |
|
T5 |
9 |
|
T169 |
1 |
|
T45 |
19 |
| others[3] |
2140 |
1 |
|
T2 |
2 |
|
T5 |
12 |
|
T6 |
1 |
| false |
698 |
1 |
|
T5 |
3 |
|
T189 |
1 |
|
T45 |
8 |
| true |
429 |
1 |
|
T3 |
1 |
|
T7 |
1 |
|
T29 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1275 |
1 |
|
T5 |
12 |
|
T37 |
1 |
|
T45 |
15 |
| others[1] |
1248 |
1 |
|
T5 |
11 |
|
T45 |
18 |
|
T18 |
1 |
| others[2] |
1214 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
9 |
| others[3] |
2142 |
1 |
|
T1 |
1 |
|
T5 |
10 |
|
T17 |
1 |
| false |
688 |
1 |
|
T2 |
1 |
|
T5 |
5 |
|
T45 |
10 |
| true |
415 |
1 |
|
T6 |
1 |
|
T7 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
100 |
1 |
|
T17 |
1 |
|
T20 |
1 |
|
T21 |
6 |
| others[1] |
108 |
1 |
|
T20 |
2 |
|
T21 |
6 |
|
T59 |
6 |
| others[2] |
108 |
1 |
|
T31 |
1 |
|
T24 |
1 |
|
T20 |
8 |
| others[3] |
174 |
1 |
|
T24 |
1 |
|
T47 |
1 |
|
T20 |
7 |
| false |
47 |
1 |
|
T20 |
3 |
|
T21 |
1 |
|
T136 |
1 |
| true |
6445 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
243 |
1 |
|
T7 |
1 |
|
T31 |
1 |
|
T20 |
13 |
| others[1] |
247 |
1 |
|
T20 |
9 |
|
T21 |
8 |
|
T8 |
1 |
| others[2] |
230 |
1 |
|
T3 |
1 |
|
T29 |
1 |
|
T36 |
1 |
| others[3] |
389 |
1 |
|
T17 |
1 |
|
T20 |
13 |
|
T21 |
11 |
| false |
118 |
1 |
|
T28 |
1 |
|
T73 |
1 |
|
T20 |
5 |
| true |
5755 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T5 |
47 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1089 |
1 |
|
T2 |
1 |
|
T5 |
10 |
|
T37 |
1 |
| others[1] |
1029 |
1 |
|
T5 |
9 |
|
T7 |
1 |
|
T189 |
1 |
| others[2] |
1114 |
1 |
|
T5 |
8 |
|
T17 |
1 |
|
T169 |
1 |
| others[3] |
1880 |
1 |
|
T1 |
1 |
|
T5 |
14 |
|
T45 |
32 |
| false |
566 |
1 |
|
T2 |
1 |
|
T5 |
6 |
|
T45 |
16 |
| true |
1304 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
246 |
1 |
|
T46 |
1 |
|
T47 |
1 |
|
T20 |
11 |
| others[1] |
252 |
1 |
|
T20 |
6 |
|
T21 |
12 |
|
T125 |
1 |
| others[2] |
229 |
1 |
|
T7 |
1 |
|
T133 |
1 |
|
T20 |
11 |
| others[3] |
356 |
1 |
|
T24 |
2 |
|
T73 |
1 |
|
T20 |
13 |
| false |
122 |
1 |
|
T20 |
6 |
|
T21 |
6 |
|
T59 |
4 |
| true |
5777 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
221 |
1 |
|
T20 |
8 |
|
T21 |
10 |
|
T8 |
2 |
| others[1] |
181 |
1 |
|
T17 |
1 |
|
T20 |
6 |
|
T21 |
8 |
| others[2] |
227 |
1 |
|
T31 |
1 |
|
T24 |
1 |
|
T20 |
12 |
| others[3] |
363 |
1 |
|
T29 |
1 |
|
T24 |
1 |
|
T47 |
1 |
| false |
109 |
1 |
|
T20 |
4 |
|
T21 |
1 |
|
T59 |
7 |
| true |
5881 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1262 |
1 |
|
T5 |
8 |
|
T189 |
1 |
|
T45 |
21 |
| others[1] |
1308 |
1 |
|
T5 |
8 |
|
T17 |
1 |
|
T37 |
1 |
| others[2] |
1231 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
6 |
| others[3] |
2111 |
1 |
|
T5 |
17 |
|
T45 |
28 |
|
T31 |
1 |
| false |
641 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
8 |
| true |
429 |
1 |
|
T6 |
1 |
|
T7 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
5 |
1 |
|
T367 |
1 |
|
T368 |
1 |
|
T369 |
1 |
| others[1] |
12 |
1 |
|
T13 |
1 |
|
T106 |
1 |
|
T170 |
1 |
| others[2] |
9 |
1 |
|
T60 |
1 |
|
T102 |
1 |
|
T166 |
1 |
| others[3] |
16 |
1 |
|
T122 |
1 |
|
T148 |
1 |
|
T153 |
1 |
| false |
7 |
1 |
|
T16 |
1 |
|
T317 |
1 |
|
T370 |
1 |
| true |
42 |
1 |
|
T157 |
1 |
|
T148 |
2 |
|
T152 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
3 |
1 |
|
T294 |
1 |
|
T371 |
1 |
|
T372 |
1 |
| others[1] |
1 |
1 |
|
T4 |
1 |
|
- |
- |
|
- |
- |
| others[2] |
4 |
1 |
|
T320 |
1 |
|
T373 |
1 |
|
T374 |
1 |
| others[3] |
4 |
1 |
|
T375 |
1 |
|
T376 |
1 |
|
T377 |
1 |
| false |
11 |
1 |
|
T75 |
1 |
|
T183 |
1 |
|
T378 |
1 |
| true |
25 |
1 |
|
T74 |
1 |
|
T379 |
1 |
|
T380 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
5 |
1 |
|
T381 |
1 |
|
T375 |
1 |
|
T382 |
1 |
| others[1] |
1 |
1 |
|
T383 |
1 |
|
- |
- |
|
- |
- |
| others[2] |
3 |
1 |
|
T384 |
1 |
|
T385 |
1 |
|
T377 |
1 |
| others[3] |
7 |
1 |
|
T320 |
1 |
|
T380 |
1 |
|
T386 |
1 |
| false |
5 |
1 |
|
T387 |
1 |
|
T388 |
1 |
|
T389 |
1 |
| true |
27 |
1 |
|
T4 |
1 |
|
T74 |
1 |
|
T75 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |