Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10933 |
1 |
|
T5 |
10 |
|
T22 |
202 |
|
T45 |
16 |
| others[1] |
824 |
1 |
|
T5 |
8 |
|
T189 |
1 |
|
T45 |
17 |
| others[2] |
845 |
1 |
|
T5 |
8 |
|
T17 |
1 |
|
T12 |
1 |
| others[3] |
1372 |
1 |
|
T5 |
21 |
|
T37 |
1 |
|
T45 |
25 |
| false |
393 |
1 |
|
T1 |
1 |
|
T29 |
1 |
|
T45 |
12 |
| true |
510 |
1 |
|
T2 |
2 |
|
T3 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2539 |
1 |
|
T2 |
1 |
|
T5 |
14 |
|
T22 |
52 |
| others[1] |
2598 |
1 |
|
T5 |
6 |
|
T22 |
40 |
|
T37 |
1 |
| others[2] |
2522 |
1 |
|
T1 |
1 |
|
T5 |
10 |
|
T7 |
1 |
| others[3] |
4202 |
1 |
|
T2 |
1 |
|
T5 |
12 |
|
T22 |
61 |
| false |
1369 |
1 |
|
T5 |
5 |
|
T22 |
17 |
|
T45 |
14 |
| true |
1647 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10351 |
1 |
|
T22 |
202 |
|
T40 |
1 |
|
T26 |
2 |
| others[1] |
278 |
1 |
|
T17 |
1 |
|
T29 |
1 |
|
T24 |
1 |
| others[2] |
282 |
1 |
|
T20 |
8 |
|
T21 |
5 |
|
T41 |
1 |
| others[3] |
486 |
1 |
|
T40 |
3 |
|
T73 |
1 |
|
T20 |
15 |
| false |
143 |
1 |
|
T169 |
1 |
|
T40 |
1 |
|
T20 |
7 |
| true |
3337 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10611 |
1 |
|
T2 |
1 |
|
T5 |
4 |
|
T22 |
202 |
| others[1] |
512 |
1 |
|
T5 |
7 |
|
T17 |
1 |
|
T45 |
8 |
| others[2] |
464 |
1 |
|
T5 |
7 |
|
T29 |
1 |
|
T45 |
10 |
| others[3] |
739 |
1 |
|
T2 |
1 |
|
T5 |
3 |
|
T6 |
1 |
| false |
227 |
1 |
|
T5 |
3 |
|
T45 |
5 |
|
T105 |
1 |
| true |
2324 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T5 |
23 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10322 |
1 |
|
T2 |
1 |
|
T22 |
202 |
|
T24 |
1 |
| others[1] |
282 |
1 |
|
T29 |
1 |
|
T20 |
13 |
|
T21 |
10 |
| others[2] |
252 |
1 |
|
T175 |
1 |
|
T20 |
6 |
|
T21 |
10 |
| others[3] |
447 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T189 |
1 |
| false |
142 |
1 |
|
T17 |
1 |
|
T20 |
6 |
|
T21 |
7 |
| true |
3432 |
1 |
|
T3 |
1 |
|
T5 |
47 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10340 |
1 |
|
T22 |
202 |
|
T24 |
2 |
|
T26 |
2 |
| others[1] |
258 |
1 |
|
T18 |
1 |
|
T20 |
13 |
|
T21 |
10 |
| others[2] |
265 |
1 |
|
T20 |
7 |
|
T21 |
9 |
|
T8 |
1 |
| others[3] |
444 |
1 |
|
T2 |
1 |
|
T29 |
1 |
|
T37 |
1 |
| false |
139 |
1 |
|
T20 |
7 |
|
T21 |
5 |
|
T59 |
7 |
| true |
3431 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10971 |
1 |
|
T1 |
1 |
|
T5 |
11 |
|
T22 |
202 |
| others[1] |
804 |
1 |
|
T2 |
1 |
|
T5 |
9 |
|
T28 |
1 |
| others[2] |
834 |
1 |
|
T5 |
9 |
|
T37 |
1 |
|
T45 |
23 |
| others[3] |
1369 |
1 |
|
T5 |
14 |
|
T17 |
1 |
|
T169 |
1 |
| false |
416 |
1 |
|
T2 |
1 |
|
T5 |
4 |
|
T45 |
6 |
| true |
483 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10921 |
1 |
|
T5 |
6 |
|
T22 |
202 |
|
T45 |
12 |
| others[1] |
785 |
1 |
|
T5 |
6 |
|
T189 |
1 |
|
T45 |
16 |
| others[2] |
815 |
1 |
|
T5 |
12 |
|
T28 |
1 |
|
T45 |
21 |
| others[3] |
1383 |
1 |
|
T1 |
1 |
|
T5 |
18 |
|
T17 |
1 |
| false |
390 |
1 |
|
T2 |
1 |
|
T5 |
5 |
|
T45 |
13 |
| true |
527 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2503 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
12 |
| others[1] |
2626 |
1 |
|
T5 |
6 |
|
T22 |
52 |
|
T45 |
20 |
| others[2] |
2598 |
1 |
|
T5 |
11 |
|
T22 |
42 |
|
T37 |
1 |
| others[3] |
4248 |
1 |
|
T5 |
13 |
|
T17 |
1 |
|
T22 |
63 |
| false |
1323 |
1 |
|
T2 |
1 |
|
T5 |
5 |
|
T22 |
14 |
| true |
1523 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10369 |
1 |
|
T7 |
1 |
|
T22 |
202 |
|
T189 |
1 |
| others[1] |
265 |
1 |
|
T2 |
1 |
|
T17 |
1 |
|
T20 |
8 |
| others[2] |
306 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T40 |
1 |
| others[3] |
434 |
1 |
|
T194 |
1 |
|
T175 |
1 |
|
T20 |
17 |
| false |
159 |
1 |
|
T24 |
1 |
|
T40 |
1 |
|
T58 |
1 |
| true |
3288 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
47 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10561 |
1 |
|
T2 |
1 |
|
T5 |
4 |
|
T22 |
202 |
| others[1] |
467 |
1 |
|
T1 |
1 |
|
T5 |
2 |
|
T45 |
10 |
| others[2] |
481 |
1 |
|
T5 |
7 |
|
T29 |
1 |
|
T169 |
1 |
| others[3] |
803 |
1 |
|
T2 |
1 |
|
T5 |
7 |
|
T16 |
1 |
| false |
230 |
1 |
|
T5 |
1 |
|
T17 |
1 |
|
T45 |
6 |
| true |
2279 |
1 |
|
T3 |
1 |
|
T5 |
26 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10347 |
1 |
|
T2 |
1 |
|
T22 |
202 |
|
T47 |
1 |
| others[1] |
274 |
1 |
|
T7 |
1 |
|
T24 |
1 |
|
T73 |
1 |
| others[2] |
244 |
1 |
|
T133 |
1 |
|
T20 |
9 |
|
T21 |
11 |
| others[3] |
436 |
1 |
|
T37 |
1 |
|
T31 |
1 |
|
T48 |
1 |
| false |
127 |
1 |
|
T20 |
4 |
|
T21 |
5 |
|
T59 |
2 |
| true |
3393 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10309 |
1 |
|
T22 |
202 |
|
T37 |
1 |
|
T24 |
1 |
| others[1] |
263 |
1 |
|
T2 |
2 |
|
T17 |
1 |
|
T169 |
1 |
| others[2] |
255 |
1 |
|
T7 |
1 |
|
T31 |
1 |
|
T24 |
1 |
| others[3] |
427 |
1 |
|
T175 |
1 |
|
T20 |
17 |
|
T21 |
15 |
| false |
128 |
1 |
|
T20 |
5 |
|
T21 |
4 |
|
T59 |
6 |
| true |
3439 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T5 |
47 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10917 |
1 |
|
T5 |
5 |
|
T22 |
202 |
|
T169 |
1 |
| others[1] |
817 |
1 |
|
T5 |
12 |
|
T17 |
1 |
|
T45 |
11 |
| others[2] |
839 |
1 |
|
T1 |
1 |
|
T5 |
8 |
|
T6 |
1 |
| others[3] |
1355 |
1 |
|
T2 |
1 |
|
T5 |
16 |
|
T37 |
1 |
| false |
404 |
1 |
|
T5 |
6 |
|
T45 |
4 |
|
T40 |
2 |
| true |
489 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10963 |
1 |
|
T5 |
9 |
|
T22 |
202 |
|
T45 |
24 |
| others[1] |
812 |
1 |
|
T1 |
1 |
|
T5 |
7 |
|
T6 |
1 |
| others[2] |
801 |
1 |
|
T2 |
1 |
|
T5 |
8 |
|
T169 |
1 |
| others[3] |
1309 |
1 |
|
T5 |
16 |
|
T37 |
1 |
|
T189 |
1 |
| false |
417 |
1 |
|
T5 |
7 |
|
T45 |
11 |
|
T20 |
9 |
| true |
519 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2550 |
1 |
|
T5 |
12 |
|
T22 |
36 |
|
T37 |
1 |
| others[1] |
2516 |
1 |
|
T2 |
1 |
|
T5 |
6 |
|
T22 |
29 |
| others[2] |
2615 |
1 |
|
T2 |
1 |
|
T5 |
12 |
|
T7 |
1 |
| others[3] |
4199 |
1 |
|
T5 |
11 |
|
T17 |
1 |
|
T22 |
71 |
| false |
1398 |
1 |
|
T1 |
1 |
|
T5 |
6 |
|
T22 |
20 |
| true |
1543 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10353 |
1 |
|
T22 |
202 |
|
T40 |
2 |
|
T48 |
1 |
| others[1] |
289 |
1 |
|
T46 |
1 |
|
T194 |
1 |
|
T40 |
1 |
| others[2] |
299 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T17 |
1 |
| others[3] |
441 |
1 |
|
T169 |
1 |
|
T40 |
1 |
|
T175 |
1 |
| false |
145 |
1 |
|
T47 |
1 |
|
T111 |
1 |
|
T20 |
6 |
| true |
3294 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
47 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10538 |
1 |
|
T5 |
6 |
|
T22 |
202 |
|
T45 |
7 |
| others[1] |
461 |
1 |
|
T3 |
1 |
|
T5 |
2 |
|
T37 |
1 |
| others[2] |
462 |
1 |
|
T5 |
10 |
|
T7 |
1 |
|
T45 |
9 |
| others[3] |
868 |
1 |
|
T5 |
5 |
|
T17 |
1 |
|
T29 |
1 |
| false |
249 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T5 |
3 |
| true |
2243 |
1 |
|
T5 |
21 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10363 |
1 |
|
T2 |
1 |
|
T22 |
202 |
|
T189 |
1 |
| others[1] |
217 |
1 |
|
T17 |
1 |
|
T29 |
1 |
|
T37 |
1 |
| others[2] |
299 |
1 |
|
T7 |
1 |
|
T169 |
1 |
|
T47 |
1 |
| others[3] |
413 |
1 |
|
T48 |
1 |
|
T73 |
1 |
|
T20 |
9 |
| false |
148 |
1 |
|
T20 |
3 |
|
T21 |
4 |
|
T59 |
6 |
| true |
3381 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10318 |
1 |
|
T1 |
1 |
|
T22 |
202 |
|
T18 |
1 |
| others[1] |
251 |
1 |
|
T2 |
1 |
|
T175 |
1 |
|
T20 |
8 |
| others[2] |
281 |
1 |
|
T31 |
1 |
|
T20 |
14 |
|
T21 |
7 |
| others[3] |
406 |
1 |
|
T2 |
1 |
|
T37 |
1 |
|
T169 |
1 |
| false |
138 |
1 |
|
T20 |
7 |
|
T21 |
4 |
|
T8 |
1 |
| true |
3427 |
1 |
|
T3 |
1 |
|
T5 |
47 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10890 |
1 |
|
T5 |
12 |
|
T22 |
202 |
|
T45 |
16 |
| others[1] |
788 |
1 |
|
T5 |
8 |
|
T37 |
1 |
|
T189 |
1 |
| others[2] |
786 |
1 |
|
T5 |
8 |
|
T45 |
19 |
|
T24 |
1 |
| others[3] |
1398 |
1 |
|
T1 |
1 |
|
T5 |
17 |
|
T17 |
1 |
| false |
461 |
1 |
|
T2 |
1 |
|
T5 |
2 |
|
T45 |
12 |
| true |
498 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10907 |
1 |
|
T2 |
1 |
|
T5 |
11 |
|
T22 |
202 |
| others[1] |
809 |
1 |
|
T2 |
1 |
|
T5 |
8 |
|
T37 |
1 |
| others[2] |
816 |
1 |
|
T5 |
9 |
|
T17 |
1 |
|
T28 |
1 |
| others[3] |
1365 |
1 |
|
T1 |
1 |
|
T5 |
15 |
|
T169 |
1 |
| false |
412 |
1 |
|
T5 |
4 |
|
T45 |
10 |
|
T20 |
9 |
| true |
512 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2543 |
1 |
|
T5 |
12 |
|
T22 |
43 |
|
T45 |
16 |
| others[1] |
2531 |
1 |
|
T5 |
9 |
|
T17 |
1 |
|
T22 |
40 |
| others[2] |
2569 |
1 |
|
T5 |
8 |
|
T22 |
48 |
|
T169 |
1 |
| others[3] |
4350 |
1 |
|
T2 |
2 |
|
T5 |
13 |
|
T22 |
56 |
| false |
1266 |
1 |
|
T1 |
1 |
|
T5 |
5 |
|
T22 |
15 |
| true |
1562 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10369 |
1 |
|
T7 |
1 |
|
T22 |
202 |
|
T40 |
1 |
| others[1] |
266 |
1 |
|
T3 |
1 |
|
T46 |
1 |
|
T194 |
1 |
| others[2] |
293 |
1 |
|
T2 |
1 |
|
T37 |
1 |
|
T28 |
1 |
| others[3] |
443 |
1 |
|
T17 |
1 |
|
T169 |
1 |
|
T20 |
19 |
| false |
148 |
1 |
|
T47 |
1 |
|
T20 |
5 |
|
T21 |
5 |
| true |
3302 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
47 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10533 |
1 |
|
T5 |
6 |
|
T22 |
202 |
|
T37 |
1 |
| others[1] |
480 |
1 |
|
T5 |
1 |
|
T17 |
1 |
|
T45 |
7 |
| others[2] |
484 |
1 |
|
T2 |
1 |
|
T5 |
5 |
|
T169 |
1 |
| others[3] |
807 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T5 |
8 |
| false |
251 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T12 |
1 |
| true |
2266 |
1 |
|
T5 |
26 |
|
T16 |
1 |
|
T29 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10310 |
1 |
|
T2 |
1 |
|
T17 |
1 |
|
T22 |
202 |
| others[1] |
269 |
1 |
|
T20 |
5 |
|
T21 |
8 |
|
T59 |
16 |
| others[2] |
276 |
1 |
|
T24 |
1 |
|
T47 |
1 |
|
T58 |
1 |
| others[3] |
430 |
1 |
|
T1 |
1 |
|
T29 |
1 |
|
T18 |
1 |
| false |
133 |
1 |
|
T169 |
1 |
|
T31 |
1 |
|
T20 |
7 |
| true |
3403 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
47 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10330 |
1 |
|
T1 |
1 |
|
T22 |
202 |
|
T26 |
2 |
| others[1] |
239 |
1 |
|
T17 |
1 |
|
T37 |
1 |
|
T58 |
1 |
| others[2] |
239 |
1 |
|
T2 |
1 |
|
T20 |
9 |
|
T21 |
4 |
| others[3] |
442 |
1 |
|
T2 |
1 |
|
T7 |
1 |
|
T29 |
1 |
| false |
130 |
1 |
|
T169 |
1 |
|
T189 |
1 |
|
T20 |
7 |
| true |
3441 |
1 |
|
T3 |
1 |
|
T5 |
47 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10917 |
1 |
|
T1 |
1 |
|
T5 |
7 |
|
T22 |
202 |
| others[1] |
822 |
1 |
|
T5 |
5 |
|
T45 |
23 |
|
T40 |
1 |
| others[2] |
798 |
1 |
|
T5 |
7 |
|
T45 |
11 |
|
T40 |
3 |
| others[3] |
1352 |
1 |
|
T5 |
21 |
|
T189 |
1 |
|
T45 |
36 |
| false |
441 |
1 |
|
T5 |
7 |
|
T45 |
7 |
|
T40 |
1 |
| true |
491 |
1 |
|
T2 |
2 |
|
T3 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10895 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
13 |
| others[1] |
788 |
1 |
|
T5 |
6 |
|
T45 |
15 |
|
T40 |
2 |
| others[2] |
807 |
1 |
|
T5 |
7 |
|
T169 |
1 |
|
T45 |
16 |
| others[3] |
1412 |
1 |
|
T5 |
16 |
|
T37 |
1 |
|
T189 |
1 |
| false |
409 |
1 |
|
T3 |
1 |
|
T5 |
5 |
|
T45 |
9 |
| true |
510 |
1 |
|
T2 |
1 |
|
T6 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2594 |
1 |
|
T5 |
9 |
|
T22 |
34 |
|
T169 |
1 |
| others[1] |
2586 |
1 |
|
T2 |
1 |
|
T5 |
12 |
|
T7 |
1 |
| others[2] |
2497 |
1 |
|
T5 |
10 |
|
T22 |
37 |
|
T45 |
21 |
| others[3] |
4276 |
1 |
|
T2 |
1 |
|
T5 |
10 |
|
T17 |
1 |
| false |
1298 |
1 |
|
T1 |
1 |
|
T5 |
6 |
|
T22 |
23 |
| true |
1570 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10362 |
1 |
|
T22 |
202 |
|
T26 |
2 |
|
T27 |
2 |
| others[1] |
266 |
1 |
|
T29 |
1 |
|
T37 |
1 |
|
T189 |
1 |
| others[2] |
247 |
1 |
|
T40 |
1 |
|
T36 |
1 |
|
T20 |
5 |
| others[3] |
461 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T73 |
1 |
| false |
137 |
1 |
|
T169 |
1 |
|
T40 |
3 |
|
T58 |
1 |
| true |
3348 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
47 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |