Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10571 |
1 |
|
T5 |
3 |
|
T17 |
1 |
|
T22 |
202 |
| others[1] |
516 |
1 |
|
T2 |
1 |
|
T5 |
5 |
|
T45 |
8 |
| others[2] |
465 |
1 |
|
T5 |
3 |
|
T6 |
1 |
|
T16 |
1 |
| others[3] |
758 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
11 |
| false |
234 |
1 |
|
T5 |
1 |
|
T28 |
1 |
|
T45 |
3 |
| true |
2277 |
1 |
|
T1 |
1 |
|
T5 |
24 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10319 |
1 |
|
T17 |
1 |
|
T22 |
202 |
|
T194 |
1 |
| others[1] |
243 |
1 |
|
T20 |
8 |
|
T21 |
11 |
|
T120 |
1 |
| others[2] |
267 |
1 |
|
T1 |
1 |
|
T175 |
1 |
|
T20 |
13 |
| others[3] |
461 |
1 |
|
T189 |
1 |
|
T20 |
20 |
|
T21 |
18 |
| false |
132 |
1 |
|
T29 |
1 |
|
T20 |
2 |
|
T21 |
6 |
| true |
3399 |
1 |
|
T2 |
2 |
|
T3 |
1 |
|
T5 |
47 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10334 |
1 |
|
T22 |
202 |
|
T194 |
1 |
|
T24 |
1 |
| others[1] |
229 |
1 |
|
T17 |
1 |
|
T20 |
9 |
|
T21 |
4 |
| others[2] |
266 |
1 |
|
T18 |
1 |
|
T20 |
5 |
|
T21 |
9 |
| others[3] |
484 |
1 |
|
T2 |
1 |
|
T29 |
1 |
|
T31 |
1 |
| false |
143 |
1 |
|
T20 |
6 |
|
T21 |
16 |
|
T25 |
1 |
| true |
3365 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10921 |
1 |
|
T1 |
1 |
|
T5 |
9 |
|
T22 |
202 |
| others[1] |
781 |
1 |
|
T5 |
6 |
|
T189 |
1 |
|
T45 |
24 |
| others[2] |
832 |
1 |
|
T2 |
1 |
|
T5 |
13 |
|
T45 |
17 |
| others[3] |
1358 |
1 |
|
T5 |
17 |
|
T17 |
1 |
|
T37 |
1 |
| false |
441 |
1 |
|
T2 |
1 |
|
T5 |
2 |
|
T45 |
8 |
| true |
488 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10896 |
1 |
|
T1 |
1 |
|
T5 |
10 |
|
T17 |
1 |
| others[1] |
798 |
1 |
|
T2 |
1 |
|
T5 |
9 |
|
T12 |
1 |
| others[2] |
802 |
1 |
|
T3 |
1 |
|
T5 |
10 |
|
T45 |
16 |
| others[3] |
1368 |
1 |
|
T5 |
13 |
|
T45 |
38 |
|
T194 |
1 |
| false |
437 |
1 |
|
T5 |
5 |
|
T45 |
6 |
|
T40 |
1 |
| true |
520 |
1 |
|
T2 |
1 |
|
T6 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2547 |
1 |
|
T5 |
5 |
|
T7 |
1 |
|
T22 |
45 |
| others[1] |
2622 |
1 |
|
T2 |
1 |
|
T5 |
15 |
|
T22 |
40 |
| others[2] |
2571 |
1 |
|
T5 |
10 |
|
T22 |
34 |
|
T37 |
1 |
| others[3] |
4175 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
11 |
| false |
1340 |
1 |
|
T5 |
6 |
|
T17 |
1 |
|
T22 |
19 |
| true |
1566 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10358 |
1 |
|
T2 |
1 |
|
T6 |
1 |
|
T7 |
1 |
| others[1] |
271 |
1 |
|
T1 |
1 |
|
T31 |
1 |
|
T24 |
1 |
| others[2] |
243 |
1 |
|
T2 |
1 |
|
T40 |
1 |
|
T20 |
7 |
| others[3] |
445 |
1 |
|
T37 |
1 |
|
T169 |
1 |
|
T46 |
1 |
| false |
153 |
1 |
|
T40 |
1 |
|
T20 |
6 |
|
T21 |
6 |
| true |
3351 |
1 |
|
T3 |
1 |
|
T5 |
47 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10556 |
1 |
|
T5 |
3 |
|
T22 |
202 |
|
T29 |
1 |
| others[1] |
501 |
1 |
|
T5 |
4 |
|
T7 |
1 |
|
T16 |
1 |
| others[2] |
454 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
8 |
| others[3] |
796 |
1 |
|
T5 |
12 |
|
T17 |
1 |
|
T45 |
17 |
| false |
235 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T45 |
3 |
| true |
2279 |
1 |
|
T3 |
1 |
|
T5 |
19 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10350 |
1 |
|
T22 |
202 |
|
T46 |
1 |
|
T133 |
1 |
| others[1] |
259 |
1 |
|
T17 |
1 |
|
T47 |
1 |
|
T20 |
10 |
| others[2] |
257 |
1 |
|
T169 |
1 |
|
T20 |
9 |
|
T21 |
12 |
| others[3] |
428 |
1 |
|
T2 |
1 |
|
T31 |
1 |
|
T24 |
1 |
| false |
127 |
1 |
|
T194 |
1 |
|
T48 |
1 |
|
T20 |
4 |
| true |
3400 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10355 |
1 |
|
T22 |
202 |
|
T37 |
1 |
|
T194 |
1 |
| others[1] |
291 |
1 |
|
T20 |
13 |
|
T21 |
11 |
|
T123 |
1 |
| others[2] |
257 |
1 |
|
T24 |
1 |
|
T48 |
1 |
|
T20 |
9 |
| others[3] |
374 |
1 |
|
T189 |
1 |
|
T20 |
15 |
|
T21 |
17 |
| false |
125 |
1 |
|
T20 |
4 |
|
T21 |
6 |
|
T59 |
6 |
| true |
3419 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10915 |
1 |
|
T5 |
11 |
|
T16 |
1 |
|
T22 |
202 |
| others[1] |
784 |
1 |
|
T5 |
5 |
|
T45 |
17 |
|
T40 |
3 |
| others[2] |
818 |
1 |
|
T5 |
12 |
|
T37 |
1 |
|
T169 |
1 |
| others[3] |
1358 |
1 |
|
T1 |
1 |
|
T5 |
15 |
|
T17 |
1 |
| false |
424 |
1 |
|
T5 |
4 |
|
T45 |
8 |
|
T20 |
7 |
| true |
522 |
1 |
|
T2 |
2 |
|
T3 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10896 |
1 |
|
T1 |
1 |
|
T5 |
8 |
|
T22 |
202 |
| others[1] |
792 |
1 |
|
T5 |
10 |
|
T45 |
22 |
|
T40 |
4 |
| others[2] |
800 |
1 |
|
T2 |
1 |
|
T5 |
12 |
|
T45 |
15 |
| others[3] |
1362 |
1 |
|
T2 |
1 |
|
T5 |
11 |
|
T37 |
1 |
| false |
455 |
1 |
|
T5 |
6 |
|
T45 |
9 |
|
T40 |
3 |
| true |
516 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2598 |
1 |
|
T5 |
10 |
|
T22 |
39 |
|
T45 |
19 |
| others[1] |
2528 |
1 |
|
T5 |
4 |
|
T22 |
46 |
|
T45 |
12 |
| others[2] |
2525 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
8 |
| others[3] |
4198 |
1 |
|
T5 |
20 |
|
T22 |
60 |
|
T37 |
1 |
| false |
1394 |
1 |
|
T2 |
1 |
|
T5 |
5 |
|
T17 |
1 |
| true |
1578 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10375 |
1 |
|
T22 |
202 |
|
T169 |
1 |
|
T31 |
1 |
| others[1] |
269 |
1 |
|
T37 |
1 |
|
T40 |
1 |
|
T20 |
6 |
| others[2] |
294 |
1 |
|
T2 |
1 |
|
T24 |
1 |
|
T40 |
1 |
| others[3] |
445 |
1 |
|
T17 |
1 |
|
T189 |
1 |
|
T40 |
1 |
| false |
136 |
1 |
|
T40 |
1 |
|
T58 |
1 |
|
T20 |
6 |
| true |
3302 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10531 |
1 |
|
T2 |
1 |
|
T5 |
5 |
|
T22 |
202 |
| others[1] |
458 |
1 |
|
T5 |
5 |
|
T17 |
1 |
|
T45 |
9 |
| others[2] |
489 |
1 |
|
T3 |
1 |
|
T5 |
4 |
|
T7 |
1 |
| others[3] |
805 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
6 |
| false |
263 |
1 |
|
T5 |
4 |
|
T16 |
1 |
|
T45 |
9 |
| true |
2275 |
1 |
|
T5 |
23 |
|
T37 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10326 |
1 |
|
T22 |
202 |
|
T189 |
1 |
|
T194 |
1 |
| others[1] |
241 |
1 |
|
T24 |
1 |
|
T48 |
1 |
|
T73 |
1 |
| others[2] |
248 |
1 |
|
T37 |
1 |
|
T18 |
1 |
|
T58 |
1 |
| others[3] |
440 |
1 |
|
T1 |
1 |
|
T169 |
1 |
|
T24 |
1 |
| false |
144 |
1 |
|
T20 |
6 |
|
T21 |
8 |
|
T121 |
1 |
| true |
3422 |
1 |
|
T2 |
2 |
|
T3 |
1 |
|
T5 |
47 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10346 |
1 |
|
T2 |
1 |
|
T22 |
202 |
|
T26 |
2 |
| others[1] |
254 |
1 |
|
T175 |
1 |
|
T20 |
10 |
|
T21 |
11 |
| others[2] |
264 |
1 |
|
T37 |
1 |
|
T20 |
9 |
|
T21 |
7 |
| others[3] |
395 |
1 |
|
T31 |
1 |
|
T194 |
1 |
|
T48 |
1 |
| false |
135 |
1 |
|
T20 |
6 |
|
T21 |
7 |
|
T25 |
1 |
| true |
3427 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10877 |
1 |
|
T5 |
9 |
|
T22 |
202 |
|
T45 |
16 |
| others[1] |
806 |
1 |
|
T5 |
10 |
|
T29 |
1 |
|
T45 |
14 |
| others[2] |
873 |
1 |
|
T5 |
8 |
|
T45 |
20 |
|
T24 |
2 |
| others[3] |
1328 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
17 |
| false |
451 |
1 |
|
T5 |
3 |
|
T16 |
1 |
|
T169 |
1 |
| true |
486 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10926 |
1 |
|
T2 |
2 |
|
T5 |
5 |
|
T22 |
202 |
| others[1] |
799 |
1 |
|
T5 |
7 |
|
T189 |
1 |
|
T45 |
19 |
| others[2] |
789 |
1 |
|
T5 |
12 |
|
T45 |
16 |
|
T40 |
3 |
| others[3] |
1340 |
1 |
|
T1 |
1 |
|
T5 |
18 |
|
T37 |
1 |
| false |
453 |
1 |
|
T5 |
5 |
|
T17 |
1 |
|
T45 |
11 |
| true |
514 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2557 |
1 |
|
T5 |
8 |
|
T17 |
1 |
|
T22 |
43 |
| others[1] |
2580 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
10 |
| others[2] |
2521 |
1 |
|
T5 |
8 |
|
T22 |
33 |
|
T45 |
22 |
| others[3] |
4260 |
1 |
|
T2 |
1 |
|
T5 |
17 |
|
T22 |
72 |
| false |
1342 |
1 |
|
T5 |
4 |
|
T22 |
16 |
|
T189 |
1 |
| true |
1561 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10344 |
1 |
|
T22 |
202 |
|
T31 |
1 |
|
T194 |
1 |
| others[1] |
282 |
1 |
|
T29 |
1 |
|
T28 |
1 |
|
T47 |
1 |
| others[2] |
280 |
1 |
|
T6 |
1 |
|
T169 |
1 |
|
T24 |
1 |
| others[3] |
468 |
1 |
|
T1 |
1 |
|
T7 |
1 |
|
T133 |
1 |
| false |
150 |
1 |
|
T20 |
7 |
|
T21 |
5 |
|
T134 |
1 |
| true |
3297 |
1 |
|
T2 |
2 |
|
T3 |
1 |
|
T5 |
47 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10605 |
1 |
|
T5 |
5 |
|
T22 |
202 |
|
T28 |
1 |
| others[1] |
482 |
1 |
|
T2 |
1 |
|
T5 |
3 |
|
T29 |
1 |
| others[2] |
458 |
1 |
|
T5 |
5 |
|
T7 |
1 |
|
T12 |
1 |
| others[3] |
770 |
1 |
|
T2 |
1 |
|
T5 |
10 |
|
T17 |
1 |
| false |
222 |
1 |
|
T45 |
5 |
|
T40 |
1 |
|
T20 |
3 |
| true |
2284 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T5 |
24 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10361 |
1 |
|
T22 |
202 |
|
T29 |
1 |
|
T37 |
1 |
| others[1] |
259 |
1 |
|
T2 |
1 |
|
T47 |
1 |
|
T48 |
1 |
| others[2] |
258 |
1 |
|
T1 |
1 |
|
T189 |
1 |
|
T46 |
1 |
| others[3] |
431 |
1 |
|
T7 |
1 |
|
T20 |
15 |
|
T21 |
15 |
| false |
138 |
1 |
|
T194 |
1 |
|
T24 |
1 |
|
T20 |
3 |
| true |
3374 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
47 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10298 |
1 |
|
T2 |
1 |
|
T17 |
1 |
|
T22 |
202 |
| others[1] |
273 |
1 |
|
T37 |
1 |
|
T175 |
1 |
|
T20 |
5 |
| others[2] |
283 |
1 |
|
T48 |
1 |
|
T20 |
9 |
|
T21 |
9 |
| others[3] |
432 |
1 |
|
T29 |
1 |
|
T31 |
1 |
|
T20 |
16 |
| false |
121 |
1 |
|
T20 |
7 |
|
T59 |
6 |
|
T127 |
2 |
| true |
3414 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10913 |
1 |
|
T5 |
12 |
|
T22 |
202 |
|
T45 |
18 |
| others[1] |
783 |
1 |
|
T5 |
9 |
|
T189 |
1 |
|
T45 |
16 |
| others[2] |
877 |
1 |
|
T2 |
1 |
|
T5 |
13 |
|
T45 |
18 |
| others[3] |
1316 |
1 |
|
T5 |
8 |
|
T37 |
1 |
|
T12 |
1 |
| false |
444 |
1 |
|
T1 |
1 |
|
T5 |
5 |
|
T45 |
15 |
| true |
488 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T6 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |