Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	1	15	93.75

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	1	15	93.75	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	227436	1		T1	322		T2	14		T3	6
auto[FlashEraseBank]	236310	1		T1	409		T2	8		T3	7

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	257342	1		T1	731		T2	9		T3	12
auto[FlashOpProgram]	185799	1		T2	12		T3	1		T4	288
auto[FlashOpErase]	16605	1		T2	1		T4	4		T22	301
auto[FlashOpInvalid]	4000	1		T279	200		T303	200		T304	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	257342	1		T1	731		T2	9		T3	12
op[FlashOpProgram]	185799	1		T2	12		T3	1		T4	288
op[FlashOpErase]	16605	1		T2	1		T4	4		T22	301
read_erase_read	736	1		T4	2		T24	1		T74	1
read_prog_read	1215	1		T2	4		T3	1		T6	3

---

Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	320482	1		T1	723		T2	9		T3	3
auto[FlashPartInfo]	139302	1		T2	6		T3	10		T4	309
auto[FlashPartInfo1]	820	1		T1	3		T2	2		T20	1
auto[FlashPartInfo2]	3142	1		T1	5		T2	5		T6	1

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for op_part_cross

Uncovered bins

part_cp	op_cp	COUNT	AT LEAST	NUMBER
[auto[FlashPartInfo1]]	[auto[FlashOpInvalid]]	0	1	1

Covered bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	191175	1		T1	723		T2	2		T3	2
auto[FlashPartData]	auto[FlashOpProgram]	121643	1		T2	6		T3	1		T17	1
auto[FlashPartData]	auto[FlashOpErase]	3734	1		T2	1		T24	1		T20	24
auto[FlashPartData]	auto[FlashOpInvalid]	3930	1		T279	192		T303	198		T304	200
auto[FlashPartInfo]	auto[FlashOpRead]	63529	1		T2	2		T3	10		T4	17
auto[FlashPartInfo]	auto[FlashOpProgram]	62870	1		T2	4		T4	288		T6	3
auto[FlashPartInfo]	auto[FlashOpErase]	12835	1		T4	4		T22	301		T74	8
auto[FlashPartInfo]	auto[FlashOpInvalid]	68	1		T279	8		T303	2		T343	8
auto[FlashPartInfo1]	auto[FlashOpRead]	688	1		T1	3		T2	2		T41	1
auto[FlashPartInfo1]	auto[FlashOpProgram]	130	1		T67	32		T113	32		T139	32
auto[FlashPartInfo1]	auto[FlashOpErase]	2	1		T20	1		T136	1		-	-
auto[FlashPartInfo2]	auto[FlashOpRead]	1950	1		T1	5		T2	3		T6	1
auto[FlashPartInfo2]	auto[FlashOpProgram]	1156	1		T2	2		T47	2		T135	1
auto[FlashPartInfo2]	auto[FlashOpErase]	34	1		T20	1		T25	1		T30	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	2	1		T343	2		-	-		-	-