Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.48	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	4	28	87.50

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	4	28	87.50	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	32223	1		T2	4		T22	580		T40	20
auto[1]	22	1		T3	1		T206	1		T332	1
auto[2]	162	1		T50	4		T51	4		T333	59
auto[3]	423	1		T6	1		T28	2		T46	2

---

Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	8268	1		T2	1		T6	1		T22	145
evic_idx[1]	8203	1		T2	1		T22	145		T28	1
evic_idx[2]	8181	1		T2	1		T22	145		T28	1
evic_idx[3]	8178	1		T2	1		T3	1		T22	145

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	31690	1		T22	580		T124	264		T193	452
evic_op[2]	530	1		T3	1		T6	1		T28	2

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	4	28	87.50	4

Automatically Generated Cross Bins for evic_all_cross

Element holes

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
*	[evic_op[1]]	[auto[1]]	--	--	4

Covered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7818	1		T22	145		T124	66		T193	113
evic_idx[0]	evic_op[1]	auto[2]	33	1		T334	33		-	-		-	-
evic_idx[0]	evic_op[1]	auto[3]	128	1		T204	10		T98	21		T335	17
evic_idx[0]	evic_op[2]	auto[0]	100	1		T40	5		T21	1		T143	4
evic_idx[0]	evic_op[2]	auto[1]	10	1		T206	1		T188	1		T336	1
evic_idx[0]	evic_op[2]	auto[2]	15	1		T333	14		T337	1		-	-
evic_idx[0]	evic_op[2]	auto[3]	11	1		T6	1		T46	1		T111	1
evic_idx[1]	evic_op[1]	auto[0]	7810	1		T22	145		T124	66		T193	113
evic_idx[1]	evic_op[1]	auto[2]	13	1		T334	13		-	-		-	-
evic_idx[1]	evic_op[1]	auto[3]	101	1		T204	7		T98	14		T335	16
evic_idx[1]	evic_op[2]	auto[0]	90	1		T40	5		T21	1		T143	4
evic_idx[1]	evic_op[2]	auto[1]	4	1		T332	1		T207	1		T338	2
evic_idx[1]	evic_op[2]	auto[2]	24	1		T333	17		T337	7		-	-
evic_idx[1]	evic_op[2]	auto[3]	8	1		T28	1		T36	1		T282	1
evic_idx[2]	evic_op[1]	auto[0]	7814	1		T22	145		T124	66		T193	113
evic_idx[2]	evic_op[1]	auto[2]	8	1		T334	8		-	-		-	-
evic_idx[2]	evic_op[1]	auto[3]	74	1		T204	3		T98	12		T335	9
evic_idx[2]	evic_op[2]	auto[0]	98	1		T40	5		T21	1		T143	4
evic_idx[2]	evic_op[2]	auto[1]	2	1		T338	2		-	-		-	-
evic_idx[2]	evic_op[2]	auto[2]	21	1		T333	14		T337	7		-	-
evic_idx[2]	evic_op[2]	auto[3]	12	1		T28	1		T134	1		T283	1
evic_idx[3]	evic_op[1]	auto[0]	7812	1		T22	145		T124	66		T193	113
evic_idx[3]	evic_op[1]	auto[2]	5	1		T334	5		-	-		-	-
evic_idx[3]	evic_op[1]	auto[3]	74	1		T204	11		T98	11		T335	7
evic_idx[3]	evic_op[2]	auto[0]	95	1		T40	5		T21	1		T143	4
evic_idx[3]	evic_op[2]	auto[1]	6	1		T3	1		T188	1		T339	1
evic_idx[3]	evic_op[2]	auto[2]	19	1		T333	14		T337	5		-	-
evic_idx[3]	evic_op[2]	auto[3]	15	1		T46	1		T111	1		T134	1