Summary for Variable instr_type_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
3 | 
0 | 
3 | 
100.00 | 
User Defined Bins for instr_type_cp
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others | 
5430 | 
1 | 
 | 
T5 | 
81 | 
 | 
T38 | 
127 | 
 | 
T39 | 
59 | 
| instr_types[0] | 
7142 | 
1 | 
 | 
T5 | 
189 | 
 | 
T38 | 
269 | 
 | 
T39 | 
196 | 
| instr_types[1] | 
4477461 | 
1 | 
 | 
T1 | 
16568 | 
 | 
T3 | 
10 | 
 | 
T5 | 
307 | 
Summary for Variable key_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for key_cp
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
4488004 | 
1 | 
 | 
T1 | 
16568 | 
 | 
T3 | 
10 | 
 | 
T5 | 
401 | 
| auto[1] | 
2029 | 
1 | 
 | 
T5 | 
176 | 
 | 
T38 | 
248 | 
 | 
T39 | 
155 | 
Summary for Cross key_instr_cross
Samples crossed: key_cp instr_type_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
6 | 
0 | 
6 | 
100.00 | 
 | 
Automatically Generated Cross Bins for key_instr_cross
Bins
| key_cp | instr_type_cp | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
others | 
4948 | 
1 | 
 | 
T5 | 
35 | 
 | 
T38 | 
101 | 
 | 
T39 | 
34 | 
| auto[0] | 
instr_types[0] | 
6392 | 
1 | 
 | 
T5 | 
166 | 
 | 
T38 | 
184 | 
 | 
T39 | 
131 | 
| auto[0] | 
instr_types[1] | 
4476664 | 
1 | 
 | 
T1 | 
16568 | 
 | 
T3 | 
10 | 
 | 
T5 | 
200 | 
| auto[1] | 
others | 
482 | 
1 | 
 | 
T5 | 
46 | 
 | 
T38 | 
26 | 
 | 
T39 | 
25 | 
| auto[1] | 
instr_types[0] | 
750 | 
1 | 
 | 
T5 | 
23 | 
 | 
T38 | 
85 | 
 | 
T39 | 
65 | 
| auto[1] | 
instr_types[1] | 
797 | 
1 | 
 | 
T5 | 
107 | 
 | 
T38 | 
137 | 
 | 
T39 | 
65 |