Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	0	3	100.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for prog_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
prog_lvl[1]	29447	1		T70	2964		T71	2992		T72	3477
prog_lvl[2]	3239	1		T70	1		T71	123		T72	1
prog_lvl[3]	4	1		T391	1		T392	1		T393	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	5415	1		T18	1363		T73	5		T126	1473
rd_lvl[2]	20471	1		T18	795		T73	10		T120	4148
rd_lvl[3]	19322	1		T73	24		T120	1508		T34	19
rd_lvl[4]	28734	1		T73	12		T34	9		T394	2586
rd_lvl[5]	13793	1		T73	6		T34	8		T395	1777
rd_lvl[6]	8595	1		T73	2		T34	385		T395	1163
rd_lvl[7]	8808	1		T73	827		T34	1136		T396	786
rd_lvl[8]	9246	1		T58	1562		T34	526		T223	1
rd_lvl[9]	5181	1		T73	620		T58	320		T397	245
rd_lvl[10]	3719	1		T73	461		T34	1		T76	535
rd_lvl[11]	3598	1		T34	56		T76	458		T214	2
rd_lvl[12]	6941	1		T397	1		T214	23		T242	449
rd_lvl[13]	6577	1		T48	499		T73	5		T398	574
rd_lvl[14]	3309	1		T48	380		T76	24		T398	267
rd_lvl[15]	4135	1		T399	640		T400	510		T401	576