Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	318922	1		T1	2		T2	2		T3	1
all_pins[1]	318922	1		T1	2		T2	2		T3	1
all_pins[2]	318922	1		T1	2		T2	2		T3	1
all_pins[3]	318922	1		T1	2		T2	2		T3	1
all_pins[4]	318922	1		T1	2		T2	2		T3	1
all_pins[5]	318922	1		T1	2		T2	2		T3	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1544343	1		T1	12		T2	12		T3	6
values[0x1]	369189	1		T48	1758		T18	2960		T73	3063
transitions[0x0=>0x1]	343637	1		T48	1758		T18	2952		T73	2236
transitions[0x1=>0x0]	343648	1		T48	1758		T18	2952		T73	2236

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	249887	1		T1	2		T2	2		T3	1
all_pins[0]	values[0x1]	69035	1		T70	2381		T71	3176		T72	2593
all_pins[0]	transitions[0x0=>0x1]	69015	1		T70	2381		T71	3176		T72	2593
all_pins[0]	transitions[0x1=>0x0]	40160	1		T70	3953		T71	4153		T72	4637
all_pins[1]	values[0x0]	278742	1		T1	2		T2	2		T3	1
all_pins[1]	values[0x1]	40180	1		T70	3953		T71	4153		T72	4637
all_pins[1]	transitions[0x0=>0x1]	40167	1		T70	3953		T71	4153		T72	4637
all_pins[1]	transitions[0x1=>0x0]	9586	1		T73	5		T34	56		T76	24
all_pins[2]	values[0x0]	309323	1		T1	2		T2	2		T3	1
all_pins[2]	values[0x1]	9599	1		T73	5		T34	56		T76	24
all_pins[2]	transitions[0x0=>0x1]	7149	1		T73	5		T34	56		T76	24
all_pins[2]	transitions[0x1=>0x0]	150185	1		T48	879		T18	2158		T73	1972
all_pins[3]	values[0x0]	166287	1		T1	2		T2	2		T3	1
all_pins[3]	values[0x1]	152635	1		T48	879		T18	2158		T73	1972
all_pins[3]	transitions[0x0=>0x1]	129615	1		T48	879		T18	2150		T73	1145
all_pins[3]	transitions[0x1=>0x0]	74643	1		T48	879		T18	794		T73	259
all_pins[4]	values[0x0]	221259	1		T1	2		T2	2		T3	1
all_pins[4]	values[0x1]	97663	1		T48	879		T18	802		T73	1086
all_pins[4]	transitions[0x0=>0x1]	97634	1		T48	879		T18	802		T73	1086
all_pins[4]	transitions[0x1=>0x0]	48	1		T260	2		T345	2		T346	3
all_pins[5]	values[0x0]	318845	1		T1	2		T2	2		T3	1
all_pins[5]	values[0x1]	77	1		T260	2		T262	1		T345	3
all_pins[5]	transitions[0x0=>0x1]	57	1		T260	2		T262	1		T345	3
all_pins[5]	transitions[0x1=>0x0]	69026	1		T70	2381		T71	3176		T72	2593