Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	284	1		T260	4		T261	7		T262	7
all_values[1]	284	1		T260	4		T261	7		T262	7
all_values[2]	284	1		T260	4		T261	7		T262	7
all_values[3]	284	1		T260	4		T261	7		T262	7
all_values[4]	284	1		T260	4		T261	7		T262	7
all_values[5]	284	1		T260	4		T261	7		T262	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	890	1		T260	14		T261	26		T262	20
auto[1]	814	1		T260	10		T261	16		T262	22

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	637	1		T260	13		T261	20		T262	8
auto[1]	1067	1		T260	11		T261	22		T262	34

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	986	1		T260	17		T261	24		T262	23
auto[1]	718	1		T260	7		T261	18		T262	19

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	36	0	36	100.00
Automatically Generated Cross Bins	36	0	36	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	65	1		T260	2		T261	3		T344	1
all_values[0]	auto[0]	auto[0]	auto[1]	24	1		T262	1		T347	1		T348	1
all_values[0]	auto[0]	auto[1]	auto[0]	54	1		T260	1		T262	1		T344	2
all_values[0]	auto[0]	auto[1]	auto[1]	33	1		T261	1		T262	3		T344	1
all_values[0]	auto[1]	auto[0]	auto[1]	43	1		T261	1		T262	2		T344	2
all_values[0]	auto[1]	auto[1]	auto[1]	65	1		T260	1		T261	2		T344	1
all_values[1]	auto[0]	auto[0]	auto[0]	55	1		T260	2		T261	1		T262	2
all_values[1]	auto[0]	auto[0]	auto[1]	29	1		T261	1		T262	1		T344	1
all_values[1]	auto[0]	auto[1]	auto[0]	52	1		T345	1		T347	1		T349	1
all_values[1]	auto[0]	auto[1]	auto[1]	23	1		T260	1		T262	1		T345	1
all_values[1]	auto[1]	auto[0]	auto[1]	72	1		T260	1		T261	5		T262	2
all_values[1]	auto[1]	auto[1]	auto[1]	53	1		T262	1		T344	1		T345	1
all_values[2]	auto[0]	auto[0]	auto[0]	66	1		T260	1		T261	1		T344	1
all_values[2]	auto[0]	auto[0]	auto[1]	28	1		T344	2		T347	1		T350	4
all_values[2]	auto[0]	auto[1]	auto[0]	40	1		T260	2		T261	3		T262	3
all_values[2]	auto[0]	auto[1]	auto[1]	29	1		T344	2		T347	1		T349	1
all_values[2]	auto[1]	auto[0]	auto[1]	60	1		T261	1		T262	1		T345	4
all_values[2]	auto[1]	auto[1]	auto[1]	61	1		T260	1		T261	2		T262	3
all_values[3]	auto[0]	auto[0]	auto[0]	56	1		T261	3		T345	4		T346	2
all_values[3]	auto[0]	auto[0]	auto[1]	33	1		T260	1		T344	2		T345	1
all_values[3]	auto[0]	auto[1]	auto[0]	60	1		T260	1		T261	1		T262	2
all_values[3]	auto[0]	auto[1]	auto[1]	26	1		T260	1		T261	1		T262	2
all_values[3]	auto[1]	auto[0]	auto[1]	64	1		T261	2		T262	1		T344	2
all_values[3]	auto[1]	auto[1]	auto[1]	45	1		T260	1		T262	2		T344	2
all_values[4]	auto[0]	auto[0]	auto[0]	54	1		T260	4		T261	2		T347	1
all_values[4]	auto[0]	auto[0]	auto[1]	38	1		T262	3		T344	2		T345	2
all_values[4]	auto[0]	auto[1]	auto[0]	37	1		T261	1		T346	4		T347	1
all_values[4]	auto[0]	auto[1]	auto[1]	28	1		T261	1		T262	1		T344	1
all_values[4]	auto[1]	auto[0]	auto[1]	58	1		T261	2		T262	1		T345	3
all_values[4]	auto[1]	auto[1]	auto[1]	69	1		T261	1		T262	2		T344	4
all_values[5]	auto[0]	auto[0]	auto[0]	51	1		T261	3		T350	3		T351	2
all_values[5]	auto[0]	auto[0]	auto[1]	28	1		T262	2		T345	2		T349	1
all_values[5]	auto[0]	auto[1]	auto[0]	47	1		T261	2		T344	4		T349	2
all_values[5]	auto[0]	auto[1]	auto[1]	30	1		T260	1		T262	1		T345	1
all_values[5]	auto[1]	auto[0]	auto[1]	66	1		T260	3		T261	1		T262	4
all_values[5]	auto[1]	auto[1]	auto[1]	62	1		T261	1		T344	2		T345	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal