| T1073 |
/workspace/coverage/default/76.flash_ctrl_otp_reset.838661637 |
|
|
Feb 29 02:42:52 PM PST 24 |
Feb 29 02:45:09 PM PST 24 |
150359900 ps |
| T1074 |
/workspace/coverage/default/6.flash_ctrl_alert_test.2739603316 |
|
|
Feb 29 02:34:54 PM PST 24 |
Feb 29 02:35:08 PM PST 24 |
29683000 ps |
| T1075 |
/workspace/coverage/default/14.flash_ctrl_otp_reset.62144023 |
|
|
Feb 29 02:37:23 PM PST 24 |
Feb 29 02:39:36 PM PST 24 |
276657500 ps |
| T1076 |
/workspace/coverage/default/11.flash_ctrl_invalid_op.3438692150 |
|
|
Feb 29 02:36:25 PM PST 24 |
Feb 29 02:37:37 PM PST 24 |
12201797400 ps |
| T1077 |
/workspace/coverage/default/2.flash_ctrl_intr_rd.3746109824 |
|
|
Feb 29 02:32:15 PM PST 24 |
Feb 29 02:34:55 PM PST 24 |
2413751500 ps |
| T1078 |
/workspace/coverage/default/16.flash_ctrl_disable.4147966348 |
|
|
Feb 29 02:38:16 PM PST 24 |
Feb 29 02:38:39 PM PST 24 |
37833900 ps |
| T1079 |
/workspace/coverage/default/11.flash_ctrl_hw_prog_rma_wipe_err.4188424188 |
|
|
Feb 29 02:36:33 PM PST 24 |
Feb 29 02:38:23 PM PST 24 |
10015411500 ps |
| T1080 |
/workspace/coverage/default/17.flash_ctrl_phy_arb.3056958308 |
|
|
Feb 29 02:38:31 PM PST 24 |
Feb 29 02:42:59 PM PST 24 |
135200100 ps |
| T1081 |
/workspace/coverage/default/28.flash_ctrl_intr_rd.1771548273 |
|
|
Feb 29 02:40:25 PM PST 24 |
Feb 29 02:42:57 PM PST 24 |
1127074000 ps |
| T1082 |
/workspace/coverage/default/1.flash_ctrl_hw_prog_rma_wipe_err.1411837148 |
|
|
Feb 29 02:32:14 PM PST 24 |
Feb 29 02:33:03 PM PST 24 |
10045601100 ps |
| T1083 |
/workspace/coverage/default/1.flash_ctrl_intr_wr_slow_flash.1053849165 |
|
|
Feb 29 02:32:01 PM PST 24 |
Feb 29 02:38:10 PM PST 24 |
47358161100 ps |
| T1084 |
/workspace/coverage/default/22.flash_ctrl_intr_rd.1585846411 |
|
|
Feb 29 02:39:41 PM PST 24 |
Feb 29 02:43:02 PM PST 24 |
5890480600 ps |
| T1085 |
/workspace/coverage/default/68.flash_ctrl_otp_reset.1973097630 |
|
|
Feb 29 02:42:42 PM PST 24 |
Feb 29 02:44:56 PM PST 24 |
138034400 ps |
| T1086 |
/workspace/coverage/default/15.flash_ctrl_intr_rd.2148289380 |
|
|
Feb 29 02:37:45 PM PST 24 |
Feb 29 02:40:35 PM PST 24 |
4394961300 ps |
| T1087 |
/workspace/coverage/default/6.flash_ctrl_rw_serr.3031483504 |
|
|
Feb 29 02:34:29 PM PST 24 |
Feb 29 02:45:35 PM PST 24 |
7902571300 ps |
| T1088 |
/workspace/coverage/default/5.flash_ctrl_phy_arb.1741991348 |
|
|
Feb 29 02:33:56 PM PST 24 |
Feb 29 02:38:56 PM PST 24 |
2801341600 ps |
| T1089 |
/workspace/coverage/default/25.flash_ctrl_disable.4190912352 |
|
|
Feb 29 02:39:57 PM PST 24 |
Feb 29 02:40:18 PM PST 24 |
35689200 ps |
| T1090 |
/workspace/coverage/default/1.flash_ctrl_error_prog_win.3269289177 |
|
|
Feb 29 02:32:06 PM PST 24 |
Feb 29 02:45:32 PM PST 24 |
765243700 ps |
| T1091 |
/workspace/coverage/default/21.flash_ctrl_otp_reset.2736388103 |
|
|
Feb 29 02:39:27 PM PST 24 |
Feb 29 02:41:42 PM PST 24 |
35514700 ps |
| T1092 |
/workspace/coverage/default/17.flash_ctrl_prog_reset.683911044 |
|
|
Feb 29 02:38:29 PM PST 24 |
Feb 29 02:38:44 PM PST 24 |
51434200 ps |
| T1093 |
/workspace/coverage/default/18.flash_ctrl_ro.1136920644 |
|
|
Feb 29 02:38:43 PM PST 24 |
Feb 29 02:40:21 PM PST 24 |
2009814000 ps |
| T1094 |
/workspace/coverage/default/27.flash_ctrl_sec_info_access.2207615268 |
|
|
Feb 29 02:40:27 PM PST 24 |
Feb 29 02:41:18 PM PST 24 |
670793300 ps |
| T1095 |
/workspace/coverage/default/15.flash_ctrl_disable.1247681984 |
|
|
Feb 29 02:37:47 PM PST 24 |
Feb 29 02:38:08 PM PST 24 |
17170500 ps |
| T1096 |
/workspace/coverage/default/7.flash_ctrl_prog_reset.3554479405 |
|
|
Feb 29 02:35:01 PM PST 24 |
Feb 29 02:35:15 PM PST 24 |
22011700 ps |
| T1097 |
/workspace/coverage/default/0.flash_ctrl_lcmgr_intg.3418910903 |
|
|
Feb 29 02:31:50 PM PST 24 |
Feb 29 02:32:04 PM PST 24 |
15404700 ps |
| T1098 |
/workspace/coverage/default/2.flash_ctrl_hw_rma.639924175 |
|
|
Feb 29 02:32:13 PM PST 24 |
Feb 29 03:00:59 PM PST 24 |
170302486700 ps |
| T1099 |
/workspace/coverage/default/20.flash_ctrl_disable.3221011292 |
|
|
Feb 29 02:39:25 PM PST 24 |
Feb 29 02:39:46 PM PST 24 |
43032000 ps |
| T1100 |
/workspace/coverage/default/26.flash_ctrl_rw_evict.2684190823 |
|
|
Feb 29 02:40:13 PM PST 24 |
Feb 29 02:40:44 PM PST 24 |
84914700 ps |
| T1101 |
/workspace/coverage/default/37.flash_ctrl_otp_reset.2157995581 |
|
|
Feb 29 02:41:22 PM PST 24 |
Feb 29 02:43:35 PM PST 24 |
75026200 ps |
| T1102 |
/workspace/coverage/default/10.flash_ctrl_disable.3939748799 |
|
|
Feb 29 02:36:16 PM PST 24 |
Feb 29 02:36:39 PM PST 24 |
29030300 ps |
| T1103 |
/workspace/coverage/default/5.flash_ctrl_hw_read_seed_err.1023574251 |
|
|
Feb 29 02:34:19 PM PST 24 |
Feb 29 02:34:33 PM PST 24 |
14792400 ps |
| T1104 |
/workspace/coverage/default/33.flash_ctrl_connect.1662681796 |
|
|
Feb 29 02:41:03 PM PST 24 |
Feb 29 02:41:20 PM PST 24 |
16418600 ps |
| T1105 |
/workspace/coverage/default/13.flash_ctrl_otp_reset.1881370645 |
|
|
Feb 29 02:37:11 PM PST 24 |
Feb 29 02:39:26 PM PST 24 |
137519600 ps |
| T1106 |
/workspace/coverage/default/0.flash_ctrl_fs_sup.1773658881 |
|
|
Feb 29 02:31:50 PM PST 24 |
Feb 29 02:32:30 PM PST 24 |
4450099700 ps |
| T1107 |
/workspace/coverage/default/6.flash_ctrl_error_prog_win.1511271797 |
|
|
Feb 29 02:34:18 PM PST 24 |
Feb 29 02:49:50 PM PST 24 |
797800900 ps |
| T1108 |
/workspace/coverage/default/10.flash_ctrl_hw_prog_rma_wipe_err.3896284634 |
|
|
Feb 29 02:36:16 PM PST 24 |
Feb 29 02:37:10 PM PST 24 |
10034648800 ps |
| T1109 |
/workspace/coverage/default/11.flash_ctrl_prog_reset.121470286 |
|
|
Feb 29 02:36:33 PM PST 24 |
Feb 29 02:36:47 PM PST 24 |
90655600 ps |
| T1110 |
/workspace/coverage/default/4.flash_ctrl_rd_buff_evict.639609245 |
|
|
Feb 29 02:33:12 PM PST 24 |
Feb 29 02:35:47 PM PST 24 |
2599584300 ps |
| T1111 |
/workspace/coverage/default/43.flash_ctrl_smoke.2097956621 |
|
|
Feb 29 02:41:55 PM PST 24 |
Feb 29 02:43:34 PM PST 24 |
76715400 ps |
| T1112 |
/workspace/coverage/default/14.flash_ctrl_hw_prog_rma_wipe_err.2363753708 |
|
|
Feb 29 02:37:35 PM PST 24 |
Feb 29 02:39:09 PM PST 24 |
10032925900 ps |
| T1113 |
/workspace/coverage/default/18.flash_ctrl_lcmgr_intg.793083753 |
|
|
Feb 29 02:38:56 PM PST 24 |
Feb 29 02:39:10 PM PST 24 |
26086500 ps |
| T1114 |
/workspace/coverage/default/31.flash_ctrl_hw_sec_otp.3573856376 |
|
|
Feb 29 02:40:53 PM PST 24 |
Feb 29 02:42:20 PM PST 24 |
4075317200 ps |
| T1115 |
/workspace/coverage/default/38.flash_ctrl_alert_test.3987817940 |
|
|
Feb 29 02:41:31 PM PST 24 |
Feb 29 02:41:46 PM PST 24 |
28722900 ps |
| T1116 |
/workspace/coverage/default/25.flash_ctrl_smoke.1363087386 |
|
|
Feb 29 02:39:59 PM PST 24 |
Feb 29 02:42:48 PM PST 24 |
157653500 ps |
| T1117 |
/workspace/coverage/default/32.flash_ctrl_hw_sec_otp.4216139499 |
|
|
Feb 29 02:40:50 PM PST 24 |
Feb 29 02:42:41 PM PST 24 |
2880093500 ps |
| T1118 |
/workspace/coverage/default/32.flash_ctrl_smoke.3899128689 |
|
|
Feb 29 02:40:47 PM PST 24 |
Feb 29 02:43:17 PM PST 24 |
1171026000 ps |
| T1119 |
/workspace/coverage/default/4.flash_ctrl_phy_host_grant_err.1112196464 |
|
|
Feb 29 02:33:52 PM PST 24 |
Feb 29 02:34:07 PM PST 24 |
44079100 ps |
| T1120 |
/workspace/coverage/default/6.flash_ctrl_invalid_op.1517436508 |
|
|
Feb 29 02:34:18 PM PST 24 |
Feb 29 02:35:25 PM PST 24 |
2374369500 ps |
| T1121 |
/workspace/coverage/default/4.flash_ctrl_sw_op.2651008937 |
|
|
Feb 29 02:33:12 PM PST 24 |
Feb 29 02:33:39 PM PST 24 |
22744300 ps |
| T1122 |
/workspace/coverage/default/1.flash_ctrl_rw.1791309739 |
|
|
Feb 29 02:32:04 PM PST 24 |
Feb 29 02:40:37 PM PST 24 |
11445227300 ps |
| T1123 |
/workspace/coverage/default/37.flash_ctrl_smoke.2065948765 |
|
|
Feb 29 02:41:23 PM PST 24 |
Feb 29 02:43:51 PM PST 24 |
36323100 ps |
| T1124 |
/workspace/coverage/default/4.flash_ctrl_intr_rd.789574409 |
|
|
Feb 29 02:33:43 PM PST 24 |
Feb 29 02:36:44 PM PST 24 |
2655244600 ps |
| T1125 |
/workspace/coverage/default/15.flash_ctrl_rw_evict_all_en.1500158627 |
|
|
Feb 29 02:37:49 PM PST 24 |
Feb 29 02:38:20 PM PST 24 |
30804900 ps |
| T69 |
/workspace/coverage/default/4.flash_ctrl_hw_read_seed_err.1167515482 |
|
|
Feb 29 02:33:55 PM PST 24 |
Feb 29 02:34:09 PM PST 24 |
25683500 ps |
| T1126 |
/workspace/coverage/default/16.flash_ctrl_alert_test.4200494839 |
|
|
Feb 29 02:38:18 PM PST 24 |
Feb 29 02:38:31 PM PST 24 |
78048700 ps |
| T1127 |
/workspace/coverage/default/1.flash_ctrl_config_regwen.1551479331 |
|
|
Feb 29 02:32:17 PM PST 24 |
Feb 29 02:32:31 PM PST 24 |
20170700 ps |
| T1128 |
/workspace/coverage/default/26.flash_ctrl_otp_reset.647558465 |
|
|
Feb 29 02:40:11 PM PST 24 |
Feb 29 02:42:24 PM PST 24 |
74619500 ps |
| T252 |
/workspace/coverage/default/0.flash_ctrl_integrity.279451449 |
|
|
Feb 29 02:31:42 PM PST 24 |
Feb 29 02:41:51 PM PST 24 |
24066661600 ps |
| T1129 |
/workspace/coverage/default/37.flash_ctrl_rw_evict_all_en.702540831 |
|
|
Feb 29 02:41:22 PM PST 24 |
Feb 29 02:41:54 PM PST 24 |
54520600 ps |
| T1130 |
/workspace/coverage/default/30.flash_ctrl_intr_rd.2197386882 |
|
|
Feb 29 02:40:39 PM PST 24 |
Feb 29 02:42:56 PM PST 24 |
1998346600 ps |
| T1131 |
/workspace/coverage/default/26.flash_ctrl_hw_sec_otp.3055404463 |
|
|
Feb 29 02:40:10 PM PST 24 |
Feb 29 02:42:54 PM PST 24 |
4462174900 ps |
| T53 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.3159351129 |
|
|
Feb 29 01:33:39 PM PST 24 |
Feb 29 01:41:16 PM PST 24 |
3257362900 ps |
| T54 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.3584284364 |
|
|
Feb 29 01:34:26 PM PST 24 |
Feb 29 01:42:18 PM PST 24 |
1739207000 ps |
| T55 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.1315732219 |
|
|
Feb 29 01:33:16 PM PST 24 |
Feb 29 01:33:55 PM PST 24 |
3988955400 ps |
| T221 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.492906497 |
|
|
Feb 29 01:33:40 PM PST 24 |
Feb 29 01:33:57 PM PST 24 |
50718700 ps |
| T260 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.910947524 |
|
|
Feb 29 01:34:03 PM PST 24 |
Feb 29 01:34:17 PM PST 24 |
14850500 ps |
| T253 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.1000956541 |
|
|
Feb 29 01:34:16 PM PST 24 |
Feb 29 01:34:33 PM PST 24 |
35827600 ps |
| T261 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.1098838567 |
|
|
Feb 29 01:34:17 PM PST 24 |
Feb 29 01:34:30 PM PST 24 |
15093800 ps |
| T254 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.3975460061 |
|
|
Feb 29 01:33:53 PM PST 24 |
Feb 29 01:34:11 PM PST 24 |
89897500 ps |
| T1132 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.3538809426 |
|
|
Feb 29 01:34:24 PM PST 24 |
Feb 29 01:34:40 PM PST 24 |
13027600 ps |
| T195 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.2835701958 |
|
|
Feb 29 01:34:16 PM PST 24 |
Feb 29 01:46:55 PM PST 24 |
2665775600 ps |
| T255 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.3250608126 |
|
|
Feb 29 01:34:05 PM PST 24 |
Feb 29 01:34:26 PM PST 24 |
760396500 ps |
| T262 |
/workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.248239853 |
|
|
Feb 29 01:34:36 PM PST 24 |
Feb 29 01:34:49 PM PST 24 |
17985200 ps |
| T1133 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.4113944411 |
|
|
Feb 29 01:33:38 PM PST 24 |
Feb 29 01:33:55 PM PST 24 |
63508700 ps |
| T217 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.725842102 |
|
|
Feb 29 01:33:48 PM PST 24 |
Feb 29 01:34:05 PM PST 24 |
138710200 ps |
| T1134 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.1147541274 |
|
|
Feb 29 01:34:15 PM PST 24 |
Feb 29 01:34:31 PM PST 24 |
14086100 ps |
| T308 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.2607357441 |
|
|
Feb 29 01:33:17 PM PST 24 |
Feb 29 01:33:58 PM PST 24 |
1694422900 ps |
| T220 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.4160385174 |
|
|
Feb 29 01:34:18 PM PST 24 |
Feb 29 01:49:15 PM PST 24 |
1551923300 ps |
| T1135 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.3523377798 |
|
|
Feb 29 01:34:16 PM PST 24 |
Feb 29 01:34:32 PM PST 24 |
35576700 ps |
| T218 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.2745870911 |
|
|
Feb 29 01:33:39 PM PST 24 |
Feb 29 01:33:59 PM PST 24 |
284462500 ps |
| T1136 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.1684317356 |
|
|
Feb 29 01:34:27 PM PST 24 |
Feb 29 01:34:43 PM PST 24 |
14157400 ps |
| T1137 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.20978933 |
|
|
Feb 29 01:34:18 PM PST 24 |
Feb 29 01:34:34 PM PST 24 |
46289000 ps |
| T1138 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.3007308269 |
|
|
Feb 29 01:33:28 PM PST 24 |
Feb 29 01:33:45 PM PST 24 |
44341500 ps |
| T344 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.549011578 |
|
|
Feb 29 01:34:13 PM PST 24 |
Feb 29 01:34:27 PM PST 24 |
25311400 ps |
| T267 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.461202980 |
|
|
Feb 29 01:33:17 PM PST 24 |
Feb 29 01:33:48 PM PST 24 |
194261800 ps |
| T1139 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.3332378332 |
|
|
Feb 29 01:33:28 PM PST 24 |
Feb 29 01:34:12 PM PST 24 |
97264600 ps |
| T219 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.105146908 |
|
|
Feb 29 01:34:19 PM PST 24 |
Feb 29 01:34:38 PM PST 24 |
93915900 ps |
| T1140 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.4092624461 |
|
|
Feb 29 01:33:06 PM PST 24 |
Feb 29 01:33:34 PM PST 24 |
28791800 ps |
| T233 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.2611752516 |
|
|
Feb 29 01:33:29 PM PST 24 |
Feb 29 01:33:43 PM PST 24 |
78363600 ps |
| T345 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.3919108185 |
|
|
Feb 29 01:33:08 PM PST 24 |
Feb 29 01:33:23 PM PST 24 |
31061300 ps |
| T225 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.1831306576 |
|
|
Feb 29 01:34:18 PM PST 24 |
Feb 29 01:34:35 PM PST 24 |
189047200 ps |
| T346 |
/workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.3689365287 |
|
|
Feb 29 01:34:37 PM PST 24 |
Feb 29 01:34:51 PM PST 24 |
18055500 ps |
| T1141 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.1811654620 |
|
|
Feb 29 01:34:18 PM PST 24 |
Feb 29 01:34:36 PM PST 24 |
27402900 ps |
| T1142 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.1394501653 |
|
|
Feb 29 01:33:40 PM PST 24 |
Feb 29 01:33:53 PM PST 24 |
16487600 ps |
| T1143 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.3386487915 |
|
|
Feb 29 01:33:32 PM PST 24 |
Feb 29 01:33:48 PM PST 24 |
17564100 ps |
| T347 |
/workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.1097858702 |
|
|
Feb 29 01:34:38 PM PST 24 |
Feb 29 01:34:52 PM PST 24 |
176014200 ps |
| T1144 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.4102906077 |
|
|
Feb 29 01:33:40 PM PST 24 |
Feb 29 01:33:55 PM PST 24 |
46752400 ps |
| T234 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.736290624 |
|
|
Feb 29 01:33:07 PM PST 24 |
Feb 29 01:33:21 PM PST 24 |
49201400 ps |
| T349 |
/workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.3907619320 |
|
|
Feb 29 01:34:35 PM PST 24 |
Feb 29 01:34:49 PM PST 24 |
16351500 ps |
| T226 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.2471243955 |
|
|
Feb 29 01:33:39 PM PST 24 |
Feb 29 01:33:56 PM PST 24 |
73281500 ps |
| T1145 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.3152656462 |
|
|
Feb 29 01:33:43 PM PST 24 |
Feb 29 01:34:27 PM PST 24 |
1189964500 ps |
| T309 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.3073003219 |
|
|
Feb 29 01:34:15 PM PST 24 |
Feb 29 01:34:50 PM PST 24 |
213628500 ps |
| T350 |
/workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.1697674169 |
|
|
Feb 29 01:34:36 PM PST 24 |
Feb 29 01:34:50 PM PST 24 |
172403500 ps |
| T1146 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.3645121303 |
|
|
Feb 29 01:33:31 PM PST 24 |
Feb 29 01:33:44 PM PST 24 |
23876800 ps |
| T227 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.466903828 |
|
|
Feb 29 01:33:40 PM PST 24 |
Feb 29 01:41:18 PM PST 24 |
734624800 ps |
| T228 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.3955688670 |
|
|
Feb 29 01:34:26 PM PST 24 |
Feb 29 01:34:45 PM PST 24 |
87587300 ps |
| T235 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.4177334410 |
|
|
Feb 29 01:33:28 PM PST 24 |
Feb 29 01:33:42 PM PST 24 |
35079500 ps |
| T1147 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.1284975731 |
|
|
Feb 29 01:33:40 PM PST 24 |
Feb 29 01:34:16 PM PST 24 |
834409700 ps |
| T229 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.966346720 |
|
|
Feb 29 01:33:17 PM PST 24 |
Feb 29 01:33:35 PM PST 24 |
157503800 ps |
| T348 |
/workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.474714475 |
|
|
Feb 29 01:34:37 PM PST 24 |
Feb 29 01:34:50 PM PST 24 |
17448900 ps |
| T1148 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.1910126689 |
|
|
Feb 29 01:34:26 PM PST 24 |
Feb 29 01:34:44 PM PST 24 |
89949300 ps |
| T230 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.914345878 |
|
|
Feb 29 01:33:17 PM PST 24 |
Feb 29 01:33:35 PM PST 24 |
126135900 ps |
| T310 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.2744482173 |
|
|
Feb 29 01:34:16 PM PST 24 |
Feb 29 01:34:31 PM PST 24 |
673674300 ps |
| T1149 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.1290058656 |
|
|
Feb 29 01:34:39 PM PST 24 |
Feb 29 01:34:53 PM PST 24 |
17564000 ps |
| T1150 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.2613670345 |
|
|
Feb 29 01:33:49 PM PST 24 |
Feb 29 01:34:05 PM PST 24 |
40339900 ps |
| T1151 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.3772201707 |
|
|
Feb 29 01:34:27 PM PST 24 |
Feb 29 01:34:42 PM PST 24 |
71901700 ps |
| T311 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.4034513583 |
|
|
Feb 29 01:34:15 PM PST 24 |
Feb 29 01:34:31 PM PST 24 |
67047900 ps |
| T231 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.2131120928 |
|
|
Feb 29 01:33:27 PM PST 24 |
Feb 29 01:39:53 PM PST 24 |
414117800 ps |
| T1152 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.603340425 |
|
|
Feb 29 01:34:05 PM PST 24 |
Feb 29 01:34:20 PM PST 24 |
11876200 ps |
| T1153 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.2113898465 |
|
|
Feb 29 01:34:16 PM PST 24 |
Feb 29 01:34:32 PM PST 24 |
49154100 ps |
| T259 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.913623210 |
|
|
Feb 29 01:33:48 PM PST 24 |
Feb 29 01:34:08 PM PST 24 |
183220200 ps |
| T1154 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.2345879244 |
|
|
Feb 29 01:33:17 PM PST 24 |
Feb 29 01:33:30 PM PST 24 |
92625400 ps |
| T263 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.2570957795 |
|
|
Feb 29 01:33:33 PM PST 24 |
Feb 29 01:33:48 PM PST 24 |
110057600 ps |
| T1155 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.1422646640 |
|
|
Feb 29 01:33:38 PM PST 24 |
Feb 29 01:33:59 PM PST 24 |
623338800 ps |
| T1156 |
/workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.1317350025 |
|
|
Feb 29 01:34:37 PM PST 24 |
Feb 29 01:34:51 PM PST 24 |
80162600 ps |
| T1157 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.2493863545 |
|
|
Feb 29 01:34:04 PM PST 24 |
Feb 29 01:34:19 PM PST 24 |
13807700 ps |
| T351 |
/workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.2859347094 |
|
|
Feb 29 01:34:42 PM PST 24 |
Feb 29 01:34:55 PM PST 24 |
42592300 ps |
| T258 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.3908689436 |
|
|
Feb 29 01:34:14 PM PST 24 |
Feb 29 01:34:33 PM PST 24 |
40198900 ps |
| T1158 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.566328937 |
|
|
Feb 29 01:33:39 PM PST 24 |
Feb 29 01:33:59 PM PST 24 |
82689200 ps |
| T1159 |
/workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.205700757 |
|
|
Feb 29 01:34:36 PM PST 24 |
Feb 29 01:34:49 PM PST 24 |
58318300 ps |
| T1160 |
/workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.2208116032 |
|
|
Feb 29 01:34:39 PM PST 24 |
Feb 29 01:34:53 PM PST 24 |
17906700 ps |
| T1161 |
/workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.1438993187 |
|
|
Feb 29 01:34:38 PM PST 24 |
Feb 29 01:34:52 PM PST 24 |
31185200 ps |
| T312 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.3209848711 |
|
|
Feb 29 01:33:17 PM PST 24 |
Feb 29 01:34:32 PM PST 24 |
6194900500 ps |
| T270 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.3994284341 |
|
|
Feb 29 01:34:29 PM PST 24 |
Feb 29 01:34:46 PM PST 24 |
27032600 ps |
| T1162 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.3828737513 |
|
|
Feb 29 01:34:02 PM PST 24 |
Feb 29 01:34:15 PM PST 24 |
19145500 ps |
| T1163 |
/workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.492144233 |
|
|
Feb 29 01:34:36 PM PST 24 |
Feb 29 01:34:50 PM PST 24 |
16772200 ps |
| T1164 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.1774361646 |
|
|
Feb 29 01:33:27 PM PST 24 |
Feb 29 01:33:41 PM PST 24 |
28440900 ps |
| T1165 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.850457284 |
|
|
Feb 29 01:34:27 PM PST 24 |
Feb 29 01:34:42 PM PST 24 |
20193600 ps |
| T1166 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.3702544290 |
|
|
Feb 29 01:34:05 PM PST 24 |
Feb 29 01:34:21 PM PST 24 |
43087500 ps |
| T1167 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.44318155 |
|
|
Feb 29 01:34:04 PM PST 24 |
Feb 29 01:34:24 PM PST 24 |
79783200 ps |
| T1168 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.3967559950 |
|
|
Feb 29 01:34:43 PM PST 24 |
Feb 29 01:34:57 PM PST 24 |
28535300 ps |
| T352 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.600934549 |
|
|
Feb 29 01:34:03 PM PST 24 |
Feb 29 01:40:21 PM PST 24 |
694994800 ps |
| T1169 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.2233712186 |
|
|
Feb 29 01:33:18 PM PST 24 |
Feb 29 01:33:35 PM PST 24 |
144021700 ps |
| T1170 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.572161596 |
|
|
Feb 29 01:34:04 PM PST 24 |
Feb 29 01:34:18 PM PST 24 |
17138400 ps |
| T1171 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.2618777499 |
|
|
Feb 29 01:34:20 PM PST 24 |
Feb 29 01:34:34 PM PST 24 |
43180500 ps |
| T264 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.1204069450 |
|
|
Feb 29 01:34:03 PM PST 24 |
Feb 29 01:34:20 PM PST 24 |
197380000 ps |
| T1172 |
/workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.2672982763 |
|
|
Feb 29 01:34:42 PM PST 24 |
Feb 29 01:34:56 PM PST 24 |
18063200 ps |
| T1173 |
/workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.1175121710 |
|
|
Feb 29 01:34:37 PM PST 24 |
Feb 29 01:34:51 PM PST 24 |
30927400 ps |
| T1174 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.2621640278 |
|
|
Feb 29 01:33:08 PM PST 24 |
Feb 29 01:33:25 PM PST 24 |
13173200 ps |
| T1175 |
/workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.1343644140 |
|
|
Feb 29 01:34:38 PM PST 24 |
Feb 29 01:34:51 PM PST 24 |
17102600 ps |
| T1176 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.1094648933 |
|
|
Feb 29 01:33:49 PM PST 24 |
Feb 29 01:34:04 PM PST 24 |
215965200 ps |
| T268 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.3714432763 |
|
|
Feb 29 01:34:20 PM PST 24 |
Feb 29 01:34:37 PM PST 24 |
35807500 ps |
| T1177 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.1107670040 |
|
|
Feb 29 01:34:26 PM PST 24 |
Feb 29 01:34:43 PM PST 24 |
35678800 ps |
| T313 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.1250460193 |
|
|
Feb 29 01:33:39 PM PST 24 |
Feb 29 01:33:56 PM PST 24 |
92880700 ps |
| T1178 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.3480462621 |
|
|
Feb 29 01:34:16 PM PST 24 |
Feb 29 01:34:32 PM PST 24 |
61716900 ps |
| T356 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.3948413550 |
|
|
Feb 29 01:34:05 PM PST 24 |
Feb 29 01:41:43 PM PST 24 |
351291700 ps |
| T1179 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.3398797732 |
|
|
Feb 29 01:34:31 PM PST 24 |
Feb 29 01:34:47 PM PST 24 |
14218800 ps |
| T1180 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.1041882225 |
|
|
Feb 29 01:34:16 PM PST 24 |
Feb 29 01:34:32 PM PST 24 |
13031100 ps |
| T1181 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.40316990 |
|
|
Feb 29 01:34:04 PM PST 24 |
Feb 29 01:34:18 PM PST 24 |
21812300 ps |
| T359 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.229374806 |
|
|
Feb 29 01:34:27 PM PST 24 |
Feb 29 01:42:06 PM PST 24 |
681413800 ps |
| T1182 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.2297625843 |
|
|
Feb 29 01:34:41 PM PST 24 |
Feb 29 01:34:58 PM PST 24 |
81059000 ps |
| T1183 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.3816586492 |
|
|
Feb 29 01:34:39 PM PST 24 |
Feb 29 01:34:55 PM PST 24 |
85235600 ps |
| T1184 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.2126224282 |
|
|
Feb 29 01:33:47 PM PST 24 |
Feb 29 01:34:01 PM PST 24 |
26461600 ps |
| T276 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.731904701 |
|
|
Feb 29 01:33:51 PM PST 24 |
Feb 29 01:34:11 PM PST 24 |
402023700 ps |
| T1185 |
/workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.2913168933 |
|
|
Feb 29 01:34:38 PM PST 24 |
Feb 29 01:34:51 PM PST 24 |
29327400 ps |
| T1186 |
/workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.3202957843 |
|
|
Feb 29 01:34:40 PM PST 24 |
Feb 29 01:34:53 PM PST 24 |
32145900 ps |
| T1187 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.2942985562 |
|
|
Feb 29 01:34:16 PM PST 24 |
Feb 29 01:34:51 PM PST 24 |
155446100 ps |
| T1188 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.2245326104 |
|
|
Feb 29 01:34:27 PM PST 24 |
Feb 29 01:34:46 PM PST 24 |
314475400 ps |
| T314 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.1874116008 |
|
|
Feb 29 01:34:04 PM PST 24 |
Feb 29 01:34:21 PM PST 24 |
75928200 ps |
| T1189 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.3352704682 |
|
|
Feb 29 01:34:27 PM PST 24 |
Feb 29 01:34:41 PM PST 24 |
58175400 ps |
| T1190 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.3623020172 |
|
|
Feb 29 01:33:38 PM PST 24 |
Feb 29 01:34:02 PM PST 24 |
2505268700 ps |
| T271 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.1744197160 |
|
|
Feb 29 01:34:26 PM PST 24 |
Feb 29 01:34:47 PM PST 24 |
63545800 ps |
| T1191 |
/workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.536578787 |
|
|
Feb 29 01:34:37 PM PST 24 |
Feb 29 01:34:51 PM PST 24 |
68416600 ps |
| T236 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.1934362471 |
|
|
Feb 29 01:33:38 PM PST 24 |
Feb 29 01:33:53 PM PST 24 |
30049900 ps |
| T1192 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.1485227892 |
|
|
Feb 29 01:33:40 PM PST 24 |
Feb 29 01:34:47 PM PST 24 |
2187243200 ps |
| T1193 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.166992884 |
|
|
Feb 29 01:33:50 PM PST 24 |
Feb 29 01:34:03 PM PST 24 |
21248400 ps |
| T357 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.915970014 |
|
|
Feb 29 01:34:16 PM PST 24 |
Feb 29 01:41:43 PM PST 24 |
650961800 ps |
| T1194 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.1525033138 |
|
|
Feb 29 01:33:39 PM PST 24 |
Feb 29 01:33:55 PM PST 24 |
18822800 ps |
| T1195 |
/workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.2353202168 |
|
|
Feb 29 01:34:37 PM PST 24 |
Feb 29 01:34:50 PM PST 24 |
17046800 ps |
| T266 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.1744925507 |
|
|
Feb 29 01:33:11 PM PST 24 |
Feb 29 01:48:05 PM PST 24 |
769308100 ps |
| T315 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.971436174 |
|
|
Feb 29 01:34:37 PM PST 24 |
Feb 29 01:34:58 PM PST 24 |
204965500 ps |
| T1196 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.3545243562 |
|
|
Feb 29 01:33:33 PM PST 24 |
Feb 29 01:33:49 PM PST 24 |
14276900 ps |
| T1197 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.3761038662 |
|
|
Feb 29 01:34:29 PM PST 24 |
Feb 29 01:34:49 PM PST 24 |
160141900 ps |
| T316 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.1119203725 |
|
|
Feb 29 01:34:16 PM PST 24 |
Feb 29 01:34:36 PM PST 24 |
104067200 ps |
| T265 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.1758198475 |
|
|
Feb 29 01:33:38 PM PST 24 |
Feb 29 01:33:59 PM PST 24 |
52313900 ps |
| T1198 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.58542262 |
|
|
Feb 29 01:34:16 PM PST 24 |
Feb 29 01:34:35 PM PST 24 |
119304100 ps |
| T1199 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.2683119226 |
|
|
Feb 29 01:33:48 PM PST 24 |
Feb 29 01:34:02 PM PST 24 |
45616400 ps |
| T1200 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.4086305162 |
|
|
Feb 29 01:33:16 PM PST 24 |
Feb 29 01:40:49 PM PST 24 |
404964100 ps |
| T1201 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.790423331 |
|
|
Feb 29 01:34:03 PM PST 24 |
Feb 29 01:34:18 PM PST 24 |
104097900 ps |
| T1202 |
/workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.253786534 |
|
|
Feb 29 01:34:36 PM PST 24 |
Feb 29 01:34:50 PM PST 24 |
52256900 ps |
| T1203 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.3702106605 |
|
|
Feb 29 01:34:31 PM PST 24 |
Feb 29 01:34:46 PM PST 24 |
22980000 ps |
| T1204 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.1999793975 |
|
|
Feb 29 01:34:25 PM PST 24 |
Feb 29 01:34:44 PM PST 24 |
205883500 ps |
| T1205 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.465339079 |
|
|
Feb 29 01:34:14 PM PST 24 |
Feb 29 01:34:33 PM PST 24 |
135275200 ps |
| T1206 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.3481939102 |
|
|
Feb 29 01:34:18 PM PST 24 |
Feb 29 01:34:48 PM PST 24 |
123833000 ps |
| T1207 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.3801222415 |
|
|
Feb 29 01:33:40 PM PST 24 |
Feb 29 01:33:56 PM PST 24 |
22039400 ps |
| T1208 |
/workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.1980707337 |
|
|
Feb 29 01:34:36 PM PST 24 |
Feb 29 01:34:49 PM PST 24 |
17297900 ps |
| T1209 |
/workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.2704735602 |
|
|
Feb 29 01:34:42 PM PST 24 |
Feb 29 01:34:56 PM PST 24 |
30885900 ps |
| T1210 |
/workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.2493855814 |
|
|
Feb 29 01:34:38 PM PST 24 |
Feb 29 01:34:51 PM PST 24 |
85498700 ps |
| T1211 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.545764132 |
|
|
Feb 29 01:33:28 PM PST 24 |
Feb 29 01:33:43 PM PST 24 |
41054700 ps |
| T1212 |
/workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.2956193027 |
|
|
Feb 29 01:34:35 PM PST 24 |
Feb 29 01:34:49 PM PST 24 |
29501000 ps |
| T1213 |
/workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.1376884642 |
|
|
Feb 29 01:34:36 PM PST 24 |
Feb 29 01:34:50 PM PST 24 |
17511500 ps |
| T1214 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.1721065173 |
|
|
Feb 29 01:33:41 PM PST 24 |
Feb 29 01:34:20 PM PST 24 |
720849100 ps |
| T1215 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.647547988 |
|
|
Feb 29 01:34:18 PM PST 24 |
Feb 29 01:34:33 PM PST 24 |
54029100 ps |
| T354 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.1933959640 |
|
|
Feb 29 01:34:25 PM PST 24 |
Feb 29 01:49:19 PM PST 24 |
809475900 ps |
| T269 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.2554650875 |
|
|
Feb 29 01:33:48 PM PST 24 |
Feb 29 01:48:45 PM PST 24 |
1381954900 ps |
| T1216 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.547554231 |
|
|
Feb 29 01:33:40 PM PST 24 |
Feb 29 01:41:20 PM PST 24 |
1663476400 ps |
| T1217 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.4139520457 |
|
|
Feb 29 01:33:40 PM PST 24 |
Feb 29 01:33:53 PM PST 24 |
17869100 ps |
| T1218 |
/workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.188135673 |
|
|
Feb 29 01:34:38 PM PST 24 |
Feb 29 01:34:52 PM PST 24 |
99537000 ps |
| T1219 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.975300442 |
|
|
Feb 29 01:34:04 PM PST 24 |
Feb 29 01:34:18 PM PST 24 |
36580400 ps |
| T1220 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.3435577812 |
|
|
Feb 29 01:33:18 PM PST 24 |
Feb 29 01:33:35 PM PST 24 |
132917900 ps |
| T1221 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.767326332 |
|
|
Feb 29 01:33:47 PM PST 24 |
Feb 29 01:34:10 PM PST 24 |
1229249300 ps |
| T1222 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.1969062924 |
|
|
Feb 29 01:34:18 PM PST 24 |
Feb 29 01:34:34 PM PST 24 |
86287300 ps |
| T237 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.1938322879 |
|
|
Feb 29 01:33:20 PM PST 24 |
Feb 29 01:33:34 PM PST 24 |
204067400 ps |
| T1223 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.931091795 |
|
|
Feb 29 01:33:27 PM PST 24 |
Feb 29 01:33:45 PM PST 24 |
32266700 ps |
| T1224 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.3223447063 |
|
|
Feb 29 01:33:33 PM PST 24 |
Feb 29 01:34:06 PM PST 24 |
849989800 ps |
| T1225 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.854033881 |
|
|
Feb 29 01:33:26 PM PST 24 |
Feb 29 01:33:40 PM PST 24 |
48996300 ps |
| T273 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.4255615128 |
|
|
Feb 29 01:33:30 PM PST 24 |
Feb 29 01:33:49 PM PST 24 |
275606500 ps |
| T1226 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.134321660 |
|
|
Feb 29 01:33:18 PM PST 24 |
Feb 29 01:33:33 PM PST 24 |
23851400 ps |
| T272 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.3601660087 |
|
|
Feb 29 01:34:25 PM PST 24 |
Feb 29 01:34:45 PM PST 24 |
243857500 ps |
| T1227 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.169291900 |
|
|
Feb 29 01:33:27 PM PST 24 |
Feb 29 01:33:43 PM PST 24 |
124491000 ps |
| T278 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.900304719 |
|
|
Feb 29 01:33:50 PM PST 24 |
Feb 29 01:34:06 PM PST 24 |
30639000 ps |
| T274 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.1995017620 |
|
|
Feb 29 01:34:15 PM PST 24 |
Feb 29 01:34:34 PM PST 24 |
49430600 ps |
| T277 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.2631664640 |
|
|
Feb 29 01:33:40 PM PST 24 |
Feb 29 01:33:59 PM PST 24 |
56700600 ps |
| T1228 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.476256128 |
|
|
Feb 29 01:34:17 PM PST 24 |
Feb 29 01:34:35 PM PST 24 |
104929200 ps |
| T1229 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.890733703 |
|
|
Feb 29 01:33:53 PM PST 24 |
Feb 29 01:34:06 PM PST 24 |
54434500 ps |
| T1230 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.1532565972 |
|
|
Feb 29 01:34:30 PM PST 24 |
Feb 29 01:34:46 PM PST 24 |
13100000 ps |
| T1231 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.4063899406 |
|
|
Feb 29 01:34:16 PM PST 24 |
Feb 29 01:34:33 PM PST 24 |
66516800 ps |
| T1232 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.1264355744 |
|
|
Feb 29 01:34:16 PM PST 24 |
Feb 29 01:34:35 PM PST 24 |
164796100 ps |
| T1233 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.3662795964 |
|
|
Feb 29 01:34:04 PM PST 24 |
Feb 29 01:34:22 PM PST 24 |
118397200 ps |
| T275 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.733215187 |
|
|
Feb 29 01:34:05 PM PST 24 |
Feb 29 01:34:24 PM PST 24 |
219337600 ps |
| T1234 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.2327296590 |
|
|
Feb 29 01:33:17 PM PST 24 |
Feb 29 01:33:33 PM PST 24 |
77618900 ps |
| T1235 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.3781901413 |
|
|
Feb 29 01:33:09 PM PST 24 |
Feb 29 01:33:24 PM PST 24 |
37251700 ps |
| T1236 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.3701012685 |
|
|
Feb 29 01:34:17 PM PST 24 |
Feb 29 01:34:36 PM PST 24 |
29939200 ps |
| T1237 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.802554125 |
|
|
Feb 29 01:34:25 PM PST 24 |
Feb 29 01:34:40 PM PST 24 |
65551700 ps |
| T1238 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.2228196793 |
|
|
Feb 29 01:34:27 PM PST 24 |
Feb 29 01:34:41 PM PST 24 |
35193900 ps |
| T1239 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.3087419688 |
|
|
Feb 29 01:33:32 PM PST 24 |
Feb 29 01:33:49 PM PST 24 |
85375400 ps |
| T1240 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.3770359627 |
|
|
Feb 29 01:34:26 PM PST 24 |
Feb 29 01:34:40 PM PST 24 |
72529100 ps |
| T1241 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.1250729457 |
|
|
Feb 29 01:34:28 PM PST 24 |
Feb 29 01:34:46 PM PST 24 |
111884300 ps |
| T1242 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.2816911499 |
|
|
Feb 29 01:33:39 PM PST 24 |
Feb 29 01:34:36 PM PST 24 |
1823516500 ps |
| T1243 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.428239418 |
|
|
Feb 29 01:33:49 PM PST 24 |
Feb 29 01:34:04 PM PST 24 |
43453000 ps |
| T353 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.866480830 |
|
|
Feb 29 01:34:17 PM PST 24 |
Feb 29 01:49:20 PM PST 24 |
1345439900 ps |
| T1244 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.1411524230 |
|
|
Feb 29 01:34:15 PM PST 24 |
Feb 29 01:34:31 PM PST 24 |
52779000 ps |
| T1245 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.618615103 |
|
|
Feb 29 01:33:17 PM PST 24 |
Feb 29 01:33:34 PM PST 24 |
41835100 ps |
| T1246 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.4140474220 |
|
|
Feb 29 01:33:26 PM PST 24 |
Feb 29 01:33:40 PM PST 24 |
141881300 ps |
| T1247 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.590507877 |
|
|
Feb 29 01:33:49 PM PST 24 |
Feb 29 01:34:05 PM PST 24 |
121542100 ps |
| T1248 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.3209228230 |
|
|
Feb 29 01:33:43 PM PST 24 |
Feb 29 01:34:03 PM PST 24 |
114147500 ps |
| T1249 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.575161932 |
|
|
Feb 29 01:33:18 PM PST 24 |
Feb 29 01:34:00 PM PST 24 |
5579828700 ps |
| T1250 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.515171202 |
|
|
Feb 29 01:34:17 PM PST 24 |
Feb 29 01:34:30 PM PST 24 |
53397200 ps |
| T1251 |
/workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.903473673 |
|
|
Feb 29 01:34:42 PM PST 24 |
Feb 29 01:34:55 PM PST 24 |
70624700 ps |
| T1252 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.384241021 |
|
|
Feb 29 01:33:29 PM PST 24 |
Feb 29 01:34:15 PM PST 24 |
88131800 ps |